; Assembly listing for method System.Runtime.CompilerServices.CastHelpers:StelemRef(System.Array,long,System.Object) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 2 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w3, [x0, #0x08] cmp x1, x3 bhs G_M000_IG10 lsl x1, x1, #3 add x1, x1, #16 add x3, x0, x1 ldr x1, [x0] ldr x1, [x1, #0x30] cbz x2, G_M000_IG06 G_M000_IG03: ldr x4, [x2] cmp x1, x4 bne G_M000_IG08 G_M000_IG04: mov x0, x3 mov x1, x2 G_M000_IG05: ldp fp, lr, [sp], #0x10 b System.Runtime.CompilerServices.CastHelpers:WriteBarrier(byref,System.Object) G_M000_IG06: str xzr, [x3] G_M000_IG07: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG08: ldr x0, [x0] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 cmp x0, x4 beq G_M000_IG04 mov x0, x3 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG09: ldp fp, lr, [sp], #0x10 br x3 G_M000_IG10: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 144 1: JIT compiled System.Runtime.CompilerServices.CastHelpers:StelemRef(System.Array,long,System.Object) [Tier1, IL size=88, code size=144] ; Assembly listing for method System.Runtime.CompilerServices.CastHelpers:LdelemaRef(System.Array,long,ulong):byref ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w3, [x0, #0x08] cmp x1, x3 bhs G_M000_IG05 lsl x1, x1, #3 add x1, x1, #16 add x1, x0, x1 ldr x0, [x0] ldr x0, [x0, #0x30] cmp x0, x2 bne G_M000_IG04 mov x0, x1 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG05: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 88 2: JIT compiled System.Runtime.CompilerServices.CastHelpers:LdelemaRef(System.Array,long,ulong) [Tier1, IL size=44, code size=88] ; Assembly listing for method System.SpanHelpers:IndexOfNullCharacter(ulong):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 2 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov x1, xzr mov x2, #0xD1FFAB1E tbnz w0, #0, G_M000_IG04 G_M000_IG03: neg w2, w0 add w2, w2, w2, LSR #31 asr w2, w2, #1 mov w2, w2 and x2, x2, #7 G_M000_IG04: cmp x2, #4 blt G_M000_IG06 align [0 bytes for IG05] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG05: lsl x3, x1, #1 ldrh w4, [x0, x3] cbz w4, G_M000_IG15 add x4, x0, x3 ldrh w4, [x4, #0x02] cbz w4, G_M000_IG14 add x4, x0, x3 ldrh w4, [x4, #0x04] cbz w4, G_M000_IG13 add x3, x0, x3 ldrh w3, [x3, #0x06] cbz w3, G_M000_IG12 add x1, x1, #4 sub x2, x2, #4 cmp x2, #4 bge G_M000_IG05 G_M000_IG06: cmp x2, #0 ble G_M000_IG08 align [4 bytes for IG07] align [4 bytes] align [0 bytes] align [0 bytes] G_M000_IG07: lsl x3, x1, #1 ldrh w3, [x0, x3] cbz w3, G_M000_IG15 add x1, x1, #1 sub x2, x2, #1 cmp x2, #0 bgt G_M000_IG07 G_M000_IG08: mov x2, #0xD1FFAB1E cmp x1, x2 bge G_M000_IG17 neg x2, x1 mov x3, #0xD1FFAB1E add x2, x2, x3 and x2, x2, #-8 cmp x2, #0 ble G_M000_IG10 align [0 bytes for IG09] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG09: lsl x3, x1, #1 ldr q16, [x0, x3] cmeq v16.8h, v16.8h, #0 umaxp v17.4s, v16.4s, v16.4s umov x3, v17.d[0] cmp x3, #0 bne G_M000_IG11 add x1, x1, #8 sub x2, x2, #8 cmp x2, #0 bgt G_M000_IG09 G_M000_IG10: mov x2, #0xD1FFAB1E cmp x1, x2 bge G_M000_IG17 neg x2, x1 mov x3, #0xD1FFAB1E add x2, x2, x3 b G_M000_IG04 G_M000_IG11: ldr q17, [@RWD00] and v16.16b, v16.16b, v17.16b ldr q17, [@RWD16] ushl v16.16b, v16.16b, v17.16b mov v17.16b, v16.16b addv b17, v17.8b umov w0, v17.b[0] ext v16.16b, v16.16b, v16.16b, #8 addv b16, v16.8b umov w2, v16.b[0] orr w0, w0, w2, LSL #8 rbit w0, w0 clz w0, w0 lsr w0, w0, #1 mov w0, w0 add w1, w0, w1 b G_M000_IG15 G_M000_IG12: add w1, w1, #3 b G_M000_IG15 G_M000_IG13: add w1, w1, #2 b G_M000_IG15 G_M000_IG14: add w1, w1, #1 b G_M000_IG15 G_M000_IG15: mov w0, w1 G_M000_IG16: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG17: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 RWD00 dq 8080808080808080h, 8080808080808080h RWD16 dq 00FFFEFDFCFBFAF9h, 00FFFEFDFCFBFAF9h ; Total bytes of code 392 3: JIT compiled System.SpanHelpers:IndexOfNullCharacter(ulong) [Tier1, IL size=492, code size=392] ; Assembly listing for method System.Guid:TryFormatCore[ushort](System.Span`1[ushort],byref,int):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! mov fp, sp str xzr, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] str x1, [fp, #0xD1FFAB1E] str x2, [fp, #0xD1FFAB1E] str x3, [fp, #0xD1FFAB1E] str w4, [fp, #0xD1FFAB1E] G_M000_IG02: ldr w0, [fp, #0xD1FFAB1E] uxtb w0, w0 ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 ble G_M000_IG04 ldr x0, [fp, #0xD1FFAB1E] str wzr, [x0] mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0xD1FFAB1E ret lr G_M000_IG04: ldr w0, [fp, #0xD1FFAB1E] uxtb w0, w0 ldr x1, [fp, #0xD1FFAB1E] str w0, [x1] ldr w0, [fp, #0xD1FFAB1E] asr w0, w0, #8 str w0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x18] ldr x0, [fp, #0x18] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] uxtb w0, w0 cbz w0, G_M000_IG05 ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] mov w1, #2 sxtw x1, w1 add x0, x0, x1 str x0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] uxtb w0, w0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0xD1FFAB1E] strh w0, [x1] G_M000_IG05: ldr w0, [fp, #0xD1FFAB1E] asr w0, w0, #8 str w0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0] ldr x1, [fp, #0xD1FFAB1E] ldr x1, [x1, #0x08] ldr w2, [fp, #0xD1FFAB1E] cmp w2, #0 cset x2, lt movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str q0, [fp, #0x80] str q1, [fp, #0x90] str q2, [fp, #0xA0] ldr q0, [fp, #0x80] str q0, [fp, #0xD1FFAB1E] ldr q0, [fp, #0x90] str q0, [fp, #0xD1FFAB1E] ldr q0, [fp, #0xA0] str q0, [fp, #0xD1FFAB1E] b G_M000_IG06 G_M000_IG06: ldr q0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str q0, [fp, #0x60] str q1, [fp, #0x70] ldr q0, [fp, #0x60] str q0, [fp, #0xD1FFAB1E] ldr q0, [fp, #0x70] str q0, [fp, #0xD1FFAB1E] ldr q0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str q0, [fp, #0x40] str q1, [fp, #0x50] ldr q0, [fp, #0x40] str q0, [fp, #0xF0] ldr q0, [fp, #0x50] str q0, [fp, #0xE0] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD8] ldr w0, [fp, #0xD1FFAB1E] tbz w0, #31, G_M000_IG07 ldr q0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str q0, [fp, #0x20] str q1, [fp, #0x30] ldr q16, [fp, #0x20] str q16, [fp, #0xC0] ldr q16, [fp, #0x30] str q16, [fp, #0xB0] ldr x0, [fp, #0xD8] ldr q16, [fp, #0xD1FFAB1E] str q16, [x0] ldr x0, [fp, #0xD8] mov w1, #2 sxtw x1, w1 mov x2, #20 mul x1, x1, x2 ldr q16, [fp, #0xF0] str q16, [x0, x1] ldr x0, [fp, #0xD8] mov w1, #2 sxtw x1, w1 mov x2, #28 mul x1, x1, x2 ldr q16, [fp, #0xE0] str q16, [x0, x1] ldr x0, [fp, #0xD8] mov w1, #2 sxtw x1, w1 lsl x1, x1, #3 ldr q16, [fp, #0xC0] str q16, [x0, x1] ldr x0, [fp, #0xD8] mov w1, #2 sxtw x1, w1 lsl x1, x1, #4 ldr q16, [fp, #0xB0] str q16, [x0, x1] ldr x0, [fp, #0xD1FFAB1E] mov w1, #2 sxtw x1, w1 mov x2, #36 mul x1, x1, x2 add x0, x0, x1 str x0, [fp, #0xD1FFAB1E] b G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0xD8] ldr q16, [fp, #0xD1FFAB1E] str q16, [x0] ldr x0, [fp, #0xD8] mov w1, #2 sxtw x1, w1 lsl x1, x1, #3 ldr q16, [fp, #0xD1FFAB1E] str q16, [x0, x1] ldr x0, [fp, #0xD8] mov w1, #2 sxtw x1, w1 lsl x1, x1, #4 ldr q16, [fp, #0xF0] str q16, [x0, x1] ldr x0, [fp, #0xD8] mov w1, #2 sxtw x1, w1 mov x2, #24 mul x1, x1, x2 ldr q16, [fp, #0xE0] str q16, [x0, x1] ldr x0, [fp, #0xD1FFAB1E] mov w1, #2 sxtw x1, w1 lsl x1, x1, #5 add x0, x0, x1 str x0, [fp, #0xD1FFAB1E] b G_M000_IG08 G_M000_IG08: ldr w0, [fp, #0xD1FFAB1E] uxtb w0, w0 cbz w0, G_M000_IG09 ldr w0, [fp, #0xD1FFAB1E] uxtb w0, w0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0xD1FFAB1E] strh w0, [x1] G_M000_IG09: str xzr, [fp, #0xD1FFAB1E] mov w0, #1 G_M000_IG10: ldp fp, lr, [sp], #0xD1FFAB1E ret lr ; Total bytes of code 820 4: JIT compiled System.Guid:TryFormatCore[ushort](System.Span`1[ushort],byref,int) [Tier0, IL size=893, code size=820] ; Assembly listing for method System.Guid:FormatGuidVector128Utf8(System.Guid,bool):System.ValueTuple`3[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! mov fp, sp str x0, [fp, #0xD1FFAB1E] str x1, [fp, #0xD1FFAB1E] str w2, [fp, #0xD1FFAB1E] G_M000_IG02: ldr q0, [@RWD00] str q0, [fp, #0xD1FFAB1E] ldr q0, [fp, #0xD1FFAB1E] str q0, [fp, #0xD1FFAB1E] ldr q0, [fp, #0xD1FFAB1E] ldr q1, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str q0, [fp, #0x70] str q1, [fp, #0x80] ldr q0, [fp, #0x70] str q0, [fp, #0xD1FFAB1E] ldr q0, [fp, #0x80] str q0, [fp, #0xD1FFAB1E] ldr q0, [fp, #0xD1FFAB1E] mov v0.16b, v0.16b ldr q1, [@RWD16] tbl v0.16b, {v0.16b}, v1.16b str q0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] uxtb w0, w0 cbz w0, G_M000_IG04 ldr q0, [fp, #0xD1FFAB1E] mov v0.16b, v0.16b ldr q1, [@RWD32] tbl v0.16b, {v0.16b}, v1.16b str q0, [fp, #0xF0] ldr q0, [fp, #0xD1FFAB1E] mov v0.16b, v0.16b ldr q1, [@RWD48] tbl v0.16b, {v0.16b}, v1.16b str q0, [fp, #0xE0] ldr q0, [fp, #0xD1FFAB1E] mov v0.16b, v0.16b ldr q1, [@RWD64] tbl v0.16b, {v0.16b}, v1.16b str q0, [fp, #0xD0] ldr q0, [fp, #0xD1FFAB1E] mov v0.16b, v0.16b ldr q1, [@RWD80] tbl v0.16b, {v0.16b}, v1.16b str q0, [fp, #0xC0] ldr q0, [@RWD96] mov v0.16b, v0.16b ldr q1, [@RWD112] tbl v0.16b, {v0.16b}, v1.16b str q0, [fp, #0xB0] ldr q0, [fp, #0xD0] ldr q1, [fp, #0xC0] orr v0.16b, v0.16b, v1.16b ldr q1, [fp, #0xB0] orr v0.16b, v0.16b, v1.16b str q0, [fp, #0xA0] stp xzr, xzr, [fp, #0x10] stp xzr, xzr, [fp, #0x20] stp xzr, xzr, [fp, #0x30] add x0, fp, #16 ldr q0, [fp, #0xF0] ldr q1, [fp, #0xE0] ldr q2, [fp, #0xA0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr q0, [fp, #0x10] ldr q1, [fp, #0x20] ldr q2, [fp, #0x30] G_M000_IG03: ldp fp, lr, [sp], #0xD1FFAB1E ret lr G_M000_IG04: movi v0.4s, #0 str q0, [fp, #0x90] stp xzr, xzr, [fp, #0x40] stp xzr, xzr, [fp, #0x50] stp xzr, xzr, [fp, #0x60] add x0, fp, #64 ldr q0, [fp, #0xD1FFAB1E] ldr q1, [fp, #0xD1FFAB1E] ldr q2, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr q0, [fp, #0x40] ldr q1, [fp, #0x50] ldr q2, [fp, #0x60] G_M000_IG05: ldp fp, lr, [sp], #0xD1FFAB1E ret lr RWD00 dq 3736353433323130h, 6665646362613938h RWD16 dq 0100030205040706h, 0D0C0F0E09080B0Ah RWD32 dq 0706050403020100h, 0D0CFF0B0A0908FFh RWD48 dq 07060504FF030201h, 0F0E0D0C0B0A0908h RWD64 dq 0D0CFF0B0A0908FFh, FFFFFFFFFFFF0F0Eh RWD80 dq FFFFFFFFFFFFFFFFh, FF03020100FFFFFFh RWD96 dq 2D2D2D2D2D2D2D2Dh, 2D2D2D2D2D2D2D2Dh RWD112 dq FFFF00FFFFFFFF00h, 00FFFFFFFF00FFFFh ; Total bytes of code 388 5: JIT compiled System.Guid:FormatGuidVector128Utf8(System.Guid,bool) [Tier0, IL size=331, code size=388] ; Assembly listing for method System.HexConverter:AsciiToHexVector128(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.ValueTuple`2[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! mov fp, sp str q0, [fp, #0x90] str q1, [fp, #0x80] G_M000_IG02: ldr q0, [fp, #0x90] ushr v0.2d, v0.2d, #4 str q0, [fp, #0x70] ldr q0, [fp, #0x70] ldr q1, [fp, #0x90] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str q0, [fp, #0x60] ldr q0, [fp, #0x70] ldr q1, [fp, #0x90] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str q0, [fp, #0x50] ldr q1, [fp, #0x60] ldr q0, [@RWD00] and v1.16b, v1.16b, v0.16b ldr q0, [fp, #0x80] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str q0, [fp, #0x40] stp xzr, xzr, [fp, #0x20] stp xzr, xzr, [fp, #0x30] ldr q1, [fp, #0x50] ldr q0, [@RWD00] and v1.16b, v1.16b, v0.16b ldr q0, [fp, #0x80] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str q0, [fp, #0x10] add x0, fp, #32 ldr q0, [fp, #0x40] ldr q1, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr q0, [fp, #0x20] ldr q1, [fp, #0x30] G_M000_IG03: ldp fp, lr, [sp], #0xA0 ret lr RWD00 dq 0F0F0F0F0F0F0F0Fh, 0F0F0F0F0F0F0F0Fh ; Total bytes of code 228 6: JIT compiled System.HexConverter:AsciiToHexVector128(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]) [Tier0, IL size=78, code size=228] ; Assembly listing for method System.Runtime.Intrinsics.Vector128:UnpackLow(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str q0, [fp, #0x20] str q1, [fp, #0x10] G_M000_IG02: b G_M000_IG03 G_M000_IG03: b G_M000_IG04 G_M000_IG04: ldr q0, [fp, #0x20] ldr q16, [fp, #0x10] zip1 v0.16b, v0.16b, v16.16b G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 44 7: JIT compiled System.Runtime.Intrinsics.Vector128:UnpackLow(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]) [Tier0, IL size=23, code size=44] ; Assembly listing for method System.Runtime.Intrinsics.Vector128:UnpackHigh(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str q0, [fp, #0x20] str q1, [fp, #0x10] G_M000_IG02: b G_M000_IG03 G_M000_IG03: b G_M000_IG04 G_M000_IG04: ldr q0, [fp, #0x20] ldr q16, [fp, #0x10] zip2 v0.16b, v0.16b, v16.16b G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 44 8: JIT compiled System.Runtime.Intrinsics.Vector128:UnpackHigh(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]) [Tier0, IL size=23, code size=44] ; Assembly listing for method System.Runtime.Intrinsics.Vector128:ShuffleUnsafe(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str q0, [fp, #0x20] str q1, [fp, #0x10] G_M000_IG02: b G_M000_IG03 G_M000_IG03: ldr q0, [fp, #0x20] ldr q16, [fp, #0x10] tbl v0.16b, {v0.16b}, v16.16b G_M000_IG04: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 40 9: JIT compiled System.Runtime.Intrinsics.Vector128:ShuffleUnsafe(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]) [Tier0, IL size=41, code size=40] ; Assembly listing for method System.ValueTuple`3[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:.ctor(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str x0, [fp, #0x48] str q0, [fp, #0x30] str q1, [fp, #0x20] str q2, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x48] ldr q16, [fp, #0x30] str q16, [x0] ldr x0, [fp, #0x48] ldr q16, [fp, #0x20] str q16, [x0, #0x10] ldr x0, [fp, #0x48] ldr q16, [fp, #0x10] str q16, [x0, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 68 10: JIT compiled System.ValueTuple`3[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]:.ctor(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]) [Tier0, IL size=22, code size=68] ; Assembly listing for method System.Number:UInt32ToDecChars[ushort](ulong,uint):ulong ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str w1, [fp, #0x34] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x18] ldr w0, [fp, #0x34] cmp w0, #10 blo G_M000_IG08 b G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x38] mov w1, #2 sxtw x1, w1 lsl x1, x1, #1 sub x0, x0, x1 str x0, [fp, #0x38] ldr w0, [fp, #0x34] mov w1, #100 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x20] ldr w0, [fp, #0x20] str w0, [fp, #0x34] ldr w0, [fp, #0x24] str w0, [fp, #0x30] ldr w0, [fp, #0x30] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG04: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG06 G_M000_IG05: add x0, fp, #24 mov w1, #49 bl CORINFO_HELP_PATCHPOINT G_M000_IG06: ldr w0, [fp, #0x34] cmp w0, #100 bhs G_M000_IG03 ldr w0, [fp, #0x34] cmp w0, #10 blo G_M000_IG08 ldr x0, [fp, #0x38] mov w1, #2 sxtw x1, w1 lsl x1, x1, #1 sub x0, x0, x1 str x0, [fp, #0x38] ldr w0, [fp, #0x34] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x38] G_M000_IG07: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG08: ldr x0, [fp, #0x38] mov w1, #2 sxtw x1, w1 sub x0, x0, x1 str x0, [fp, #0x28] ldr x0, [fp, #0x28] str x0, [fp, #0x38] ldr w0, [fp, #0x34] add w0, w0, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x28] strh w0, [x1] ldr x0, [fp, #0x38] G_M000_IG09: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 340 11: JIT compiled System.Number:UInt32ToDecChars[ushort](ulong,uint) [Tier0, IL size=114, code size=340] ; Assembly listing for method System.Number:WriteTwoDigits[ushort](uint,ulong) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str w0, [fp, #0x3C] str x1, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x30] str x0, [fp, #0x28] b G_M000_IG03 G_M000_IG03: ldr x0, [fp, #0x28] str x0, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w1, [fp, #0x3C] mov w2, #2 lsl w2, w2, #1 mul w1, w1, w2 mov w1, w1 add x1, x0, x1 str x1, [fp, #0x10] ldr x1, [fp, #0x10] mov w2, #2 lsl w2, w2, #1 ldr x0, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG04: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 160 12: JIT compiled System.Number:WriteTwoDigits[ushort](uint,ulong) [Tier0, IL size=75, code size=160] ; Assembly listing for method System.ArgumentOutOfRangeException:ThrowIfNegative[int](int,System.String) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str w0, [fp, #0x1C] str x1, [fp, #0x10] G_M000_IG02: ldr w0, [fp, #0x1C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG03 ldr x0, [fp, #0x10] ldr w1, [fp, #0x1C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 80 13: JIT compiled System.ArgumentOutOfRangeException:ThrowIfNegative[int](int,System.String) [Tier0, IL size=22, code size=80] ; Assembly listing for method System.SpanHelpers:IndexOfNullByte(ulong):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 2 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov x1, xzr and w2, w0, #15 neg w2, w2 add w2, w2, #16 and w2, w2, #15 mov w2, w2 G_M000_IG03: cmp x2, #8 blo G_M000_IG05 align [0 bytes for IG04] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG04: sub x2, x2, #8 ldrb w3, [x0, x1] cbz w3, G_M000_IG13 add x3, x0, x1 ldrb w3, [x3, #0x01] cbz w3, G_M000_IG14 add x3, x0, x1 ldrb w3, [x3, #0x02] cbz w3, G_M000_IG15 add x3, x0, x1 ldrb w3, [x3, #0x03] cbz w3, G_M000_IG16 add x3, x0, x1 ldrb w3, [x3, #0x04] cbz w3, G_M000_IG17 add x3, x0, x1 ldrb w3, [x3, #0x05] cbz w3, G_M000_IG18 add x3, x0, x1 ldrb w3, [x3, #0x06] cbz w3, G_M000_IG19 add x3, x0, x1 ldrb w3, [x3, #0x07] cbz w3, G_M000_IG20 add x1, x1, #8 cmp x2, #8 bhs G_M000_IG04 G_M000_IG05: cmp x2, #4 blo G_M000_IG07 G_M000_IG06: sub x2, x2, #4 ldrb w3, [x0, x1] cbz w3, G_M000_IG13 add x3, x0, x1 ldrb w3, [x3, #0x01] cbz w3, G_M000_IG14 add x3, x0, x1 ldrb w3, [x3, #0x02] cbz w3, G_M000_IG15 add x3, x0, x1 ldrb w3, [x3, #0x03] cbz w3, G_M000_IG16 add x1, x1, #4 G_M000_IG07: cbz x2, G_M000_IG09 align [4 bytes for IG08] align [4 bytes] align [4 bytes] align [0 bytes] G_M000_IG08: sub x2, x2, #1 ldrb w3, [x0, x1] cbz w3, G_M000_IG13 add x1, x1, #1 cbnz x2, G_M000_IG08 G_M000_IG09: mov x2, #0xD1FFAB1E cmp x1, x2 bhs G_M000_IG23 neg w2, w1 movn w3, #0xD1FFAB1E LSL #16 add w2, w2, w3 and w2, w2, #0xD1FFAB1E mov w2, w2 cmp x2, x1 bls G_M000_IG11 align [0 bytes for IG10] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG10: ldr q16, [x0, x1] cmeq v16.16b, v16.16b, #0 umaxp v17.4s, v16.4s, v16.4s umov x3, v17.d[0] cmp x3, #0 bne G_M000_IG12 add x1, x1, #16 cmp x2, x1 bhi G_M000_IG10 G_M000_IG11: mov x2, #0xD1FFAB1E cmp x1, x2 bhs G_M000_IG23 neg x2, x1 mov x3, #0xD1FFAB1E add x2, x2, x3 b G_M000_IG03 G_M000_IG12: ldr q17, [@RWD00] and v16.16b, v16.16b, v17.16b ldr q17, [@RWD16] ushl v16.16b, v16.16b, v17.16b mov v17.16b, v16.16b addv b17, v17.8b umov w0, v17.b[0] ext v16.16b, v16.16b, v16.16b, #8 addv b16, v16.8b umov w2, v16.b[0] orr w0, w0, w2, LSL #8 rbit w0, w0 clz w0, w0 mov w0, w0 add w1, w0, w1 b G_M000_IG21 G_M000_IG13: b G_M000_IG21 G_M000_IG14: add w1, w1, #1 b G_M000_IG21 G_M000_IG15: add w1, w1, #2 b G_M000_IG21 G_M000_IG16: add w1, w1, #3 b G_M000_IG21 G_M000_IG17: add w1, w1, #4 b G_M000_IG21 G_M000_IG18: add w1, w1, #5 b G_M000_IG21 G_M000_IG19: add w1, w1, #6 b G_M000_IG21 G_M000_IG20: add w1, w1, #7 G_M000_IG21: mov w0, w1 G_M000_IG22: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG23: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 RWD00 dq 8080808080808080h, 8080808080808080h RWD16 dq 00FFFEFDFCFBFAF9h, 00FFFEFDFCFBFAF9h ; Total bytes of code 504 14: JIT compiled System.SpanHelpers:IndexOfNullByte(ulong) [Tier1, IL size=581, code size=504] ; Assembly listing for method System.SpanHelpers:NonPackedIndexOfValueType[short,System.SpanHelpers+DontNegate`1[short]](byref,short,int):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 30 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: cmp w2, #8 bge G_M000_IG11 G_M000_IG03: mov x3, xzr cmp w2, #4 blt G_M000_IG04 sub w2, w2, #4 lsl x4, x3, #1 ldrsh w5, [x0, x4] sxth w6, w1 cmp w5, w6 beq G_M000_IG10 add x5, x4, #2 ldrsh w5, [x0, x5] cmp w5, w6 beq G_M000_IG09 add x5, x4, #4 ldrsh w5, [x0, x5] cmp w5, w6 beq G_M000_IG08 add x4, x4, #6 ldrsh w4, [x0, x4] cmp w4, w6 beq G_M000_IG07 add x3, x3, #4 G_M000_IG04: cmp w2, #0 ble G_M000_IG17 sxth w6, w1 align [4 bytes for IG05] align [4 bytes] align [4 bytes] align [0 bytes] G_M000_IG05: sub w2, w2, #1 lsl x1, x3, #1 ldrsh w1, [x0, x1] cmp w1, w6 beq G_M000_IG10 add x3, x3, #1 cmp w2, #0 bgt G_M000_IG05 G_M000_IG06: b G_M000_IG17 G_M000_IG07: add w3, w3, #3 b G_M000_IG15 G_M000_IG08: add w3, w3, #2 b G_M000_IG15 G_M000_IG09: add w3, w3, #1 b G_M000_IG15 G_M000_IG10: b G_M000_IG15 G_M000_IG11: sxth w6, w1 dup v16.8h, w6 mov x1, x0 sub w3, w2, #8 sbfiz x3, x3, #1, #32 add x4, x1, x3 align [0 bytes for IG12] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG12: ldr q17, [x1] cmeq v17.8h, v16.8h, v17.8h umaxp v18.4s, v17.4s, v17.4s umov x5, v18.d[0] cmp x5, #0 bne G_M000_IG14 add x1, x1, #16 cmp x1, x4 bls G_M000_IG12 G_M000_IG13: mov w0, w2 tst w0, #7 beq G_M000_IG17 ldr q17, [x4] cmeq v17.8h, v16.8h, v17.8h umaxp v16.4s, v17.4s, v17.4s umov x1, v16.d[0] cmp x1, #0 beq G_M000_IG17 lsr x0, x3, #1 ldr q16, [@RWD00] and v17.8h, v17.8h, v16.8h ldr q16, [@RWD16] ushl v16.8h, v17.8h, v16.8h addv h16, v16.8h umov w1, v16.h[0] rbit w1, w1 clz w1, w1 add w3, w0, w1 b G_M000_IG15 G_M000_IG14: sub x3, x1, x0 lsr x0, x3, #1 ldr q16, [@RWD00] and v16.8h, v17.8h, v16.8h ldr q17, [@RWD16] ushl v16.8h, v16.8h, v17.8h addv h16, v16.8h umov w1, v16.h[0] rbit w1, w1 clz w1, w1 add w3, w0, w1 G_M000_IG15: mov w0, w3 G_M000_IG16: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG17: movn w0, #0 G_M000_IG18: ldp fp, lr, [sp], #0x10 ret lr RWD00 dq 8000800080008000h, 8000800080008000h RWD16 dq FFF4FFF3FFF2FFF1h, FFF8FFF7FFF6FFF5h ; Total bytes of code 400 15: JIT compiled System.SpanHelpers:NonPackedIndexOfValueType[short,System.SpanHelpers+DontNegate`1[short]](byref,short,int) [Tier1, IL size=843, code size=400] ; Assembly listing for method System.Char:System.IUtfChar.CastFrom(uint):ushort ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str w0, [fp, #0x1C] G_M000_IG02: ldr w0, [fp, #0x1C] uxth w0, w0 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 16: JIT compiled System.Char:System.IUtfChar.CastFrom(uint) [Tier0, IL size=3, code size=28] ; Assembly listing for method System.SpanHelpers:LastIndexOfValueType[short,System.SpanHelpers+DontNegate`1[short]](byref,short,int):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 30 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: cmp w2, #8 bge G_M000_IG11 G_M000_IG03: sxtw x3, w2 sub x3, x3, #1 cmp w2, #4 blt G_M000_IG04 sub w2, w2, #4 lsl x4, x3, #1 ldrsh w5, [x0, x4] sxth w6, w1 cmp w5, w6 beq G_M000_IG10 sub x5, x4, #2 ldrsh w5, [x0, x5] cmp w5, w6 beq G_M000_IG09 sub x5, x4, #4 ldrsh w5, [x0, x5] cmp w5, w6 beq G_M000_IG08 sub x4, x4, #6 ldrsh w4, [x0, x4] cmp w4, w6 beq G_M000_IG07 sub x3, x3, #4 G_M000_IG04: cmp w2, #0 ble G_M000_IG17 sxth w6, w1 align [4 bytes for IG05] align [4 bytes] align [0 bytes] align [0 bytes] G_M000_IG05: sub w2, w2, #1 lsl x1, x3, #1 ldrsh w1, [x0, x1] cmp w1, w6 beq G_M000_IG10 sub x3, x3, #1 cmp w2, #0 bgt G_M000_IG05 G_M000_IG06: b G_M000_IG17 G_M000_IG07: sub w3, w3, #3 b G_M000_IG15 G_M000_IG08: sub w3, w3, #2 b G_M000_IG15 G_M000_IG09: sub w3, w3, #1 b G_M000_IG15 G_M000_IG10: b G_M000_IG15 G_M000_IG11: sxth w6, w1 dup v16.8h, w6 sub w3, w2, #8 sxtw x1, w3 cmp x1, #0 ble G_M000_IG13 align [0 bytes for IG12] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG12: lsl x2, x1, #1 ldr q17, [x0, x2] cmeq v17.8h, v16.8h, v17.8h umaxp v18.4s, v17.4s, v17.4s umov x2, v18.d[0] cmp x2, #0 bne G_M000_IG14 sub x1, x1, #8 cmp x1, #0 bgt G_M000_IG12 G_M000_IG13: ldr q17, [x0] cmeq v17.8h, v16.8h, v17.8h umaxp v16.4s, v17.4s, v17.4s umov x1, v16.d[0] cmp x1, #0 beq G_M000_IG17 ldr q16, [@RWD00] and v17.8h, v17.8h, v16.8h ldr q16, [@RWD16] ushl v16.8h, v17.8h, v16.8h addv h16, v16.8h umov w0, v16.h[0] clz w0, w0 neg w0, w0 add w3, w0, #31 b G_M000_IG15 G_M000_IG14: ldr q16, [@RWD00] and v16.8h, v17.8h, v16.8h ldr q17, [@RWD16] ushl v16.8h, v16.8h, v17.8h addv h16, v16.8h umov w0, v16.h[0] clz w0, w0 neg w0, w0 add w0, w0, w1 add w3, w0, #31 G_M000_IG15: mov w0, w3 G_M000_IG16: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG17: movn w0, #0 G_M000_IG18: ldp fp, lr, [sp], #0x10 ret lr RWD00 dq 8000800080008000h, 8000800080008000h RWD16 dq FFF4FFF3FFF2FFF1h, FFF8FFF7FFF6FFF5h ; Total bytes of code 384 17: JIT compiled System.SpanHelpers:LastIndexOfValueType[short,System.SpanHelpers+DontNegate`1[short]](byref,short,int) [Tier1, IL size=819, code size=384] ; Assembly listing for method (dynamicClass):InvokeStub_EventAttribute.set_Level(System.Object,System.Object,ulong):System.Object ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp mov x0, x1 G_M000_IG02: ldr x1, [x2] ldr w1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 mov x0, xzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 56 18: JIT compiled (dynamicClass):InvokeStub_EventAttribute.set_Level(System.Object,System.Object,ulong) [FullOpts, IL size=25, code size=56] ; Assembly listing for method (dynamicClass):InvokeStub_EventAttribute.set_Message(System.Object,System.Object,ulong):System.Object ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp mov x0, x1 G_M000_IG02: ldr x1, [x2] ldr x1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 mov x0, xzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 56 19: JIT compiled (dynamicClass):InvokeStub_EventAttribute.set_Message(System.Object,System.Object,ulong) [FullOpts, IL size=25, code size=56] ; Assembly listing for method (dynamicClass):InvokeStub_EventAttribute.set_Task(System.Object,System.Object,ulong):System.Object ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp mov x0, x1 G_M000_IG02: ldr x1, [x2] ldr w1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 mov x0, xzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 56 20: JIT compiled (dynamicClass):InvokeStub_EventAttribute.set_Task(System.Object,System.Object,ulong) [FullOpts, IL size=25, code size=56] ; Assembly listing for method (dynamicClass):InvokeStub_EventAttribute.set_Opcode(System.Object,System.Object,ulong):System.Object ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp mov x0, x1 G_M000_IG02: ldr x1, [x2] ldr w1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 mov x0, xzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 56 21: JIT compiled (dynamicClass):InvokeStub_EventAttribute.set_Opcode(System.Object,System.Object,ulong) [FullOpts, IL size=25, code size=56] ; Assembly listing for method (dynamicClass):InvokeStub_EventAttribute.set_Version(System.Object,System.Object,ulong):System.Object ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp mov x0, x1 G_M000_IG02: ldr x1, [x2] ldrb w1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 mov x0, xzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 56 22: JIT compiled (dynamicClass):InvokeStub_EventAttribute.set_Version(System.Object,System.Object,ulong) [FullOpts, IL size=25, code size=56] ; Assembly listing for method (dynamicClass):InvokeStub_EventAttribute.set_Keywords(System.Object,System.Object,ulong):System.Object ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp mov x0, x1 G_M000_IG02: ldr x1, [x2] ldr x1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 mov x0, xzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 56 23: JIT compiled (dynamicClass):InvokeStub_EventAttribute.set_Keywords(System.Object,System.Object,ulong) [FullOpts, IL size=25, code size=56] ; Assembly listing for method System.Number:Int64ToHexChars[ushort](ulong,ulong,int,int):ulong ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str x0, [fp, #0x58] str x1, [fp, #0x50] str w2, [fp, #0x4C] str w3, [fp, #0x48] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x10] b G_M000_IG08 G_M000_IG03: ldr w0, [fp, #0x10] sub w0, w0, #1 str w0, [fp, #0x10] ldr w0, [fp, #0x10] cmp w0, #0 bgt G_M000_IG05 G_M000_IG04: add x0, fp, #16 mov w1, #2 bl CORINFO_HELP_PATCHPOINT G_M000_IG05: ldr x0, [fp, #0x50] and w0, w0, #15 str w0, [fp, #0x44] ldr x0, [fp, #0x58] mov w1, #2 sxtw x1, w1 sub x0, x0, x1 str x0, [fp, #0x38] ldr x0, [fp, #0x38] str x0, [fp, #0x58] ldr x0, [fp, #0x38] str x0, [fp, #0x30] ldr w0, [fp, #0x44] str w0, [fp, #0x2C] ldr w0, [fp, #0x44] cmp w0, #10 blt G_M000_IG06 ldr x0, [fp, #0x30] str x0, [fp, #0x20] ldr w0, [fp, #0x2C] str w0, [fp, #0x1C] ldr w0, [fp, #0x4C] str w0, [fp, #0x18] b G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x30] str x0, [fp, #0x20] ldr w0, [fp, #0x2C] str w0, [fp, #0x1C] mov w0, #48 str w0, [fp, #0x18] G_M000_IG07: ldr w0, [fp, #0x1C] ldr w1, [fp, #0x18] add w0, w0, w1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x20] strh w0, [x1] ldr x0, [fp, #0x50] lsr x0, x0, #4 str x0, [fp, #0x50] G_M000_IG08: ldr w0, [fp, #0x48] sub w0, w0, #1 str w0, [fp, #0x40] ldr w0, [fp, #0x48] sub w0, w0, #1 str w0, [fp, #0x48] ldr w0, [fp, #0x40] tbz w0, #31, G_M000_IG03 ldr x0, [fp, #0x50] cbnz x0, G_M000_IG03 ldr x0, [fp, #0x58] G_M000_IG09: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 296 24: JIT compiled System.Number:Int64ToHexChars[ushort](ulong,ulong,int,int) [Tier0, IL size=67, code size=296] ; Assembly listing for method System.Char:System.IUtfChar.CastFrom(int):ushort ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str w0, [fp, #0x1C] G_M000_IG02: ldr w0, [fp, #0x1C] uxth w0, w0 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 25: JIT compiled System.Char:System.IUtfChar.CastFrom(int) [Tier0, IL size=3, code size=28] ; Assembly listing for method System.SpanHelpers:NonPackedIndexOfAnyInRangeUnsignedNumber[ushort,System.SpanHelpers+DontNegate`1[ushort]](byref,ushort,ushort,int):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x90]! mov fp, sp str xzr, [fp, #0x68] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str x0, [fp, #0x88] str w1, [fp, #0x84] str w2, [fp, #0x80] str w3, [fp, #0x7C] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x18] ldr w0, [fp, #0x7C] cmp w0, #8 bge G_M000_IG09 ldr w0, [fp, #0x80] uxth w0, w0 ldr w1, [fp, #0x84] uxth w1, w1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x78] str wzr, [fp, #0x74] b G_M000_IG06 G_M000_IG03: ldr x0, [fp, #0x88] ldr w1, [fp, #0x74] sxtw x1, w1 lsl x1, x1, #1 add x0, x0, x1 str x0, [fp, #0x68] ldr x0, [fp, #0x68] ldrh w0, [x0] ldr w1, [fp, #0x84] uxth w1, w1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x14] ldr w0, [fp, #0x14] ldr w1, [fp, #0x78] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG05 ldr w0, [fp, #0x74] G_M000_IG04: ldp fp, lr, [sp], #0x90 ret lr G_M000_IG05: ldr w0, [fp, #0x74] add w0, w0, #1 str w0, [fp, #0x74] G_M000_IG06: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG08 G_M000_IG07: add x0, fp, #24 mov w1, #90 bl CORINFO_HELP_PATCHPOINT G_M000_IG08: ldr w0, [fp, #0x74] ldr w1, [fp, #0x7C] cmp w0, w1 blt G_M000_IG03 b G_M000_IG17 G_M000_IG09: b G_M000_IG10 G_M000_IG10: ldr w0, [fp, #0x84] uxth w0, w0 dup v16.8h, w0 str q16, [fp, #0x50] ldr w0, [fp, #0x80] uxth w0, w0 ldr w1, [fp, #0x84] uxth w1, w1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 dup v16.8h, w0 str q16, [fp, #0x40] ldr x0, [fp, #0x88] str x0, [fp, #0x28] ldr x0, [fp, #0x88] ldr w1, [fp, #0x7C] sub w1, w1, #8 mov w1, w1 lsl x1, x1, #1 add x0, x0, x1 str x0, [fp, #0x20] G_M000_IG11: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG13 G_M000_IG12: add x0, fp, #24 mov w1, #148 bl CORINFO_HELP_PATCHPOINT G_M000_IG13: ldr x0, [fp, #0x28] ldr q0, [x0] ldr q16, [fp, #0x50] sub v0.8h, v0.8h, v16.8h ldr q16, [fp, #0x40] cmhs v0.8h, v16.8h, v0.8h movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str q0, [fp, #0x30] ldr q0, [fp, #0x30] ldr q16, [fp, #0x30] umaxp v0.4s, v0.4s, v16.4s umov x0, v0.d[0] cmp x0, #0 beq G_M000_IG15 ldr x0, [fp, #0x88] ldr x1, [fp, #0x28] ldr q0, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG14: ldp fp, lr, [sp], #0x90 ret lr G_M000_IG15: ldr x0, [fp, #0x28] mov x1, #2 lsl x1, x1, #3 add x0, x0, x1 str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] cmp x0, x1 blo G_M000_IG11 ldr x0, [fp, #0x20] ldr q0, [x0] ldr q16, [fp, #0x50] sub v0.8h, v0.8h, v16.8h ldr q16, [fp, #0x40] cmhs v0.8h, v16.8h, v0.8h movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str q0, [fp, #0x30] ldr q0, [fp, #0x30] ldr q16, [fp, #0x30] umaxp v0.4s, v0.4s, v16.4s umov x0, v0.d[0] cmp x0, #0 beq G_M000_IG17 ldr x0, [fp, #0x88] ldr x1, [fp, #0x20] ldr q0, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG16: ldp fp, lr, [sp], #0x90 ret lr G_M000_IG17: movn w0, #0 G_M000_IG18: ldp fp, lr, [sp], #0x90 ret lr ; Total bytes of code 708 26: JIT compiled System.SpanHelpers:NonPackedIndexOfAnyInRangeUnsignedNumber[ushort,System.SpanHelpers+DontNegate`1[ushort]](byref,ushort,ushort,int) [Tier0, IL size=294, code size=708] ; Assembly listing for method System.SpanHelpers+DontNegate`1[ushort]:NegateIfNeeded(bool):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str w0, [fp, #0x1C] G_M000_IG02: ldr w0, [fp, #0x1C] uxtb w0, w0 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 27: JIT compiled System.SpanHelpers+DontNegate`1[ushort]:NegateIfNeeded(bool) [Tier0, IL size=2, code size=28] ; Assembly listing for method System.SpanHelpers:SequenceCompareTo(byref,int,byref,int):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 5 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: cmp x0, x2 beq G_M000_IG10 G_M000_IG03: cmp w1, w3 csel w4, w1, w3, lo mov w4, w4 mov x5, xzr mov x6, x4 cmp x6, #16 blo G_M000_IG06 sub x6, x4, #16 cbz x6, G_M000_IG05 align [0 bytes for IG04] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG04: ldr q16, [x0, x5] ldr q17, [x2, x5] cmeq v16.16b, v16.16b, v17.16b uminp v16.4s, v16.4s, v16.4s umov x7, v16.d[0] cmn x7, #1 bne G_M000_IG08 add x5, x5, #16 cmp x6, x5 bhi G_M000_IG04 G_M000_IG05: mov x5, x6 ldr q16, [x0, x5] ldr q17, [x2, x5] cmeq v16.16b, v16.16b, v17.16b uminp v16.4s, v16.4s, v16.4s umov x6, v16.d[0] cmn x6, #1 bne G_M000_IG08 b G_M000_IG10 G_M000_IG06: cmp x4, #8 bls G_M000_IG08 sub x6, x4, #8 cbz x6, G_M000_IG08 align [4 bytes for IG07] align [4 bytes] align [4 bytes] align [4 bytes] G_M000_IG07: ldr x7, [x0, x5] ldr x8, [x2, x5] cmp x7, x8 bne G_M000_IG08 add x5, x5, #8 cmp x6, x5 bhi G_M000_IG07 G_M000_IG08: cmp x4, x5 bls G_M000_IG10 align [0 bytes for IG09] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG09: ldrb w6, [x2, x5] ldrb w7, [x0, x5] sub w6, w7, w6 cbnz w6, G_M000_IG12 add x5, x5, #1 cmp x4, x5 bhi G_M000_IG09 G_M000_IG10: sub w0, w1, w3 G_M000_IG11: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG12: mov w0, w6 G_M000_IG13: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 248 28: JIT compiled System.SpanHelpers:SequenceCompareTo(byref,int,byref,int) [Tier1, IL size=287, code size=248] ; Assembly listing for method BenchmarkDotNet.Autogenerated.UniqueProgramName:Main(System.String[]):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 29: JIT compiled BenchmarkDotNet.Autogenerated.UniqueProgramName:Main(System.String[]) [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Autogenerated.UniqueProgramName:AfterAssemblyLoadingAttached(System.String[]):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! mov fp, sp movi v16.16b, #0 add x9, fp, #80 add x10, fp, #0xD1FFAB1E stp q16, q16, [x9, #-0x40] stp q16, q16, [x9, #-0x20] bfm x9, xzr, #0, #5 dczva x9 add x9, x9, #64 cmp x9, x10 blo pc-16 (-4 instructions) stp q16, q16, [x10] stp q16, q16, [x10, #0x20] add x1, sp, #0xD1FFAB1E str x1, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] G_M000_IG02: add x2, fp, #0xD1FFAB1E add x1, fp, #0xD1FFAB1E ldr x0, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 cbz w0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x58] ldr x0, [fp, #0x58] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x58] str x0, [fp, #0xD1FFAB1E] b G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] G_M000_IG04: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #3 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xF8] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xF0] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x90] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #3 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x50] ldr x1, [fp, #0x50] ldr x0, [fp, #0x90] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #3 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x90] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x2, [fp, #0x90] str x2, [fp, #0xF0] G_M000_IG06: ldr x2, [fp, #0xF0] ldr x1, [fp, #0xF8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x48] ldr x1, [fp, #0x48] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x40] ldr x1, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xE8] ldr x0, [fp, #0xE8] str x0, [fp, #0xE0] ldr x0, [fp, #0xE8] cbnz x0, G_M000_IG07 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0xE0] G_M000_IG07: ldr x0, [fp, #0xE0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] ldr w0, [x0, #0x08] cbnz w0, G_M000_IG08 str wzr, [fp, #0xDC] b G_M000_IG09 G_M000_IG08: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr w1, [x1, #0x08] sub w1, w1, #1 ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG13 add x0, x0, x1, LSL #3 add x0, x0, #16 ldr x0, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xDC] G_M000_IG09: ldr w0, [fp, #0xDC] str w0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] ldr w0, [x0, #0x08] cbnz w0, G_M000_IG10 ldr x0, [fp, #0xD1FFAB1E] movz x11, #56 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 G_M000_IG10: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x38] ldr x0, [fp, #0x38] ldr x1, [fp, #0x38] ldr x1, [x1] ldr x1, [x1, #0x50] ldr x1, [x1, #0x28] blr x1 str x0, [fp, #0xA8] add x0, fp, #176 mov w1, #39 mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG11: ldp q16, q17, [fp, #0xB0] stp q16, q17, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD0] str x0, [fp, #0xD1FFAB1E] G_M000_IG12: add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #0xD1FFAB1E ldr w1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x30] ldr x1, [fp, #0x30] ldr x0, [fp, #0xA8] ldr x2, [fp, #0xA8] ldr x2, [x2] ldr x2, [x2, #0x50] ldr x2, [x2, #0x38] blr x2 str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 mov w2, #24 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 str x0, [fp, #0x98] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, #2 bl CORINFO_HELP_NEWARR_1_OBJ str x0, [fp, #0xA0] ldr x0, [fp, #0xA0] ldr x2, [fp, #0xD1FFAB1E] mov x1, xzr bl CORINFO_HELP_ARRADDR_ST ldr x0, [fp, #0xA0] ldr x2, [fp, #0xD1FFAB1E] mov x1, #1 bl CORINFO_HELP_ARRADDR_ST ldr x0, [fp, #0x98] ldr x2, [fp, #0xA0] mov x1, xzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 str wzr, [fp, #0xD1FFAB1E] b G_M000_IG20 G_M000_IG13: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 G_M000_IG14: b G_M000_IG16 G_M000_IG15: b G_M000_IG18 G_M000_IG16: ldr x0, [fp, #0xD1FFAB1E] bl G_M000_IG38 G_M000_IG17: b G_M000_IG22 G_M000_IG18: ldr x0, [fp, #0xD1FFAB1E] bl G_M000_IG38 G_M000_IG19: b G_M000_IG22 G_M000_IG20: ldr x0, [fp, #0xD1FFAB1E] bl G_M000_IG38 G_M000_IG21: nop G_M000_IG22: ldr w0, [fp, #0xD1FFAB1E] G_M000_IG23: ldp fp, lr, [sp], #0xD1FFAB1E ret lr G_M000_IG24: stp fp, lr, [sp, #-0x20]! ldr x1, [x1, #-0x08] str x1, [sp, #0x18] sub fp, x1, #0xD1FFAB1E G_M000_IG25: str x0, [fp, #0x80] ldr x1, [fp, #0x80] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x78] ldr x1, [fp, #0x78] str x1, [fp, #0x70] ldr x1, [fp, #0x78] cbnz x1, G_M000_IG26 str wzr, [fp, #0x68] b G_M000_IG30 G_M000_IG26: ldr x1, [fp, #0x70] str x1, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz x0, G_M000_IG28 ldr x1, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbz x0, G_M000_IG27 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x1, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cmp x0, #0 cset x0, ne str w0, [fp, #0x6C] b G_M000_IG29 G_M000_IG27: str wzr, [fp, #0x6C] b G_M000_IG29 G_M000_IG28: mov w0, #1 str w0, [fp, #0x6C] G_M000_IG29: ldr w0, [fp, #0x6C] cmp w0, #0 cset x0, ne str w0, [fp, #0x68] G_M000_IG30: ldr w0, [fp, #0x68] G_M000_IG31: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG32: stp fp, lr, [sp, #-0x20]! add x3, fp, #0xD1FFAB1E str x3, [sp, #0x18] G_M000_IG33: str x0, [fp, #0x60] ldr x0, [fp, #0xD1FFAB1E] movz x11, #88 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 ldr x0, [fp, #0xD1FFAB1E] movz x11, #96 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 ldr x0, [fp, #0xD1FFAB1E] movz x11, #104 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 ldr x0, [fp, #0xD1FFAB1E] movz x11, #112 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 ldr x0, [fp, #0xD1FFAB1E] movz x11, #120 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 ldr x0, [fp, #0xD1FFAB1E] movz x11, #128 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x08] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0xD1FFAB1E] movz x11, #136 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 movn w0, #0 str w0, [fp, #0xD1FFAB1E] adr x0, [G_M000_IG14] G_M000_IG34: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG35: stp fp, lr, [sp, #-0x20]! add x3, fp, #0xD1FFAB1E str x3, [sp, #0x18] G_M000_IG36: str x0, [fp, #0x88] ldr x0, [fp, #0x88] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x11, #72 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x08] blr x1 str x0, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0xD1FFAB1E] movz x11, #80 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 movn w0, #0 str w0, [fp, #0xD1FFAB1E] adr x0, [G_M000_IG15] G_M000_IG37: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG38: stp fp, lr, [sp, #-0x20]! add x3, fp, #0xD1FFAB1E str x3, [sp, #0x18] G_M000_IG39: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] movz x11, #64 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG40: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 1976 30: JIT compiled BenchmarkDotNet.Autogenerated.UniqueProgramName:AfterAssemblyLoadingAttached(System.String[]) [Tier0, IL size=406, code size=1976] ; Assembly listing for method BenchmarkDotNet.Engines.AnonymousPipesHost:TryGetFileHandles(System.String[],byref,byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str wzr, [fp, #0x24] str xzr, [fp, #0x18] str x0, [fp, #0x38] str x1, [fp, #0x30] str x2, [fp, #0x28] G_M000_IG02: str wzr, [fp, #0x24] mov w0, #0xD1FFAB1E str w0, [fp, #0x10] b G_M000_IG06 G_M000_IG03: ldr x0, [fp, #0x38] ldr w1, [fp, #0x24] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG10 add x0, x0, x1, LSL #3 add x0, x0, #16 ldr x0, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG05 ldr x14, [fp, #0x38] ldr w15, [fp, #0x24] add w15, w15, #1 ldr w12, [x14, #0x08] cmp w15, w12 bhs G_M000_IG10 add x14, x14, x15, LSL #3 add x14, x14, #16 ldr x15, [x14] ldr x14, [fp, #0x30] bl CORINFO_HELP_CHECKED_ASSIGN_REF ldr x14, [fp, #0x38] ldr w15, [fp, #0x24] add w15, w15, #2 ldr w12, [x14, #0x08] cmp w15, w12 bhs G_M000_IG10 add x14, x14, x15, LSL #3 add x14, x14, #16 ldr x15, [x14] ldr x14, [fp, #0x28] bl CORINFO_HELP_CHECKED_ASSIGN_REF mov w0, #1 G_M000_IG04: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG05: ldr w14, [fp, #0x24] add w14, w14, #1 str w14, [fp, #0x24] G_M000_IG06: ldr w0, [fp, #0x10] sub w0, w0, #1 str w0, [fp, #0x10] ldr w0, [fp, #0x10] cmp w0, #0 bgt G_M000_IG08 G_M000_IG07: add x0, fp, #16 mov w1, #39 bl CORINFO_HELP_PATCHPOINT G_M000_IG08: ldr w0, [fp, #0x24] ldr x1, [fp, #0x38] ldr w1, [x1, #0x08] cmp w0, w1 blt G_M000_IG03 str xzr, [fp, #0x18] ldr x14, [fp, #0x28] str xzr, [x14] ldr x14, [fp, #0x30] ldr x15, [fp, #0x18] bl CORINFO_HELP_CHECKED_ASSIGN_REF mov w0, wzr G_M000_IG09: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG10: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 324 31: JIT compiled BenchmarkDotNet.Engines.AnonymousPipesHost:TryGetFileHandles(System.String[],byref,byref) [Tier0, IL size=55, code size=324] ; Assembly listing for method BenchmarkDotNet.Engines.AnonymousPipesHost:.ctor(System.String,System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str xzr, [x9, #0x30] str x0, [fp, #0x58] str x1, [fp, #0x50] str x2, [fp, #0x48] G_M000_IG02: ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x40] ldr x0, [fp, #0x58] ldr x1, [fp, #0x50] mov w2, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x28] ldr x1, [fp, #0x30] ldr x2, [fp, #0x28] ldr x0, [fp, #0x40] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x14, [fp, #0x58] add x14, x14, #8 ldr x15, [fp, #0x40] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x58] ldr x0, [x0, #0x08] str x0, [fp, #0x20] ldr x0, [fp, #0x20] mov w1, #1 ldr x2, [fp, #0x20] ldr x2, [x2] ldr x2, [x2, #0x80] ldr x2, [x2, #0x10] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] ldr x0, [fp, #0x58] ldr x1, [fp, #0x48] mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x10] ldr x1, [fp, #0x18] ldr x2, [fp, #0x10] ldr x0, [fp, #0x38] mov w3, wzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x14, [fp, #0x58] add x14, x14, #16 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 404 32: JIT compiled BenchmarkDotNet.Engines.AnonymousPipesHost:.ctor(System.String,System.String) [Tier0, IL size=68, code size=404] ; Assembly listing for method BenchmarkDotNet.Engines.AnonymousPipesHost:OpenAnonymousPipe(System.String,int):System.IO.Stream:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str w2, [fp, #0x3C] G_M000_IG02: str xzr, [fp, #0x30] ldr x0, [fp, #0x40] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x14] ldr w1, [fp, #0x14] add x0, fp, #48 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x30] str x0, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr w2, [fp, #0x3C] mov w3, #1 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 216 33: JIT compiled BenchmarkDotNet.Engines.AnonymousPipesHost:OpenAnonymousPipe(System.String,int) [Tier0, IL size=25, code size=216] ; Assembly listing for method System.Number:TryParseBinaryIntegerStyle[int](System.ReadOnlySpan`1[ushort],int,System.Globalization.NumberFormatInfo,byref):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! mov fp, sp add x9, fp, #56 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] stp q16, q16, [x9, #0x80] str xzr, [x9, #0xA0] str x0, [fp, #0xD1FFAB1E] str x1, [fp, #0xD1FFAB1E] str w2, [fp, #0xD1FFAB1E] str x3, [fp, #0xD1FFAB1E] str x4, [fp, #0xF8] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x30] add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG52 str wzr, [fp, #0xF4] ldr w0, [fp, #0xD1FFAB1E] cmp w0, #0 bls G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldrh w0, [x0] str w0, [fp, #0xF0] ldr w0, [fp, #0xD1FFAB1E] and w0, w0, #1 cbz w0, G_M000_IG06 ldr w0, [fp, #0xF0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG06 G_M000_IG03: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG05 G_M000_IG04: add x0, fp, #48 mov w1, #37 bl CORINFO_HELP_PATCHPOINT G_M000_IG05: ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG52 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] ldr w0, [fp, #0xF0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG03 G_M000_IG06: str wzr, [fp, #0xEC] ldr w0, [fp, #0xD1FFAB1E] and w0, w0, #4 cbz w0, G_M000_IG17 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbz w0, G_M000_IG08 ldr w0, [fp, #0xF0] cmp w0, #45 bne G_M000_IG07 mov w0, #1 str w0, [fp, #0xEC] ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG52 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] b G_M000_IG17 G_M000_IG07: ldr w0, [fp, #0xF0] cmp w0, #43 bne G_M000_IG17 ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG52 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] b G_M000_IG17 G_M000_IG08: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbz w0, G_M000_IG09 ldr w0, [fp, #0xF0] cmp w0, #45 bne G_M000_IG09 mov w0, #1 str w0, [fp, #0xEC] ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG52 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] b G_M000_IG17 G_M000_IG09: add x0, fp, #0xD1FFAB1E ldr w1, [fp, #0xF4] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x78] str x1, [fp, #0x80] G_M000_IG10: ldp x0, x1, [fp, #0x78] stp x0, x1, [fp, #0xD1FFAB1E] G_M000_IG11: str wzr, [fp, #0xF4] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0xD8] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0xD0] ldr x0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG14 G_M000_IG12: ldp x0, x1, [fp, #0xD1FFAB1E] stp x0, x1, [fp, #0x38] G_M000_IG13: ldr x0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x48] str x1, [fp, #0x50] ldr x0, [fp, #0x38] ldr x1, [fp, #0x40] ldr x2, [fp, #0x48] ldr x3, [fp, #0x50] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 cbz w0, G_M000_IG14 ldr x0, [fp, #0xD8] ldr w0, [x0, #0x08] ldr w1, [fp, #0xF4] add w0, w0, w1 str w0, [fp, #0xF4] ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG52 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] b G_M000_IG17 G_M000_IG14: ldr x0, [fp, #0xD0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG17 G_M000_IG15: ldp x0, x1, [fp, #0xD1FFAB1E] stp x0, x1, [fp, #0x58] G_M000_IG16: ldr x0, [fp, #0xD0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x68] str x1, [fp, #0x70] ldr x0, [fp, #0x58] ldr x1, [fp, #0x60] ldr x2, [fp, #0x68] ldr x3, [fp, #0x70] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 cbz w0, G_M000_IG17 mov w0, #1 str w0, [fp, #0xEC] ldr x0, [fp, #0xD0] ldr w0, [x0, #0x08] ldr w1, [fp, #0xF4] add w0, w0, w1 str w0, [fp, #0xF4] ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG52 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] G_M000_IG17: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cmp w0, #0 cset x0, eq ldr w1, [fp, #0xEC] and w0, w0, w1 str w0, [fp, #0xE8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0xE4] ldr w0, [fp, #0xF0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG52 ldr w0, [fp, #0xF0] cmp w0, #48 bne G_M000_IG21 G_M000_IG18: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG20 G_M000_IG19: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG20: ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG43 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] ldr w0, [fp, #0xF0] cmp w0, #48 beq G_M000_IG18 ldr w0, [fp, #0xF0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG21 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbnz w0, G_M000_IG56 str wzr, [fp, #0xE8] b G_M000_IG56 G_M000_IG21: ldr w0, [fp, #0xF0] sub w0, w0, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xE4] ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] str wzr, [fp, #0xCC] b G_M000_IG24 G_M000_IG22: ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 blo G_M000_IG23 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbnz w0, G_M000_IG43 b G_M000_IG40 G_M000_IG23: ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] ldr w0, [fp, #0xF0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG56 ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] ldr w0, [fp, #0xE4] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xE4] ldr w0, [fp, #0xF0] sub w0, w0, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x2C] ldr w1, [fp, #0x2C] ldr w0, [fp, #0xE4] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0xE4] ldr w0, [fp, #0xCC] add w0, w0, #1 str w0, [fp, #0xCC] G_M000_IG24: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG26 G_M000_IG25: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG26: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 sub w0, w0, #2 ldr w1, [fp, #0xCC] cmp w0, w1 bgt G_M000_IG22 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 blo G_M000_IG27 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbnz w0, G_M000_IG43 b G_M000_IG40 G_M000_IG27: ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] ldr w0, [fp, #0xF0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG56 ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbnz w0, G_M000_IG31 ldr w0, [fp, #0xE8] str w0, [fp, #0x94] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0x28] ldr w1, [fp, #0x28] ldr w0, [fp, #0xE4] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG29 ldr w0, [fp, #0x94] str w0, [fp, #0x88] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0x24] ldr w1, [fp, #0x24] ldr w0, [fp, #0xE4] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG28 ldr w0, [fp, #0x88] str w0, [fp, #0x90] ldr w0, [fp, #0xF0] cmp w0, #53 cset x0, gt str w0, [fp, #0x8C] b G_M000_IG30 G_M000_IG28: ldr w0, [fp, #0x88] str w0, [fp, #0x90] str wzr, [fp, #0x8C] b G_M000_IG30 G_M000_IG29: ldr w0, [fp, #0x94] str w0, [fp, #0x90] mov w0, #1 str w0, [fp, #0x8C] G_M000_IG30: ldr w0, [fp, #0x90] ldr w1, [fp, #0x8C] orr w0, w0, w1 uxtb w0, w0 str w0, [fp, #0xE8] b G_M000_IG32 G_M000_IG31: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0x20] ldr w1, [fp, #0x20] ldr w0, [fp, #0xE4] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0xE8] G_M000_IG32: ldr w0, [fp, #0xE4] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xE4] ldr w0, [fp, #0xF0] sub w0, w0, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x1C] ldr w1, [fp, #0x1C] ldr w0, [fp, #0xE4] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0xE4] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG35 ldr w0, [fp, #0xE8] str w0, [fp, #0xB0] ldr w0, [fp, #0xE4] str w0, [fp, #0xAC] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0xA8] ldr w0, [fp, #0xEC] cbnz w0, G_M000_IG33 ldr w0, [fp, #0xB0] str w0, [fp, #0xA4] ldr w0, [fp, #0xAC] str w0, [fp, #0xA0] ldr w0, [fp, #0xA8] str w0, [fp, #0x9C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0x98] b G_M000_IG34 G_M000_IG33: ldr w0, [fp, #0xB0] str w0, [fp, #0xA4] ldr w0, [fp, #0xAC] str w0, [fp, #0xA0] ldr w0, [fp, #0xA8] str w0, [fp, #0x9C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0x98] G_M000_IG34: ldr w0, [fp, #0x9C] ldr w1, [fp, #0x98] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x18] ldr w1, [fp, #0x18] ldr w0, [fp, #0xA0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w1, [fp, #0xA4] orr w0, w0, w1 uxtb w0, w0 str w0, [fp, #0xE8] G_M000_IG35: ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG40 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] b G_M000_IG37 G_M000_IG36: mov w0, #1 str w0, [fp, #0xE8] ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG55 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] G_M000_IG37: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG39 G_M000_IG38: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG39: ldr w0, [fp, #0xF0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG36 b G_M000_IG56 G_M000_IG40: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG42 G_M000_IG41: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG42: ldr w0, [fp, #0xE8] cbnz w0, G_M000_IG55 G_M000_IG43: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbnz w0, G_M000_IG44 ldr x0, [fp, #0xF8] ldr w1, [fp, #0xE4] str w1, [x0] b G_M000_IG47 G_M000_IG44: ldr x0, [fp, #0xF8] str x0, [fp, #0xC0] ldr w0, [fp, #0xEC] cbnz w0, G_M000_IG45 ldr x0, [fp, #0xC0] str x0, [fp, #0xB8] ldr w0, [fp, #0xE4] str w0, [fp, #0xB4] b G_M000_IG46 G_M000_IG45: ldr x0, [fp, #0xC0] str x0, [fp, #0xB8] ldr w0, [fp, #0xE4] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xB4] G_M000_IG46: ldr x0, [fp, #0xB8] ldr w1, [fp, #0xB4] str w1, [x0] G_M000_IG47: str wzr, [fp, #0xE0] G_M000_IG48: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG50 G_M000_IG49: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG50: ldr w0, [fp, #0xE0] G_M000_IG51: ldp fp, lr, [sp], #0xD1FFAB1E ret lr G_M000_IG52: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG54 G_M000_IG53: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG54: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr x1, [fp, #0xF8] str w0, [x1] mov w0, #1 str w0, [fp, #0xE0] b G_M000_IG48 G_M000_IG55: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr x1, [fp, #0xF8] str w0, [x1] mov w0, #2 str w0, [fp, #0xE0] b G_M000_IG48 G_M000_IG56: ldr w0, [fp, #0xF0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG62 ldr w0, [fp, #0xD1FFAB1E] and w0, w0, #2 cbz w0, G_M000_IG52 ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] b G_M000_IG58 G_M000_IG57: ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG61 ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] G_M000_IG58: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG60 G_M000_IG59: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG60: ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 blt G_M000_IG57 G_M000_IG61: ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG40 G_M000_IG62: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr w2, [fp, #0xF4] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 cbnz w0, G_M000_IG40 b G_M000_IG52 G_M000_IG63: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 3308 34: JIT compiled System.Number:TryParseBinaryIntegerStyle[int](System.ReadOnlySpan`1[ushort],int,System.Globalization.NumberFormatInfo,byref) [Tier0, IL size=1142, code size=3308] ; Assembly listing for method System.Int32:System.IBinaryIntegerParseAndFormatInfo.get_IsSigned():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, #1 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 35: JIT compiled System.Int32:System.IBinaryIntegerParseAndFormatInfo.get_IsSigned() [Tier0, IL size=2, code size=20] ; Assembly listing for method System.Int32:System.IBinaryIntegerParseAndFormatInfo.get_MaxDigitCount():int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, #10 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 36: JIT compiled System.Int32:System.IBinaryIntegerParseAndFormatInfo.get_MaxDigitCount() [Tier0, IL size=3, code size=20] ; Assembly listing for method System.Int32:System.IBinaryIntegerParseAndFormatInfo.MultiplyBy10(int):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str w0, [fp, #0x1C] G_M000_IG02: ldr w0, [fp, #0x1C] mov w1, #10 mul w0, w0, w1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 32 37: JIT compiled System.Int32:System.IBinaryIntegerParseAndFormatInfo.MultiplyBy10(int) [Tier0, IL size=5, code size=32] ; Assembly listing for method BenchmarkDotNet.Engines.AnonymousPipesHost:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] mov w1, wzr mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 92 38: JIT compiled BenchmarkDotNet.Engines.AnonymousPipesHost:.cctor() [Tier0, IL size=13, code size=92] ; Assembly listing for method System.ArgumentOutOfRangeException:ThrowIfNegativeOrZero[int](int,System.String) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str w0, [fp, #0x1C] str x1, [fp, #0x10] G_M000_IG02: ldr w0, [fp, #0x1C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG03 ldr w0, [fp, #0x1C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x10] ldr w1, [fp, #0x1C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG04: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 108 39: JIT compiled System.ArgumentOutOfRangeException:ThrowIfNegativeOrZero[int](int,System.String) [Tier0, IL size=36, code size=108] ; Assembly listing for method BenchmarkDotNet.Engines.HostExtensions:BeforeAnythingElse(BenchmarkDotNet.Engines.IHost) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x11, #144 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 mov w1, #1 ldr x2, [x11] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 48 40: JIT compiled BenchmarkDotNet.Engines.HostExtensions:BeforeAnythingElse(BenchmarkDotNet.Engines.IHost) [Tier0, IL size=8, code size=48] ; Assembly listing for method BenchmarkDotNet.Engines.AnonymousPipesHost:SendSignal(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x0, [fp, #0x48] str w1, [fp, #0x44] G_M000_IG02: ldr w0, [fp, #0x44] cmp w0, #4 bne G_M000_IG03 mov w0, #1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr w0, [fp, #0x44] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x28] ldr x1, [fp, #0x28] ldr x0, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x48] ldr x0, [x0, #0x10] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x20] ldr x1, [x1] ldr x1, [x1, #0x48] ldr x1, [x1, #0x38] blr x1 str x0, [fp, #0x38] ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG05 ldr x0, [fp, #0x38] cbnz x0, G_M000_IG04 ldr w0, [fp, #0x44] cmp w0, #4 beq G_M000_IG05 G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x30] bl CORINFO_HELP_THROW G_M000_IG05: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 344 41: JIT compiled BenchmarkDotNet.Engines.AnonymousPipesHost:SendSignal(int) [Tier0, IL size=72, code size=344] ; Assembly listing for method BenchmarkDotNet.Engines.Engine+Signals:ToMessage(int):System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str w0, [fp, #0x1C] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr w1, [fp, #0x1C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 96 42: JIT compiled BenchmarkDotNet.Engines.Engine+Signals:ToMessage(int) [Tier0, IL size=12, code size=96] ; Assembly listing for method BenchmarkDotNet.Engines.Engine+Signals:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x38] mov w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr x0, [fp, #0x38] mov w1, #2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr x0, [fp, #0x38] mov w1, #3 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr x0, [fp, #0x38] mov w1, #4 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr x15, [fp, #0x38] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x3, [fp, #0x20] ldr x1, [fp, #0x28] ldr x2, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 556 43: JIT compiled BenchmarkDotNet.Engines.Engine+Signals:.cctor() [Tier0, IL size=106, code size=556] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.__Canon]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] mov w1, wzr mov x2, xzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 52 44: JIT compiled System.Collections.Generic.Dictionary`2[int,System.__Canon]:.ctor() [Tier0, IL size=9, code size=52] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.__Canon]:.ctor(int,System.Collections.Generic.IEqualityComparer`1[int]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str w1, [fp, #0x24] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w0, [fp, #0x24] tbz w0, #31, G_M000_IG03 mov w0, #22 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr w0, [fp, #0x24] cmp w0, #0 ble G_M000_IG04 ldr x0, [fp, #0x28] ldr w1, [fp, #0x24] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG04: b G_M000_IG05 G_M000_IG05: ldr x0, [fp, #0x18] cbz x0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr x14, [fp, #0x18] cmp x0, x14 beq G_M000_IG06 ldr x14, [fp, #0x28] add x14, x14, #24 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 188 45: JIT compiled System.Collections.Generic.Dictionary`2[int,System.__Canon]:.ctor(int,System.Collections.Generic.IEqualityComparer`1[int]) [Tier0, IL size=136, code size=188] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.__Canon]:Add(int,System.__Canon):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str w1, [fp, #0x24] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x28] ldr w1, [fp, #0x24] ldr x2, [fp, #0x18] mov w3, #2 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 str w0, [fp, #0x14] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 68 46: JIT compiled System.Collections.Generic.Dictionary`2[int,System.__Canon]:Add(int,System.__Canon) [Tier0, IL size=11, code size=68] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.__Canon]:TryInsert(int,System.__Canon,ubyte):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] str xzr, [x9, #0x40] str x0, [fp, #0x78] str x0, [fp, #0x70] str w1, [fp, #0x6C] str x2, [fp, #0x60] str w3, [fp, #0x5C] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x18] b G_M000_IG03 G_M000_IG03: ldr x0, [fp, #0x70] ldr x0, [x0, #0x08] cbnz x0, G_M000_IG04 ldr x0, [fp, #0x70] mov w1, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG04: ldr x0, [fp, #0x70] ldr x0, [x0, #0x10] str x0, [fp, #0x50] ldr x0, [fp, #0x70] ldr x0, [x0, #0x18] str x0, [fp, #0x48] ldr x0, [fp, #0x48] cbz x0, G_M000_IG05 ldr x0, [fp, #0x48] ldr w1, [fp, #0x6C] movz x11, #160 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 str w0, [fp, #0x20] b G_M000_IG06 G_M000_IG05: add x0, fp, #108 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x20] G_M000_IG06: ldr w0, [fp, #0x20] str w0, [fp, #0x44] str wzr, [fp, #0x40] ldr x0, [fp, #0x70] ldr w1, [fp, #0x44] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x38] ldr x0, [fp, #0x38] ldr w0, [x0] sub w0, w0, #1 str w0, [fp, #0x34] ldr x0, [fp, #0x48] cbnz x0, G_M000_IG13 G_M000_IG07: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG09 G_M000_IG08: add x0, fp, #24 mov w1, #125 bl CORINFO_HELP_PATCHPOINT G_M000_IG09: ldr w0, [fp, #0x34] ldr x1, [fp, #0x50] ldr w1, [x1, #0x08] cmp w0, w1 bhs G_M000_IG21 ldr x0, [fp, #0x50] ldr w1, [fp, #0x34] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG28 mov w2, #24 madd x0, x1, x2, x0 add x0, x0, #16 ldr w0, [x0, #0x08] ldr w1, [fp, #0x44] cmp w0, w1 bne G_M000_IG12 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x1, [fp, #0x50] ldr w2, [fp, #0x34] ldr w3, [x1, #0x08] cmp w2, w3 bhs G_M000_IG28 mov w3, #24 madd x1, x2, x3, x1 add x1, x1, #16 ldr w1, [x1, #0x10] ldr w2, [fp, #0x6C] ldr x3, [fp, #0x10] ldr x3, [x3] ldr x3, [x3, #0x40] ldr x3, [x3, #0x20] blr x3 cbz w0, G_M000_IG12 ldr w14, [fp, #0x5C] uxtb w14, w14 cmp w14, #1 bne G_M000_IG10 ldr x14, [fp, #0x50] ldr w15, [fp, #0x34] ldr w12, [x14, #0x08] cmp w15, w12 bhs G_M000_IG28 mov w12, #24 madd x14, x15, x12, x14 add x14, x14, #16 ldr x15, [fp, #0x60] bl CORINFO_HELP_CHECKED_ASSIGN_REF b G_M000_IG26 G_M000_IG10: ldr w0, [fp, #0x5C] uxtb w0, w0 cmp w0, #2 bne G_M000_IG11 ldr w0, [fp, #0x6C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG11: b G_M000_IG18 G_M000_IG12: ldr x0, [fp, #0x50] ldr w1, [fp, #0x34] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG28 mov w2, #24 madd x0, x1, x2, x0 add x0, x0, #16 ldr w0, [x0, #0x0C] str w0, [fp, #0x34] ldr w0, [fp, #0x40] add w0, w0, #1 str w0, [fp, #0x40] ldr w0, [fp, #0x40] ldr x1, [fp, #0x50] ldr w1, [x1, #0x08] cmp w0, w1 bls G_M000_IG07 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 b G_M000_IG07 G_M000_IG13: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG15 G_M000_IG14: add x0, fp, #24 mov w1, #241 bl CORINFO_HELP_PATCHPOINT G_M000_IG15: ldr w1, [fp, #0x34] ldr x0, [fp, #0x50] ldr w0, [x0, #0x08] cmp w1, w0 bhs G_M000_IG21 ldr x1, [fp, #0x50] ldr w0, [fp, #0x34] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG28 mov w2, #24 madd x1, x0, x2, x1 add x1, x1, #16 ldr w1, [x1, #0x08] ldr w0, [fp, #0x44] cmp w1, w0 bne G_M000_IG20 ldr x1, [fp, #0x50] ldr w0, [fp, #0x34] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG28 mov w2, #24 madd x1, x0, x2, x1 add x1, x1, #16 ldr w1, [x1, #0x10] ldr x0, [fp, #0x48] ldr w2, [fp, #0x6C] movz x11, #152 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x3, [x11] blr x3 cbz w0, G_M000_IG20 ldr w14, [fp, #0x5C] uxtb w14, w14 cmp w14, #1 bne G_M000_IG16 ldr x14, [fp, #0x50] ldr w15, [fp, #0x34] ldr w12, [x14, #0x08] cmp w15, w12 bhs G_M000_IG28 mov w12, #24 madd x14, x15, x12, x14 add x14, x14, #16 ldr x15, [fp, #0x60] bl CORINFO_HELP_CHECKED_ASSIGN_REF b G_M000_IG26 G_M000_IG16: ldr w0, [fp, #0x5C] uxtb w0, w0 cmp w0, #2 bne G_M000_IG17 ldr w0, [fp, #0x6C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG17: b G_M000_IG18 G_M000_IG18: mov w0, wzr G_M000_IG19: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG20: ldr x0, [fp, #0x50] ldr w1, [fp, #0x34] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG28 mov w2, #24 madd x0, x1, x2, x0 add x0, x0, #16 ldr w0, [x0, #0x0C] str w0, [fp, #0x34] ldr w0, [fp, #0x40] add w0, w0, #1 str w0, [fp, #0x40] ldr w0, [fp, #0x40] ldr x1, [fp, #0x50] ldr w1, [x1, #0x08] cmp w0, w1 bls G_M000_IG13 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 b G_M000_IG13 G_M000_IG21: ldr x0, [fp, #0x70] ldr w0, [x0, #0x40] cmp w0, #0 ble G_M000_IG22 ldr x0, [fp, #0x70] ldr w0, [x0, #0x3C] str w0, [fp, #0x30] ldr x0, [fp, #0x50] ldr x1, [fp, #0x70] ldr w1, [x1, #0x3C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG28 mov w2, #24 madd x0, x1, x2, x0 add x0, x0, #16 ldr w0, [x0, #0x0C] neg w0, w0 sub w0, w0, #3 ldr x1, [fp, #0x70] str w0, [x1, #0x3C] ldr x0, [fp, #0x70] ldr w0, [x0, #0x40] sub w0, w0, #1 ldr x1, [fp, #0x70] str w0, [x1, #0x40] b G_M000_IG24 G_M000_IG22: ldr x0, [fp, #0x70] ldr w0, [x0, #0x38] str w0, [fp, #0x24] ldr w0, [fp, #0x24] ldr x1, [fp, #0x50] ldr w1, [x1, #0x08] cmp w0, w1 bne G_M000_IG23 ldr x0, [fp, #0x70] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x70] ldr w1, [fp, #0x44] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x38] G_M000_IG23: ldr w14, [fp, #0x24] str w14, [fp, #0x30] ldr w14, [fp, #0x24] add w14, w14, #1 ldr x15, [fp, #0x70] str w14, [x15, #0x38] ldr x14, [fp, #0x70] ldr x14, [x14, #0x10] str x14, [fp, #0x50] G_M000_IG24: ldr x14, [fp, #0x50] ldr w15, [fp, #0x30] ldr w12, [x14, #0x08] cmp w15, w12 bhs G_M000_IG28 mov w12, #24 madd x14, x15, x12, x14 add x14, x14, #16 str x14, [fp, #0x28] ldr x14, [fp, #0x28] ldr w15, [fp, #0x44] str w15, [x14, #0x08] ldr x14, [fp, #0x38] ldr w14, [x14] sub w14, w14, #1 ldr x15, [fp, #0x28] str w14, [x15, #0x0C] ldr x14, [fp, #0x28] ldr w15, [fp, #0x6C] str w15, [x14, #0x10] ldr x14, [fp, #0x28] ldr x15, [fp, #0x60] bl CORINFO_HELP_CHECKED_ASSIGN_REF ldr w0, [fp, #0x30] add w0, w0, #1 ldr x1, [fp, #0x38] str w0, [x1] ldr x0, [fp, #0x70] ldr w0, [x0, #0x44] add w0, w0, #1 ldr x1, [fp, #0x70] str w0, [x1, #0x44] b G_M000_IG25 G_M000_IG25: b G_M000_IG26 G_M000_IG26: mov w0, #1 G_M000_IG27: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG28: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 1432 47: JIT compiled System.Collections.Generic.Dictionary`2[int,System.__Canon]:TryInsert(int,System.__Canon,ubyte) [Tier0, IL size=569, code size=1432] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.__Canon]:Initialize(int):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str x0, [fp, #0x48] str x0, [fp, #0x40] str w1, [fp, #0x3C] G_M000_IG02: ldr w0, [fp, #0x3C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x38] ldr w1, [fp, #0x38] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x30] ldr x0, [fp, #0x40] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] cbz x0, G_M000_IG04 G_M000_IG03: ldr x1, [fp, #0x18] ldr x1, [x1, #0x30] ldr x1, [x1] ldr x1, [x1, #0x18] str x1, [fp, #0x20] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x20] G_M000_IG05: ldr w1, [fp, #0x38] sxtw x1, w1 ldr x0, [fp, #0x20] bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x28] ldr x0, [fp, #0x40] movn w1, #0 str w1, [x0, #0x3C] ldr w0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x40] str x0, [x14, #0x30] ldr x14, [fp, #0x40] add x14, x14, #8 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x40] add x14, x14, #16 ldr x15, [fp, #0x28] bl CORINFO_HELP_ASSIGN_REF ldr w0, [fp, #0x38] G_M000_IG06: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 272 48: JIT compiled System.Collections.Generic.Dictionary`2[int,System.__Canon]:Initialize(int) [Tier0, IL size=56, code size=272] ; Assembly listing for method System.Collections.HashHelpers:GetFastModMultiplier(uint):ulong ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str w0, [fp, #0x1C] G_M000_IG02: movn x0, #0 ldr w1, [fp, #0x1C] mov w1, w1 cmp x1, #0 beq G_M000_IG04 udiv x0, x0, x1 add x0, x0, #1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: bl CORINFO_HELP_THROWDIVZERO brk_windows #0 ; Total bytes of code 56 49: JIT compiled System.Collections.HashHelpers:GetFastModMultiplier(uint) [Tier0, IL size=9, code size=56] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.__Canon]:GetBucket(uint):byref:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: ldr x2, [fp, #0x28] ldr x2, [x2, #0x08] str x2, [fp, #0x18] ldr x2, [fp, #0x28] ldr x2, [x2, #0x30] ldr x1, [fp, #0x18] ldr w1, [x1, #0x08] ldr w0, [fp, #0x24] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x1, [fp, #0x18] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG04 add x0, x1, x0, LSL #2 add x0, x0, #16 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 112 50: JIT compiled System.Collections.Generic.Dictionary`2[int,System.__Canon]:GetBucket(uint) [Tier0, IL size=29, code size=112] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.__Canon]:Resize():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x14] ldr w1, [fp, #0x14] ldr x0, [fp, #0x18] mov w2, wzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 51: JIT compiled System.Collections.Generic.Dictionary`2[int,System.__Canon]:Resize() [Tier0, IL size=19, code size=84] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.__Canon]:Resize(int,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp str xzr, [fp, #0x50] str xzr, [fp, #0x40] str xzr, [fp, #0x38] str xzr, [fp, #0x28] str x0, [fp, #0x68] str x0, [fp, #0x60] str w1, [fp, #0x5C] str w2, [fp, #0x58] G_M000_IG02: ldr x0, [fp, #0x60] ldr x0, [x0] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] cbz x0, G_M000_IG04 G_M000_IG03: ldr x1, [fp, #0x10] ldr x1, [x1, #0x30] ldr x1, [x1] ldr x1, [x1, #0x18] str x1, [fp, #0x20] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x20] G_M000_IG05: ldr w1, [fp, #0x5C] sxtw x1, w1 ldr x0, [fp, #0x20] bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x50] ldr x0, [fp, #0x60] ldr w0, [x0, #0x38] str w0, [fp, #0x4C] ldr x0, [fp, #0x60] ldr x0, [x0, #0x10] ldr x1, [fp, #0x50] ldr w2, [fp, #0x4C] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov w1, #0xD1FFAB1E str w1, [fp, #0x18] b G_M000_IG06 G_M000_IG06: ldr w1, [fp, #0x5C] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC ldr x14, [fp, #0x60] add x14, x14, #8 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF ldr w0, [fp, #0x5C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x60] str x0, [x1, #0x30] str wzr, [fp, #0x30] b G_M000_IG09 G_M000_IG07: ldr x1, [fp, #0x50] ldr w0, [fp, #0x30] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG13 mov w2, #24 madd x1, x0, x2, x1 add x1, x1, #16 ldr w1, [x1, #0x0C] cmn w1, #1 blt G_M000_IG08 ldr x1, [fp, #0x50] ldr w0, [fp, #0x30] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG13 mov w2, #24 madd x1, x0, x2, x1 add x1, x1, #16 ldr w1, [x1, #0x08] ldr x0, [fp, #0x60] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x28] ldr x14, [fp, #0x50] ldr w15, [fp, #0x30] ldr w12, [x14, #0x08] cmp w15, w12 bhs G_M000_IG13 mov w12, #24 madd x14, x15, x12, x14 add x14, x14, #16 add x14, x14, #12 ldr x15, [fp, #0x28] ldr w15, [x15] sub w15, w15, #1 str w15, [x14] ldr w14, [fp, #0x30] add w14, w14, #1 ldr x15, [fp, #0x28] str w14, [x15] G_M000_IG08: ldr w14, [fp, #0x30] add w14, w14, #1 str w14, [fp, #0x30] G_M000_IG09: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG11 G_M000_IG10: add x0, fp, #24 mov w1, #241 bl CORINFO_HELP_PATCHPOINT G_M000_IG11: ldr w1, [fp, #0x30] ldr w0, [fp, #0x4C] cmp w1, w0 blt G_M000_IG07 ldr x14, [fp, #0x60] add x14, x14, #16 ldr x15, [fp, #0x50] bl CORINFO_HELP_ASSIGN_REF G_M000_IG12: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG13: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 552 52: JIT compiled System.Collections.Generic.Dictionary`2[int,System.__Canon]:Resize(int,bool) [Tier0, IL size=254, code size=552] ; Assembly listing for method BenchmarkDotNet.Engines.Engine+Signals+<>c:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 53: JIT compiled BenchmarkDotNet.Engines.Engine+Signals+<>c:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method BenchmarkDotNet.Engines.Engine+Signals+<>c:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 54: JIT compiled BenchmarkDotNet.Engines.Engine+Signals+<>c:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Linq.Enumerable:ToDictionary[System.Collections.Generic.KeyValuePair`2[int,System.__Canon],System.__Canon,int](System.Collections.Generic.IEnumerable`1[System.Collections.Generic.KeyValuePair`2[int,System.__Canon]],System.Func`2[System.Collections.Generic.KeyValuePair`2[int,System.__Canon],System.__Canon],System.Func`2[System.Collections.Generic.KeyValuePair`2[int,System.__Canon],int]):System.Collections.Generic.Dictionary`2[System.__Canon,int] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] str x2, [fp, #0x20] str x3, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] str x0, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: ldr x0, [fp, #0x10] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] ldr x3, [fp, #0x18] mov x4, xzr movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 G_M000_IG06: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 136 55: JIT compiled System.Linq.Enumerable:ToDictionary[System.Collections.Generic.KeyValuePair`2[int,System.__Canon],System.__Canon,int](System.Collections.Generic.IEnumerable`1[System.Collections.Generic.KeyValuePair`2[int,System.__Canon]],System.Func`2[System.Collections.Generic.KeyValuePair`2[int,System.__Canon],System.__Canon],System.Func`2[System.Collections.Generic.KeyValuePair`2[int,System.__Canon],int]) [Tier0, IL size=10, code size=136] ; Assembly listing for method System.Linq.Enumerable:ToDictionary[System.Collections.Generic.KeyValuePair`2[int,System.__Canon],System.__Canon,int](System.Collections.Generic.IEnumerable`1[System.Collections.Generic.KeyValuePair`2[int,System.__Canon]],System.Func`2[System.Collections.Generic.KeyValuePair`2[int,System.__Canon],System.__Canon],System.Func`2[System.Collections.Generic.KeyValuePair`2[int,System.__Canon],int],System.Collections.Generic.IEqualityComparer`1[System.__Canon]):System.Collections.Generic.Dictionary`2[System.__Canon,int] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! mov fp, sp movi v16.16b, #0 add x9, fp, #48 mov x10, #128 stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40]! subs x10, x10, #64 bge pc-16 (-4 instructions) add x5, sp, #0xD1FFAB1E str x5, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] str x1, [fp, #0xD1FFAB1E] str x2, [fp, #0xD1FFAB1E] str x3, [fp, #0xD1FFAB1E] str x4, [fp, #0xD1FFAB1E] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x40] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG04 mov w0, #9 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG05 mov w0, #2 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG05: str wzr, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] cbz x0, G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] str x0, [fp, #0xD0] b G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0xD0] G_M000_IG08: ldr x0, [fp, #0xD0] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbz x0, G_M000_IG37 ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] str x0, [fp, #0x30] ldr x0, [fp, #0x30] ldr x0, [x0, #0x18] cmp x0, #64 ble G_M000_IG11 G_M000_IG09: ldr x0, [fp, #0x30] ldr x0, [x0, #0x40] cbz x0, G_M000_IG11 G_M000_IG10: ldr x0, [fp, #0x30] ldr x0, [x0, #0x40] str x0, [fp, #0x80] b G_M000_IG12 G_M000_IG11: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x80] G_M000_IG12: ldr x0, [fp, #0x80] str x0, [fp, #0x78] ldr x0, [fp, #0xD1FFAB1E] ldr x11, [fp, #0x78] ldr x1, [fp, #0x78] ldr x1, [x1] blr x1 str w0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] cbnz w0, G_M000_IG17 ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x28] cbz x0, G_M000_IG14 G_M000_IG13: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x28] str x0, [fp, #0x48] b G_M000_IG15 G_M000_IG14: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x48] G_M000_IG15: ldr x0, [fp, #0x48] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x50] ldr x0, [fp, #0x50] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x50] G_M000_IG16: ldp fp, lr, [sp], #0xD1FFAB1E ret lr G_M000_IG17: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x0, [x0, #0x18] cmp x0, #72 ble G_M000_IG20 G_M000_IG18: ldr x0, [fp, #0x28] ldr x0, [x0, #0x48] cbz x0, G_M000_IG20 G_M000_IG19: ldr x0, [fp, #0x28] ldr x0, [x0, #0x48] str x0, [fp, #0x70] b G_M000_IG21 G_M000_IG20: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x70] G_M000_IG21: ldr x0, [fp, #0x70] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xF8] ldr x0, [fp, #0xF8] cbz x0, G_M000_IG27 ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x0, [x0, #0x18] cmp x0, #96 ble G_M000_IG24 G_M000_IG22: ldr x0, [fp, #0x20] ldr x0, [x0, #0x60] cbz x0, G_M000_IG24 G_M000_IG23: ldr x0, [fp, #0x20] ldr x0, [x0, #0x60] str x0, [fp, #0x58] b G_M000_IG25 G_M000_IG24: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x58] G_M000_IG25: ldr x0, [fp, #0x58] ldr x1, [fp, #0xF8] ldr x2, [fp, #0xD1FFAB1E] ldr x3, [fp, #0xD1FFAB1E] ldr x4, [fp, #0xD1FFAB1E] movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 G_M000_IG26: ldp fp, lr, [sp], #0xD1FFAB1E ret lr G_M000_IG27: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x18] cmp x0, #80 ble G_M000_IG30 G_M000_IG28: ldr x0, [fp, #0x18] ldr x0, [x0, #0x50] cbz x0, G_M000_IG30 G_M000_IG29: ldr x0, [fp, #0x18] ldr x0, [x0, #0x50] str x0, [fp, #0x68] b G_M000_IG31 G_M000_IG30: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x68] G_M000_IG31: ldr x0, [fp, #0x68] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xF0] ldr x0, [fp, #0xF0] cbz x0, G_M000_IG37 ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x18] cmp x0, #88 ble G_M000_IG34 G_M000_IG32: ldr x0, [fp, #0x10] ldr x0, [x0, #0x58] cbz x0, G_M000_IG34 G_M000_IG33: ldr x0, [fp, #0x10] ldr x0, [x0, #0x58] str x0, [fp, #0x60] b G_M000_IG35 G_M000_IG34: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x60] G_M000_IG35: ldr x0, [fp, #0x60] ldr x1, [fp, #0xF0] ldr x2, [fp, #0xD1FFAB1E] ldr x3, [fp, #0xD1FFAB1E] ldr x4, [fp, #0xD1FFAB1E] movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 G_M000_IG36: ldp fp, lr, [sp], #0xD1FFAB1E ret lr G_M000_IG37: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x28] cbz x0, G_M000_IG39 G_M000_IG38: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x28] str x0, [fp, #0xC0] b G_M000_IG40 G_M000_IG39: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0xC0] G_M000_IG40: ldr x0, [fp, #0xC0] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xC8] ldr x0, [fp, #0xC8] ldr w1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xC8] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x30] cbz x0, G_M000_IG42 G_M000_IG41: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x30] str x0, [fp, #0xB8] b G_M000_IG43 G_M000_IG42: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0xB8] G_M000_IG43: ldr x0, [fp, #0xB8] str x0, [fp, #0xB0] ldr x0, [fp, #0xD1FFAB1E] ldr x11, [fp, #0xB0] ldr x1, [fp, #0xB0] ldr x1, [x1] blr x1 str x0, [fp, #0xE8] G_M000_IG44: b G_M000_IG51 G_M000_IG45: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x38] cbz x0, G_M000_IG47 G_M000_IG46: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x38] str x0, [fp, #0xA8] b G_M000_IG48 G_M000_IG47: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0xA8] G_M000_IG48: ldr x0, [fp, #0xA8] str x0, [fp, #0xA0] ldr x0, [fp, #0xE8] ldr x11, [fp, #0xA0] ldr x1, [fp, #0xA0] ldr x1, [x1] blr x1 str x0, [fp, #0x90] str x1, [fp, #0x98] G_M000_IG49: ldp x0, x1, [fp, #0x90] stp x0, x1, [fp, #0xD8] G_M000_IG50: ldr x1, [fp, #0xD8] ldr x2, [fp, #0xE0] ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x08] ldr x3, [fp, #0xD1FFAB1E] ldr x3, [x3, #0x18] blr x3 str x0, [fp, #0x88] ldr x1, [fp, #0xD8] ldr x2, [fp, #0xE0] ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x08] ldr x3, [fp, #0xD1FFAB1E] ldr x3, [x3, #0x18] blr x3 str w0, [fp, #0x3C] ldr w2, [fp, #0x3C] ldr x1, [fp, #0x88] ldr x0, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG51: ldr w0, [fp, #0x40] sub w0, w0, #1 str w0, [fp, #0x40] ldr w0, [fp, #0x40] cmp w0, #0 bgt G_M000_IG53 G_M000_IG52: add x0, fp, #64 mov w1, #150 bl CORINFO_HELP_PATCHPOINT G_M000_IG53: ldr x0, [fp, #0xE8] movz x11, #168 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG45 b G_M000_IG54 G_M000_IG54: ldr x0, [fp, #0xD1FFAB1E] bl G_M000_IG58 G_M000_IG55: nop G_M000_IG56: ldr x0, [fp, #0xD1FFAB1E] G_M000_IG57: ldp fp, lr, [sp], #0xD1FFAB1E ret lr G_M000_IG58: stp fp, lr, [sp, #-0x20]! add x3, fp, #0xD1FFAB1E str x3, [sp, #0x18] G_M000_IG59: ldr x0, [fp, #0xE8] cbz x0, G_M000_IG60 ldr x0, [fp, #0xE8] movz x11, #176 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG60: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 1560 56: JIT compiled System.Linq.Enumerable:ToDictionary[System.Collections.Generic.KeyValuePair`2[int,System.__Canon],System.__Canon,int](System.Collections.Generic.IEnumerable`1[System.Collections.Generic.KeyValuePair`2[int,System.__Canon]],System.Func`2[System.Collections.Generic.KeyValuePair`2[int,System.__Canon],System.__Canon],System.Func`2[System.Collections.Generic.KeyValuePair`2[int,System.__Canon],int],System.Collections.Generic.IEqualityComparer`1[System.__Canon]) [Tier0, IL size=175, code size=1560] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.__Canon]:get_Count():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x38] ldr x1, [fp, #0x18] ldr w1, [x1, #0x40] sub w0, w0, w1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 57: JIT compiled System.Collections.Generic.Dictionary`2[int,System.__Canon]:get_Count() [Tier0, IL size=14, code size=40] ; Assembly listing for method System.Collections.Generic.Dictionary`2[System.__Canon,int]:.ctor(int,System.Collections.Generic.IEqualityComparer`1[System.__Canon]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp str xzr, [fp, #0x48] str xzr, [fp, #0x40] str xzr, [fp, #0x38] str x0, [fp, #0x68] str x0, [fp, #0x60] str w1, [fp, #0x5C] str x2, [fp, #0x50] G_M000_IG02: ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w0, [fp, #0x5C] tbz w0, #31, G_M000_IG03 mov w0, #22 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr w0, [fp, #0x5C] cmp w0, #0 ble G_M000_IG04 ldr x0, [fp, #0x60] ldr w1, [fp, #0x5C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG04: ldr x14, [fp, #0x60] str x14, [fp, #0x40] ldr x14, [fp, #0x50] str x14, [fp, #0x38] ldr x14, [fp, #0x50] cbnz x14, G_M000_IG08 ldr x14, [fp, #0x60] ldr x14, [x14] str x14, [fp, #0x20] ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x20] cbz x0, G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x20] str x0, [fp, #0x28] b G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x28] G_M000_IG07: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x38] G_M000_IG08: ldr x14, [fp, #0x40] add x14, x14, #24 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x60] ldr x0, [x0] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 cmp x0, x1 bne G_M000_IG13 ldr x0, [fp, #0x60] ldr x0, [x0, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x48] ldr x0, [fp, #0x48] cbz x0, G_M000_IG13 ldr x0, [fp, #0x60] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] cbz x0, G_M000_IG10 G_M000_IG09: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] str x0, [fp, #0x30] b G_M000_IG11 G_M000_IG10: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x30] G_M000_IG11: ldr x0, [fp, #0x30] ldr x1, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x60] add x14, x14, #24 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG12: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG13: ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 500 58: JIT compiled System.Collections.Generic.Dictionary`2[System.__Canon,int]:.ctor(int,System.Collections.Generic.IEqualityComparer`1[System.__Canon]) [Tier0, IL size=136, code size=500] ; Assembly listing for method System.Collections.Generic.Dictionary`2[System.__Canon,int]:Initialize(int):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str x0, [fp, #0x48] str x0, [fp, #0x40] str w1, [fp, #0x3C] G_M000_IG02: ldr w0, [fp, #0x3C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x38] ldr w1, [fp, #0x38] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x30] ldr x0, [fp, #0x40] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x28] cbz x0, G_M000_IG04 G_M000_IG03: ldr x1, [fp, #0x18] ldr x1, [x1, #0x30] ldr x1, [x1] ldr x1, [x1, #0x28] str x1, [fp, #0x20] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x20] G_M000_IG05: ldr w1, [fp, #0x38] sxtw x1, w1 ldr x0, [fp, #0x20] bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x28] ldr x0, [fp, #0x40] movn w1, #0 str w1, [x0, #0x3C] ldr w0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x40] str x0, [x14, #0x30] ldr x14, [fp, #0x40] add x14, x14, #8 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x40] add x14, x14, #16 ldr x15, [fp, #0x28] bl CORINFO_HELP_ASSIGN_REF ldr w0, [fp, #0x38] G_M000_IG06: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 272 59: JIT compiled System.Collections.Generic.Dictionary`2[System.__Canon,int]:Initialize(int) [Tier0, IL size=56, code size=272] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.__Canon]:System.Collections.Generic.IEnumerable>.GetEnumerator():System.Collections.Generic.IEnumerator`1[System.Collections.Generic.KeyValuePair`2[int,System.__Canon]]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x38] str xzr, [fp, #0x28] str x0, [fp, #0x48] str x0, [fp, #0x40] G_M000_IG02: ldr x0, [fp, #0x40] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG07 ldr x0, [fp, #0x40] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x28] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x28] str x0, [fp, #0x20] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x20] G_M000_IG05: ldr x0, [fp, #0x20] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x8, [fp, #0x28] add x8, x8, #8 ldr x0, [fp, #0x40] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x28] str x0, [fp, #0x38] ldr x0, [fp, #0x38] G_M000_IG06: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG07: ldr x0, [fp, #0x40] ldr x0, [x0] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x20] cbz x0, G_M000_IG09 G_M000_IG08: ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x20] str x0, [fp, #0x30] b G_M000_IG10 G_M000_IG09: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x30] G_M000_IG10: ldr x0, [fp, #0x30] bl CORINFO_HELP_GETGENERICS_GCSTATIC_BASE ldr x0, [x0] str x0, [fp, #0x38] ldr x0, [fp, #0x38] G_M000_IG11: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 304 60: JIT compiled System.Collections.Generic.Dictionary`2[int,System.__Canon]:System.Collections.Generic.IEnumerable>.GetEnumerator() [Tier0, IL size=30, code size=304] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.__Canon]:GetEnumerator():System.Collections.Generic.Dictionary`2+Enumerator[int,System.__Canon]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #32 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] str x0, [fp, #0x58] str x0, [fp, #0x50] str x8, [fp, #0x48] G_M000_IG02: ldr x0, [fp, #0x50] ldr x0, [x0] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x28] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x28] str x0, [fp, #0x18] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x18] G_M000_IG05: add x0, fp, #32 ldr x1, [fp, #0x18] ldr x2, [fp, #0x50] mov w3, #2 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x14, [fp, #0x48] add x13, fp, #32 bl CORINFO_HELP_ASSIGN_BYREF ldp x12, x15, [x13], #0x10 stp x12, x15, [x14], #0x10 bl CORINFO_HELP_ASSIGN_BYREF ldr x12, [x13], #0x08 str x12, [x14], #0x08 G_M000_IG06: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 192 61: JIT compiled System.Collections.Generic.Dictionary`2[int,System.__Canon]:GetEnumerator() [Tier0, IL size=8, code size=192] ; Assembly listing for method System.Collections.Generic.Dictionary`2+Enumerator[int,System.__Canon]:.ctor(System.Collections.Generic.Dictionary`2[int,System.__Canon],int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] str w3, [fp, #0x14] G_M000_IG02: ldr x14, [fp, #0x28] ldr x15, [fp, #0x18] bl CORINFO_HELP_CHECKED_ASSIGN_REF ldr x0, [fp, #0x18] ldr w0, [x0, #0x44] ldr x1, [fp, #0x28] str w0, [x1, #0x08] ldr x0, [fp, #0x28] str wzr, [x0, #0x0C] ldr x0, [fp, #0x28] ldr w1, [fp, #0x14] str w1, [x0, #0x10] ldr x0, [fp, #0x28] stp xzr, xzr, [x0, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 88 62: JIT compiled System.Collections.Generic.Dictionary`2+Enumerator[int,System.__Canon]:.ctor(System.Collections.Generic.Dictionary`2[int,System.__Canon],int) [Tier0, IL size=46, code size=88] ; Assembly listing for method System.Collections.Generic.Dictionary`2+Enumerator[int,System.__Canon]:MoveNext():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str xzr, [fp, #0x40] str xzr, [fp, #0x30] str xzr, [fp, #0x20] str x1, [fp, #0x58] str x0, [fp, #0x50] str x1, [fp, #0x48] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x10] ldr x0, [fp, #0x50] ldr w0, [x0, #0x08] ldr x1, [fp, #0x50] ldr x1, [x1] ldr w1, [x1, #0x44] cmp w0, w1 beq G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 b G_M000_IG08 G_M000_IG03: ldr x0, [fp, #0x50] ldr x0, [x0] ldr x0, [x0, #0x10] str x0, [fp, #0x30] ldr x0, [fp, #0x50] ldr w0, [x0, #0x0C] str w0, [fp, #0x3C] ldr w0, [fp, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x50] str w0, [x1, #0x0C] ldr x0, [fp, #0x30] ldr w1, [fp, #0x3C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG12 mov w2, #24 madd x0, x1, x2, x0 add x0, x0, #16 str x0, [fp, #0x40] ldr x0, [fp, #0x40] ldr w0, [x0, #0x0C] cmn w0, #1 blt G_M000_IG08 stp xzr, xzr, [fp, #0x20] ldr x0, [fp, #0x48] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] cbz x0, G_M000_IG05 G_M000_IG04: ldr x3, [fp, #0x48] ldr x3, [x3, #0x30] ldr x3, [x3] ldr x3, [x3, #0x18] str x3, [fp, #0x18] b G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x18] G_M000_IG06: ldr x3, [fp, #0x40] ldr x3, [x3] ldr x2, [fp, #0x40] ldr w2, [x2, #0x10] add x0, fp, #32 ldr x1, [fp, #0x18] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x14, [fp, #0x50] add x14, x14, #24 add x13, fp, #32 bl CORINFO_HELP_ASSIGN_BYREF ldr x12, [x13], #0x08 str x12, [x14], #0x08 mov w0, #1 G_M000_IG07: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG08: ldr w0, [fp, #0x10] sub w0, w0, #1 str w0, [fp, #0x10] ldr w0, [fp, #0x10] cmp w0, #0 bgt G_M000_IG10 G_M000_IG09: add x0, fp, #16 mov w1, #94 bl CORINFO_HELP_PATCHPOINT G_M000_IG10: ldr x0, [fp, #0x50] ldr w0, [x0, #0x0C] ldr x1, [fp, #0x50] ldr x1, [x1] ldr w1, [x1, #0x38] cmp w0, w1 blo G_M000_IG03 ldr x0, [fp, #0x50] ldr x0, [x0] ldr w0, [x0, #0x38] add w0, w0, #1 ldr x1, [fp, #0x50] str w0, [x1, #0x0C] ldr x0, [fp, #0x50] stp xzr, xzr, [x0, #0x18] mov w0, wzr G_M000_IG11: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG12: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 456 63: JIT compiled System.Collections.Generic.Dictionary`2+Enumerator[int,System.__Canon]:MoveNext() [Tier0, IL size=146, code size=456] ; Assembly listing for method System.Collections.Generic.KeyValuePair`2[int,System.__Canon]:.ctor(int,System.__Canon):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] str x3, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x28] ldr w15, [fp, #0x1C] str w15, [x14, #0x08] ldr x14, [fp, #0x28] ldr x15, [fp, #0x10] bl CORINFO_HELP_CHECKED_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 56 64: JIT compiled System.Collections.Generic.KeyValuePair`2[int,System.__Canon]:.ctor(int,System.__Canon) [Tier0, IL size=15, code size=56] ; Assembly listing for method System.Collections.Generic.Dictionary`2+Enumerator[int,System.__Canon]:get_Current():System.Collections.Generic.KeyValuePair`2[int,System.__Canon]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] G_M000_IG03: ldp x1, x2, [x0, #0x18] stp x1, x2, [fp, #0x10] G_M000_IG04: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 48 65: JIT compiled System.Collections.Generic.Dictionary`2+Enumerator[int,System.__Canon]:get_Current() [Tier0, IL size=7, code size=48] ; Assembly listing for method BenchmarkDotNet.Engines.Engine+Signals+<>c:<.cctor>b__5_0(System.Collections.Generic.KeyValuePair`2[int,System.String]):System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x18] str x2, [fp, #0x20] G_M000_IG02: add x0, fp, #24 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 64 66: JIT compiled BenchmarkDotNet.Engines.Engine+Signals+<>c:<.cctor>b__5_0(System.Collections.Generic.KeyValuePair`2[int,System.String]) [Tier0, IL size=8, code size=64] ; Assembly listing for method System.Collections.Generic.KeyValuePair`2[int,System.__Canon]:get_Value():System.__Canon:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 32 67: JIT compiled System.Collections.Generic.KeyValuePair`2[int,System.__Canon]:get_Value() [Tier0, IL size=7, code size=32] ; Assembly listing for method BenchmarkDotNet.Engines.Engine+Signals+<>c:<.cctor>b__5_1(System.Collections.Generic.KeyValuePair`2[int,System.String]):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x18] str x2, [fp, #0x20] G_M000_IG02: add x0, fp, #24 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 64 68: JIT compiled BenchmarkDotNet.Engines.Engine+Signals+<>c:<.cctor>b__5_1(System.Collections.Generic.KeyValuePair`2[int,System.String]) [Tier0, IL size=8, code size=64] ; Assembly listing for method System.Collections.Generic.KeyValuePair`2[int,System.__Canon]:get_Key():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 32 69: JIT compiled System.Collections.Generic.KeyValuePair`2[int,System.__Canon]:get_Key() [Tier0, IL size=7, code size=32] ; Assembly listing for method System.Collections.Generic.Dictionary`2[System.__Canon,int]:Add(System.__Canon,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] G_M000_IG02: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] ldr w2, [fp, #0x1C] mov w3, #2 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 str w0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 68 70: JIT compiled System.Collections.Generic.Dictionary`2[System.__Canon,int]:Add(System.__Canon,int) [Tier0, IL size=11, code size=68] ; Assembly listing for method System.Collections.Generic.Dictionary`2[System.__Canon,int]:TryInsert(System.__Canon,int,ubyte):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0xC0]! mov fp, sp str xzr, [fp, #0x98] str xzr, [fp, #0x90] str xzr, [fp, #0x80] str xzr, [fp, #0x70] str x0, [fp, #0xB8] str x0, [fp, #0xB0] str x1, [fp, #0xA8] str w2, [fp, #0xA4] str w3, [fp, #0xA0] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x30] ldr x0, [fp, #0xA8] cbnz x0, G_M000_IG03 mov w0, #4 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0xB0] ldr x0, [x0, #0x08] cbnz x0, G_M000_IG04 ldr x0, [fp, #0xB0] mov w1, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG04: ldr x0, [fp, #0xB0] ldr x0, [x0, #0x10] str x0, [fp, #0x98] ldr x0, [fp, #0xB0] ldr x0, [x0, #0x18] str x0, [fp, #0x90] b G_M000_IG05 G_M000_IG05: ldr x0, [fp, #0xB0] ldr x0, [x0] str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x30] cbz x0, G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x28] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x30] str x0, [fp, #0x60] b G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x60] G_M000_IG08: ldr x0, [fp, #0x60] str x0, [fp, #0x58] ldr x0, [fp, #0x90] ldr x11, [fp, #0x58] ldr x1, [fp, #0xA8] ldr x2, [fp, #0x58] ldr x2, [x2] blr x2 str w0, [fp, #0x54] b G_M000_IG09 G_M000_IG09: ldr w0, [fp, #0x54] str w0, [fp, #0x8C] str wzr, [fp, #0x88] ldr x0, [fp, #0xB0] ldr w1, [fp, #0x8C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x80] ldr x0, [fp, #0x80] ldr w0, [x0] sub w0, w0, #1 str w0, [fp, #0x7C] b G_M000_IG10 G_M000_IG10: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG12 G_M000_IG11: add x0, fp, #48 mov w1, #241 bl CORINFO_HELP_PATCHPOINT G_M000_IG12: ldr w0, [fp, #0x7C] ldr x1, [fp, #0x98] ldr w1, [x1, #0x08] cmp w0, w1 bhs G_M000_IG24 ldr x0, [fp, #0x98] ldr w1, [fp, #0x7C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG30 mov w2, #24 madd x0, x1, x2, x0 add x0, x0, #16 ldr w0, [x0, #0x08] ldr w1, [fp, #0x8C] cmp w0, w1 bne G_M000_IG23 ldr x0, [fp, #0xB0] ldr x0, [x0] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x38] cbz x0, G_M000_IG14 G_M000_IG13: ldr x1, [fp, #0x20] ldr x1, [x1, #0x30] ldr x1, [x1] ldr x1, [x1, #0x38] str x1, [fp, #0x48] b G_M000_IG15 G_M000_IG14: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x48] G_M000_IG15: ldr x1, [fp, #0x48] str x1, [fp, #0x40] ldr x1, [fp, #0x98] ldr w0, [fp, #0x7C] ldr w11, [x1, #0x08] cmp w0, w11 bhs G_M000_IG30 mov w11, #24 madd x1, x0, x11, x1 add x1, x1, #16 ldr x1, [x1] ldr x0, [fp, #0x90] ldr x11, [fp, #0x40] ldr x2, [fp, #0xA8] ldr x3, [fp, #0x40] ldr x3, [x3] blr x3 cbz w0, G_M000_IG23 ldr w0, [fp, #0xA0] uxtb w0, w0 cmp w0, #1 bne G_M000_IG17 ldr x0, [fp, #0x98] ldr w1, [fp, #0x7C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG30 mov w2, #24 madd x0, x1, x2, x0 add x0, x0, #16 ldr w1, [fp, #0xA4] str w1, [x0, #0x10] mov w0, #1 G_M000_IG16: ldp fp, lr, [sp], #0xC0 ret lr G_M000_IG17: ldr w0, [fp, #0xA0] uxtb w0, w0 cmp w0, #2 bne G_M000_IG21 ldr x0, [fp, #0xB0] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x40] cbz x0, G_M000_IG19 G_M000_IG18: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x40] str x0, [fp, #0x38] b G_M000_IG20 G_M000_IG19: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x38] G_M000_IG20: ldr x0, [fp, #0x38] ldr x1, [fp, #0xA8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG21: mov w0, wzr G_M000_IG22: ldp fp, lr, [sp], #0xC0 ret lr G_M000_IG23: ldr x0, [fp, #0x98] ldr w1, [fp, #0x7C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG30 mov w2, #24 madd x0, x1, x2, x0 add x0, x0, #16 ldr w0, [x0, #0x0C] str w0, [fp, #0x7C] ldr w0, [fp, #0x88] add w0, w0, #1 str w0, [fp, #0x88] ldr w0, [fp, #0x88] ldr x1, [fp, #0x98] ldr w1, [x1, #0x08] cmp w0, w1 bls G_M000_IG10 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 b G_M000_IG10 G_M000_IG24: ldr x0, [fp, #0xB0] ldr w0, [x0, #0x40] cmp w0, #0 ble G_M000_IG25 ldr x0, [fp, #0xB0] ldr w0, [x0, #0x3C] str w0, [fp, #0x78] ldr x0, [fp, #0x98] ldr x1, [fp, #0xB0] ldr w1, [x1, #0x3C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG30 mov w2, #24 madd x0, x1, x2, x0 add x0, x0, #16 ldr w0, [x0, #0x0C] neg w0, w0 sub w0, w0, #3 ldr x1, [fp, #0xB0] str w0, [x1, #0x3C] ldr x0, [fp, #0xB0] ldr w0, [x0, #0x40] sub w0, w0, #1 ldr x1, [fp, #0xB0] str w0, [x1, #0x40] b G_M000_IG27 G_M000_IG25: ldr x0, [fp, #0xB0] ldr w0, [x0, #0x38] str w0, [fp, #0x6C] ldr w0, [fp, #0x6C] ldr x1, [fp, #0x98] ldr w1, [x1, #0x08] cmp w0, w1 bne G_M000_IG26 ldr x0, [fp, #0xB0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xB0] ldr w1, [fp, #0x8C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x80] G_M000_IG26: ldr w14, [fp, #0x6C] str w14, [fp, #0x78] ldr w14, [fp, #0x6C] add w14, w14, #1 ldr x15, [fp, #0xB0] str w14, [x15, #0x38] ldr x14, [fp, #0xB0] ldr x14, [x14, #0x10] str x14, [fp, #0x98] G_M000_IG27: ldr x14, [fp, #0x98] ldr w15, [fp, #0x78] ldr w12, [x14, #0x08] cmp w15, w12 bhs G_M000_IG30 mov w12, #24 madd x14, x15, x12, x14 add x14, x14, #16 str x14, [fp, #0x70] ldr x14, [fp, #0x70] ldr w15, [fp, #0x8C] str w15, [x14, #0x08] ldr x14, [fp, #0x80] ldr w14, [x14] sub w14, w14, #1 ldr x15, [fp, #0x70] str w14, [x15, #0x0C] ldr x14, [fp, #0x70] ldr x15, [fp, #0xA8] bl CORINFO_HELP_CHECKED_ASSIGN_REF ldr x1, [fp, #0x70] ldr w0, [fp, #0xA4] str w0, [x1, #0x10] ldr w1, [fp, #0x78] add w1, w1, #1 ldr x0, [fp, #0x80] str w1, [x0] ldr x1, [fp, #0xB0] ldr w1, [x1, #0x44] add w1, w1, #1 ldr x0, [fp, #0xB0] str w1, [x0, #0x44] ldr w1, [fp, #0x88] cmp w1, #100 bls G_M000_IG28 ldr x1, [fp, #0x90] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz x0, G_M000_IG28 ldr x1, [fp, #0x98] ldr w1, [x1, #0x08] ldr x0, [fp, #0xB0] mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG28: mov w0, #1 G_M000_IG29: ldp fp, lr, [sp], #0xC0 ret lr G_M000_IG30: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 1360 71: JIT compiled System.Collections.Generic.Dictionary`2[System.__Canon,int]:TryInsert(System.__Canon,int,ubyte) [Tier0, IL size=569, code size=1360] ; Assembly listing for method System.Collections.Generic.Dictionary`2[System.__Canon,int]:GetBucket(uint):byref:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: ldr x2, [fp, #0x28] ldr x2, [x2, #0x08] str x2, [fp, #0x18] ldr x2, [fp, #0x28] ldr x2, [x2, #0x30] ldr x1, [fp, #0x18] ldr w1, [x1, #0x08] ldr w0, [fp, #0x24] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x1, [fp, #0x18] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG04 add x0, x1, x0, LSL #2 add x0, x0, #16 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 112 72: JIT compiled System.Collections.Generic.Dictionary`2[System.__Canon,int]:GetBucket(uint) [Tier0, IL size=29, code size=112] ; Assembly listing for method System.Collections.Generic.Dictionary`2+Enumerator[int,System.__Canon]:Dispose():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 24 73: JIT compiled System.Collections.Generic.Dictionary`2+Enumerator[int,System.__Canon]:Dispose() [Tier0, IL size=1, code size=24] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.__Canon]:get_Item(int):System.__Canon:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: ldr x0, [fp, #0x28] ldr w1, [fp, #0x24] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x0, [fp, #0x18] cbz x0, G_M000_IG04 ldr x0, [fp, #0x18] ldr x0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: ldr w0, [fp, #0x24] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str xzr, [fp, #0x10] ldr x0, [fp, #0x10] G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 120 74: JIT compiled System.Collections.Generic.Dictionary`2[int,System.__Canon]:get_Item(int) [Tier0, IL size=39, code size=120] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.__Canon]:FindValue(int):byref:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str xzr, [x9, #0x50] str x0, [fp, #0x78] str x0, [fp, #0x70] str w1, [fp, #0x6C] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x18] b G_M000_IG03 G_M000_IG03: str xzr, [fp, #0x60] ldr x0, [fp, #0x70] ldr x0, [x0, #0x08] cbz x0, G_M000_IG19 ldr x0, [fp, #0x70] ldr x0, [x0, #0x18] str x0, [fp, #0x50] ldr x0, [fp, #0x50] cbnz x0, G_M000_IG08 add x0, fp, #108 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x4C] ldr x0, [fp, #0x70] ldr w1, [fp, #0x4C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [x0] str w0, [fp, #0x48] ldr x0, [fp, #0x70] ldr x0, [x0, #0x10] str x0, [fp, #0x40] str wzr, [fp, #0x3C] ldr w0, [fp, #0x48] sub w0, w0, #1 str w0, [fp, #0x48] G_M000_IG04: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG06 G_M000_IG05: add x0, fp, #24 mov w1, #99 bl CORINFO_HELP_PATCHPOINT G_M000_IG06: ldr w0, [fp, #0x48] ldr x1, [fp, #0x40] ldr w1, [x1, #0x08] cmp w0, w1 bhs G_M000_IG19 ldr x0, [fp, #0x40] ldr w1, [fp, #0x48] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG20 mov w2, #24 madd x0, x1, x2, x0 add x0, x0, #16 str x0, [fp, #0x60] ldr x0, [fp, #0x60] ldr w0, [x0, #0x08] ldr w1, [fp, #0x4C] cmp w0, w1 bne G_M000_IG07 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x1, [fp, #0x60] ldr w1, [x1, #0x10] ldr w2, [fp, #0x6C] ldr x3, [fp, #0x10] ldr x3, [x3] ldr x3, [x3, #0x40] ldr x3, [x3, #0x20] blr x3 cbnz w0, G_M000_IG14 G_M000_IG07: ldr x0, [fp, #0x60] ldr w0, [x0, #0x0C] str w0, [fp, #0x48] ldr w0, [fp, #0x3C] add w0, w0, #1 str w0, [fp, #0x3C] ldr w0, [fp, #0x3C] ldr x1, [fp, #0x40] ldr w1, [x1, #0x08] cmp w0, w1 bls G_M000_IG04 b G_M000_IG13 G_M000_IG08: ldr x0, [fp, #0x50] ldr w1, [fp, #0x6C] movz x11, #216 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 str w0, [fp, #0x38] ldr x0, [fp, #0x70] ldr w1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [x0] str w0, [fp, #0x34] ldr x0, [fp, #0x70] ldr x0, [x0, #0x10] str x0, [fp, #0x28] str wzr, [fp, #0x24] ldr w0, [fp, #0x34] sub w0, w0, #1 str w0, [fp, #0x34] G_M000_IG09: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG11 G_M000_IG10: add x0, fp, #24 mov w1, #212 bl CORINFO_HELP_PATCHPOINT G_M000_IG11: ldr w1, [fp, #0x34] ldr x0, [fp, #0x28] ldr w0, [x0, #0x08] cmp w1, w0 bhs G_M000_IG19 ldr x1, [fp, #0x28] ldr w0, [fp, #0x34] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG20 mov w2, #24 madd x1, x0, x2, x1 add x1, x1, #16 str x1, [fp, #0x60] ldr x1, [fp, #0x60] ldr w1, [x1, #0x08] ldr w0, [fp, #0x38] cmp w1, w0 bne G_M000_IG12 ldr x1, [fp, #0x60] ldr w1, [x1, #0x10] ldr x0, [fp, #0x50] ldr w2, [fp, #0x6C] movz x11, #224 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x3, [x11] blr x3 cbnz w0, G_M000_IG14 G_M000_IG12: ldr x0, [fp, #0x60] ldr w0, [x0, #0x0C] str w0, [fp, #0x34] ldr w0, [fp, #0x24] add w0, w0, #1 str w0, [fp, #0x24] ldr w0, [fp, #0x24] ldr x1, [fp, #0x28] ldr w1, [x1, #0x08] cmp w0, w1 bls G_M000_IG09 G_M000_IG13: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG14: ldr x0, [fp, #0x60] ldrsb wzr, [x0] ldr x0, [fp, #0x60] str x0, [fp, #0x58] G_M000_IG15: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG17 G_M000_IG16: add x0, fp, #24 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG17: ldr x0, [fp, #0x58] G_M000_IG18: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG19: str xzr, [fp, #0x58] b G_M000_IG15 G_M000_IG20: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 800 75: JIT compiled System.Collections.Generic.Dictionary`2[int,System.__Canon]:FindValue(int) [Tier0, IL size=299, code size=800] ; Assembly listing for method System.Collections.Generic.EqualityComparer`1[int]:get_Default():System.Collections.Generic.EqualityComparer`1[int] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #30 bl CORINFO_HELP_CLASSINIT_SHARED_DYNAMICCLASS movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 52 76: JIT compiled System.Collections.Generic.EqualityComparer`1[int]:get_Default() [Tier0, IL size=6, code size=52] ; Assembly listing for method System.Collections.Generic.EqualityComparer`1[int]:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 112 77: JIT compiled System.Collections.Generic.EqualityComparer`1[int]:.cctor() [Tier0, IL size=26, code size=112] ; Assembly listing for method System.Collections.Generic.EnumEqualityComparer`1[int]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 78: JIT compiled System.Collections.Generic.EnumEqualityComparer`1[int]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Collections.Generic.EqualityComparer`1[int]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 79: JIT compiled System.Collections.Generic.EqualityComparer`1[int]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Collections.Generic.EnumEqualityComparer`1[int]:Equals(int,int):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] str w2, [fp, #0x10] G_M000_IG02: ldr w0, [fp, #0x14] ldr w1, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 80: JIT compiled System.Collections.Generic.EnumEqualityComparer`1[int]:Equals(int,int) [Tier0, IL size=8, code size=56] ; Assembly listing for method System.Runtime.CompilerServices.RuntimeHelpers:EnumEquals[int](int,int):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str w0, [fp, #0x1C] str w1, [fp, #0x18] G_M000_IG02: ldr w0, [fp, #0x1C] ldr w1, [fp, #0x18] cmp w0, w1 cset x0, eq G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 81: JIT compiled System.Runtime.CompilerServices.RuntimeHelpers:EnumEquals[int](int,int) [Tier0, IL size=5, code size=40] ; Assembly listing for method BenchmarkDotNet.Engines.AnonymousPipesHost:WriteLine(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x20] ldr x2, [fp, #0x18] ldr x2, [x2] ldr x2, [x2, #0x68] ldr x2, [x2, #0x30] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 68 82: JIT compiled BenchmarkDotNet.Engines.AnonymousPipesHost:WriteLine(System.String) [Tier0, IL size=13, code size=68] ; Assembly listing for method System.SpanHelpers:NonPackedIndexOfAnyValueType[short,System.SpanHelpers+DontNegate`1[short]](byref,short,short,int):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 19 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: cmp w3, #8 bge G_M000_IG22 G_M000_IG03: mov x4, xzr cmp w3, #4 blt G_M000_IG13 sxth w5, w1 align [0 bytes for IG04] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG04: sub w3, w3, #4 lsl x6, x4, #1 add x6, x0, x6 ldrsh w7, [x6] cmp w7, w5 beq G_M000_IG21 G_M000_IG05: sxth w8, w2 cmp w7, w8 cset x7, eq tst w7, #255 bne G_M000_IG21 G_M000_IG06: ldrsh w7, [x6, #0x02] cmp w7, w5 beq G_M000_IG20 G_M000_IG07: cmp w7, w8 cset x7, eq tst w7, #255 bne G_M000_IG20 G_M000_IG08: ldrsh w7, [x6, #0x04] cmp w7, w5 beq G_M000_IG19 G_M000_IG09: cmp w7, w8 cset x7, eq tst w7, #255 bne G_M000_IG19 G_M000_IG10: ldrsh w7, [x6, #0x06] cmp w7, w5 beq G_M000_IG18 G_M000_IG11: cmp w7, w8 cset x7, eq tst w7, #255 bne G_M000_IG18 G_M000_IG12: add x4, x4, #4 cmp w3, #4 bge G_M000_IG04 G_M000_IG13: cmp w3, #0 ble G_M000_IG28 sxth w5, w1 align [4 bytes for IG14] align [4 bytes] align [0 bytes] align [0 bytes] G_M000_IG14: sub w3, w3, #1 lsl x8, x4, #1 ldrsh w7, [x0, x8] cmp w7, w5 beq G_M000_IG21 G_M000_IG15: sxth w8, w2 cmp w7, w8 cset x1, eq tst w1, #255 bne G_M000_IG21 G_M000_IG16: add x4, x4, #1 cmp w3, #0 bgt G_M000_IG14 G_M000_IG17: b G_M000_IG28 G_M000_IG18: add w4, w4, #3 b G_M000_IG26 G_M000_IG19: add w4, w4, #2 b G_M000_IG26 G_M000_IG20: add w4, w4, #1 b G_M000_IG26 G_M000_IG21: b G_M000_IG26 G_M000_IG22: sxth w5, w1 dup v16.8h, w5 sxth w8, w2 dup v17.8h, w8 mov x1, x0 sub w4, w3, #8 sbfiz x2, x4, #1, #32 add x4, x1, x2 align [0 bytes for IG23] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG23: ldr q18, [x1] cmeq v19.8h, v16.8h, v18.8h cmeq v18.8h, v17.8h, v18.8h orr v18.8h, v19.8h, v18.8h umaxp v19.4s, v18.4s, v18.4s umov x5, v19.d[0] cmp x5, #0 bne G_M000_IG25 add x1, x1, #16 cmp x1, x4 bls G_M000_IG23 G_M000_IG24: mov w0, w3 tst w0, #7 beq G_M000_IG28 ldr q18, [x4] cmeq v16.8h, v16.8h, v18.8h cmeq v17.8h, v17.8h, v18.8h orr v18.8h, v16.8h, v17.8h umaxp v16.4s, v18.4s, v18.4s umov x1, v16.d[0] cmp x1, #0 beq G_M000_IG28 lsr x0, x2, #1 ldr q16, [@RWD00] and v18.8h, v18.8h, v16.8h ldr q16, [@RWD16] ushl v16.8h, v18.8h, v16.8h addv h16, v16.8h umov w1, v16.h[0] rbit w1, w1 clz w1, w1 add w4, w0, w1 b G_M000_IG26 G_M000_IG25: sub x4, x1, x0 lsr x0, x4, #1 ldr q16, [@RWD00] and v16.8h, v18.8h, v16.8h ldr q17, [@RWD16] ushl v16.8h, v16.8h, v17.8h addv h16, v16.8h umov w1, v16.h[0] rbit w1, w1 clz w1, w1 add w4, w0, w1 G_M000_IG26: mov w0, w4 G_M000_IG27: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG28: movn w0, #0 G_M000_IG29: ldp fp, lr, [sp], #0x10 ret lr RWD00 dq 8000800080008000h, 8000800080008000h RWD16 dq FFF4FFF3FFF2FFF1h, FFF8FFF7FFF6FFF5h ; Total bytes of code 508 83: JIT compiled System.SpanHelpers:NonPackedIndexOfAnyValueType[short,System.SpanHelpers+DontNegate`1[short]](byref,short,short,int) [Tier1, IL size=1156, code size=508] ; Assembly listing for method BenchmarkDotNet.Autogenerated.UniqueProgramName+<>c:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 84: JIT compiled BenchmarkDotNet.Autogenerated.UniqueProgramName+<>c:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method BenchmarkDotNet.Autogenerated.UniqueProgramName+<>c:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 85: JIT compiled BenchmarkDotNet.Autogenerated.UniqueProgramName+<>c:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Linq.Enumerable:SkipWhile[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,bool]):System.Collections.Generic.IEnumerable`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] str x2, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x20] cbnz x0, G_M000_IG04 mov w0, #12 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x18] b G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x18] G_M000_IG07: ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG08: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 188 86: JIT compiled System.Linq.Enumerable:SkipWhile[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,bool]) [Tier0, IL size=28, code size=188] ; Assembly listing for method System.Linq.Enumerable:SkipWhileIterator[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,bool]):System.Collections.Generic.IEnumerable`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] str x2, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: ldr x0, [fp, #0x10] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movn w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x18] add x14, x14, #24 ldr x15, [fp, #0x28] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x18] add x14, x14, #40 ldr x15, [fp, #0x20] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x18] G_M000_IG06: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 172 87: JIT compiled System.Linq.Enumerable:SkipWhileIterator[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,bool]) [Tier0, IL size=22, code size=172] ; Assembly listing for method System.Linq.Enumerable+d__247`1[System.__Canon]:.ctor(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x18] ldr w1, [fp, #0x14] str w1, [x0, #0x38] bl System.Environment:get_CurrentManagedThreadId():int ldr x1, [fp, #0x18] str w0, [x1, #0x3C] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 72 88: JIT compiled System.Linq.Enumerable+d__247`1[System.__Canon]:.ctor(int) [Tier0, IL size=25, code size=72] ; Assembly listing for method System.Linq.Enumerable:Skip[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],int):System.Collections.Generic.IEnumerable`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp str xzr, [fp, #0x48] str x0, [fp, #0x68] str x0, [fp, #0x60] str x1, [fp, #0x58] str w2, [fp, #0x54] G_M000_IG02: ldr x0, [fp, #0x58] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr w0, [fp, #0x54] cmp w0, #0 bgt G_M000_IG13 ldr x0, [fp, #0x60] ldr x0, [x0, #0x10] ldr x0, [x0, #0x28] cbz x0, G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x60] ldr x0, [x0, #0x10] ldr x0, [x0, #0x28] str x0, [fp, #0x20] b G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x20] G_M000_IG06: ldr x0, [fp, #0x20] ldr x1, [fp, #0x58] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz x0, G_M000_IG10 ldr x0, [fp, #0x60] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x60] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x18] b G_M000_IG09 G_M000_IG08: ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x18] G_M000_IG09: ldr x0, [fp, #0x18] ldr x1, [fp, #0x58] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz x0, G_M000_IG12 G_M000_IG10: ldr x0, [fp, #0x58] G_M000_IG11: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG12: str wzr, [fp, #0x54] b G_M000_IG21 G_M000_IG13: ldr x0, [fp, #0x60] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG15 G_M000_IG14: ldr x0, [fp, #0x60] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x40] b G_M000_IG16 G_M000_IG15: ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x40] G_M000_IG16: ldr x0, [fp, #0x40] ldr x1, [fp, #0x58] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x48] ldr x0, [fp, #0x48] cbz x0, G_M000_IG21 ldr x0, [fp, #0x60] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] cbz x0, G_M000_IG18 G_M000_IG17: ldr x0, [fp, #0x60] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] str x0, [fp, #0x30] b G_M000_IG19 G_M000_IG18: ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x30] G_M000_IG19: ldr x0, [fp, #0x30] str x0, [fp, #0x28] ldr x0, [fp, #0x48] ldr x11, [fp, #0x28] ldr w1, [fp, #0x54] ldr x2, [fp, #0x28] ldr x2, [x2] blr x2 G_M000_IG20: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG21: ldr x0, [fp, #0x60] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] cbz x0, G_M000_IG23 G_M000_IG22: ldr x0, [fp, #0x60] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] str x0, [fp, #0x38] b G_M000_IG24 G_M000_IG23: ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x38] G_M000_IG24: ldr x0, [fp, #0x38] ldr x1, [fp, #0x58] ldr w2, [fp, #0x54] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG25: ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 576 89: JIT compiled System.Linq.Enumerable:Skip[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],int) [Tier0, IL size=63, code size=576] ; Assembly listing for method System.Linq.Enumerable:SkipIterator[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],int):System.Collections.Generic.IEnumerable`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp str xzr, [fp, #0x48] str xzr, [fp, #0x40] str xzr, [fp, #0x30] str xzr, [fp, #0x20] str x0, [fp, #0x68] str x0, [fp, #0x60] str x1, [fp, #0x58] str w2, [fp, #0x54] G_M000_IG02: ldr x0, [fp, #0x60] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x60] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x38] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x38] G_M000_IG05: ldr x0, [fp, #0x38] ldr x1, [fp, #0x58] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x48] ldr x0, [fp, #0x48] cbnz x0, G_M000_IG10 ldr x0, [fp, #0x60] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] cbz x0, G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x60] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] str x0, [fp, #0x18] b G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x18] G_M000_IG08: ldr x0, [fp, #0x18] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x58] ldr w2, [fp, #0x54] movn w3, #0 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x20] str x0, [fp, #0x40] ldr x0, [fp, #0x40] G_M000_IG09: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG10: ldr x0, [fp, #0x60] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] cbz x0, G_M000_IG12 G_M000_IG11: ldr x0, [fp, #0x60] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] str x0, [fp, #0x28] b G_M000_IG13 G_M000_IG12: ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x28] G_M000_IG13: ldr x0, [fp, #0x28] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] ldr x0, [fp, #0x30] ldr x1, [fp, #0x48] ldr w2, [fp, #0x54] movn w3, #0xD1FFAB1E LSL #16 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x30] str x0, [fp, #0x40] ldr x0, [fp, #0x40] G_M000_IG14: ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 396 90: JIT compiled System.Linq.Enumerable:SkipIterator[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],int) [Tier0, IL size=36, code size=396] ; Assembly listing for method System.Linq.Enumerable+EnumerablePartition`1[System.__Canon]:.ctor(System.Collections.Generic.IEnumerable`1[System.__Canon],int,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] str w3, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] add x14, x14, #24 ldr x15, [fp, #0x20] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x28] ldr w1, [fp, #0x1C] str w1, [x0, #0x28] ldr x0, [fp, #0x28] ldr w1, [fp, #0x18] str w1, [x0, #0x2C] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 91: JIT compiled System.Linq.Enumerable+EnumerablePartition`1[System.__Canon]:.ctor(System.Collections.Generic.IEnumerable`1[System.__Canon],int,int) [Tier0, IL size=28, code size=96] ; Assembly listing for method System.Linq.Enumerable+Iterator`1[System.__Canon]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 bl System.Environment:get_CurrentManagedThreadId():int ldr x1, [fp, #0x18] str w0, [x1, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 92: JIT compiled System.Linq.Enumerable+Iterator`1[System.__Canon]:.ctor() [Tier0, IL size=18, code size=56] ; Assembly listing for method System.Linq.Enumerable:FirstOrDefault[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon]):System.__Canon ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x2, [fp, #0x30] ldr x2, [x2, #0x10] ldr x2, [x2, #0x10] str x2, [fp, #0x18] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x18] G_M000_IG05: add x2, fp, #32 ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG06: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 120 93: JIT compiled System.Linq.Enumerable:FirstOrDefault[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon]) [Tier0, IL size=9, code size=120] ; Assembly listing for method System.Linq.Enumerable:TryGetFirst[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],byref):System.__Canon ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0xE0]! mov fp, sp add x9, fp, #144 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] add x3, sp, #224 str x3, [fp, #0xD8] str x0, [fp, #0xD0] str x0, [fp, #0xC8] str x1, [fp, #0xC0] str x2, [fp, #0xB8] G_M000_IG02: ldr x0, [fp, #0xC0] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0xC8] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0xC8] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x88] b G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0xC8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x88] G_M000_IG06: ldr x0, [fp, #0x88] ldr x1, [fp, #0xC0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xB0] ldr x0, [fp, #0xB0] cbz x0, G_M000_IG12 ldr x0, [fp, #0xC8] ldr x0, [x0, #0x10] str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] cmp x0, #64 ble G_M000_IG09 G_M000_IG07: ldr x0, [fp, #0x28] ldr x0, [x0, #0x40] cbz x0, G_M000_IG09 G_M000_IG08: ldr x0, [fp, #0x28] ldr x0, [x0, #0x40] str x0, [fp, #0x38] b G_M000_IG10 G_M000_IG09: ldr x0, [fp, #0xC8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x38] G_M000_IG10: ldr x0, [fp, #0x38] str x0, [fp, #0x30] ldr x0, [fp, #0xB0] ldr x11, [fp, #0x30] ldr x1, [fp, #0xB8] ldr x2, [fp, #0x30] ldr x2, [x2] blr x2 G_M000_IG11: ldp fp, lr, [sp], #0xE0 ret lr G_M000_IG12: ldr x0, [fp, #0xC8] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] cbz x0, G_M000_IG14 G_M000_IG13: ldr x0, [fp, #0xC8] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] str x0, [fp, #0x80] b G_M000_IG15 G_M000_IG14: ldr x0, [fp, #0xC8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x80] G_M000_IG15: ldr x0, [fp, #0x80] ldr x1, [fp, #0xC0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xA8] ldr x0, [fp, #0xA8] cbz x0, G_M000_IG25 ldr x0, [fp, #0xC8] ldr x0, [x0, #0x10] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x0, [x0, #0x08] cmp x0, #48 ble G_M000_IG18 G_M000_IG16: ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] cbz x0, G_M000_IG18 G_M000_IG17: ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] str x0, [fp, #0x58] b G_M000_IG19 G_M000_IG18: ldr x0, [fp, #0xC8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x58] G_M000_IG19: ldr x0, [fp, #0x58] str x0, [fp, #0x50] ldr x0, [fp, #0xA8] ldr x11, [fp, #0x50] ldr x1, [fp, #0x50] ldr x1, [x1] blr x1 cmp w0, #0 ble G_M000_IG38 ldr x0, [fp, #0xB8] mov w1, #1 strb w1, [x0] ldr x0, [fp, #0xC8] ldr x0, [x0, #0x10] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] cmp x0, #56 ble G_M000_IG22 G_M000_IG20: ldr x0, [fp, #0x18] ldr x0, [x0, #0x38] cbz x0, G_M000_IG22 G_M000_IG21: ldr x0, [fp, #0x18] ldr x0, [x0, #0x38] str x0, [fp, #0x48] b G_M000_IG23 G_M000_IG22: ldr x0, [fp, #0xC8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x48] G_M000_IG23: ldr x0, [fp, #0x48] str x0, [fp, #0x40] ldr x0, [fp, #0xA8] ldr x11, [fp, #0x40] mov w1, wzr ldr x2, [fp, #0x40] ldr x2, [x2] blr x2 G_M000_IG24: ldp fp, lr, [sp], #0xE0 ret lr G_M000_IG25: ldr x0, [fp, #0xC8] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] cbz x0, G_M000_IG27 G_M000_IG26: ldr x0, [fp, #0xC8] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] str x0, [fp, #0x78] b G_M000_IG28 G_M000_IG27: ldr x0, [fp, #0xC8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x78] G_M000_IG28: ldr x0, [fp, #0x78] str x0, [fp, #0x70] ldr x0, [fp, #0xC0] ldr x11, [fp, #0x70] ldr x1, [fp, #0x70] ldr x1, [x1] blr x1 str x0, [fp, #0xA0] G_M000_IG29: ldr x0, [fp, #0xA0] movz x11, #232 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbz w0, G_M000_IG33 ldr x0, [fp, #0xB8] mov w11, #1 strb w11, [x0] ldr x0, [fp, #0xC8] ldr x0, [x0, #0x10] ldr x0, [x0, #0x28] cbz x0, G_M000_IG31 G_M000_IG30: ldr x0, [fp, #0xC8] ldr x0, [x0, #0x10] ldr x0, [x0, #0x28] str x0, [fp, #0x68] b G_M000_IG32 G_M000_IG31: ldr x0, [fp, #0xC8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x68] G_M000_IG32: ldr x0, [fp, #0x68] str x0, [fp, #0x60] ldr x0, [fp, #0xA0] ldr x11, [fp, #0x60] ldr x1, [fp, #0x60] ldr x1, [x1] blr x1 str x0, [fp, #0x98] b G_M000_IG34 G_M000_IG33: b G_M000_IG36 G_M000_IG34: ldr x0, [fp, #0xD8] bl G_M000_IG42 G_M000_IG35: b G_M000_IG40 G_M000_IG36: ldr x0, [fp, #0xD8] bl G_M000_IG42 G_M000_IG37: nop G_M000_IG38: ldr x0, [fp, #0xB8] strb wzr, [x0] str xzr, [fp, #0x90] ldr x0, [fp, #0x90] G_M000_IG39: ldp fp, lr, [sp], #0xE0 ret lr G_M000_IG40: ldr x0, [fp, #0x98] G_M000_IG41: ldp fp, lr, [sp], #0xE0 ret lr G_M000_IG42: stp fp, lr, [sp, #-0x20]! add x3, fp, #224 str x3, [sp, #0x18] G_M000_IG43: ldr x0, [fp, #0xA0] cbz x0, G_M000_IG44 ldr x0, [fp, #0xA0] movz x11, #240 movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG44: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 992 94: JIT compiled System.Linq.Enumerable:TryGetFirst[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],byref) [Tier0, IL size=113, code size=992] ; Assembly listing for method System.Linq.Enumerable+EnumerablePartition`1[System.__Canon]:TryGetFirst(byref):System.__Canon:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp str xzr, [fp, #0x58] str xzr, [fp, #0x50] str xzr, [fp, #0x48] add x2, sp, #128 str x2, [fp, #0x78] str x0, [fp, #0x70] str x0, [fp, #0x68] str x1, [fp, #0x60] G_M000_IG02: ldr x0, [fp, #0x68] ldr x0, [x0] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x10] str x0, [fp, #0x40] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x40] G_M000_IG05: ldr x0, [fp, #0x40] str x0, [fp, #0x38] ldr x0, [fp, #0x68] ldr x0, [x0, #0x18] ldr x11, [fp, #0x38] ldr x1, [fp, #0x38] ldr x1, [x1] blr x1 str x0, [fp, #0x58] G_M000_IG06: ldr x0, [fp, #0x68] ldr x1, [fp, #0x58] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG10 ldr x0, [fp, #0x58] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbz w0, G_M000_IG10 ldr x0, [fp, #0x60] mov w11, #1 strb w11, [x0] ldr x0, [fp, #0x68] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x18] cbz x0, G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x18] str x0, [fp, #0x30] b G_M000_IG09 G_M000_IG08: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x30] G_M000_IG09: ldr x0, [fp, #0x30] str x0, [fp, #0x28] ldr x0, [fp, #0x58] ldr x11, [fp, #0x28] ldr x1, [fp, #0x28] ldr x1, [x1] blr x1 str x0, [fp, #0x50] b G_M000_IG11 G_M000_IG10: b G_M000_IG13 G_M000_IG11: ldr x0, [fp, #0x78] bl G_M000_IG19 G_M000_IG12: b G_M000_IG17 G_M000_IG13: ldr x0, [fp, #0x78] bl G_M000_IG19 G_M000_IG14: nop G_M000_IG15: ldr x0, [fp, #0x60] strb wzr, [x0] str xzr, [fp, #0x48] ldr x0, [fp, #0x48] G_M000_IG16: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG17: ldr x0, [fp, #0x50] G_M000_IG18: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG19: stp fp, lr, [sp, #-0x20]! add x3, fp, #128 str x3, [sp, #0x18] G_M000_IG20: ldr x0, [fp, #0x58] cbz x0, G_M000_IG21 ldr x0, [fp, #0x58] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG21: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 460 95: JIT compiled System.Linq.Enumerable+EnumerablePartition`1[System.__Canon]:TryGetFirst(byref) [Tier0, IL size=68, code size=460] ; Assembly listing for method System.Linq.Enumerable+d__247`1[System.__Canon]:System.Collections.Generic.IEnumerable.GetEnumerator():System.Collections.Generic.IEnumerator`1[System.__Canon]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str x0, [fp, #0x38] str x0, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x30] ldr w0, [x0, #0x38] cmn w0, #2 bne G_M000_IG03 ldr x0, [fp, #0x30] ldr w0, [x0, #0x3C] str w0, [fp, #0x1C] bl System.Environment:get_CurrentManagedThreadId():int ldr w1, [fp, #0x1C] cmp w0, w1 bne G_M000_IG03 ldr x0, [fp, #0x30] str wzr, [x0, #0x38] ldr x0, [fp, #0x30] str x0, [fp, #0x28] b G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x30] ldr x0, [x0] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] mov w1, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x20] str x14, [fp, #0x28] G_M000_IG04: ldr x14, [fp, #0x30] ldr x15, [x14, #0x18] ldr x14, [fp, #0x28] add x14, x14, #16 bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x30] ldr x15, [x14, #0x28] ldr x14, [fp, #0x28] add x14, x14, #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x28] G_M000_IG05: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 192 96: JIT compiled System.Linq.Enumerable+d__247`1[System.__Canon]:System.Collections.Generic.IEnumerable.GetEnumerator() [Tier0, IL size=67, code size=192] ; Assembly listing for method System.Linq.Enumerable+EnumerablePartition`1[System.__Canon]:SkipBeforeFirst(System.Collections.Generic.IEnumerator`1[System.__Canon]):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x0, [fp, #0x20] str x1, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x20] ldr x0, [x0] ldr x1, [fp, #0x20] ldr w1, [x1, #0x28] ldr x2, [fp, #0x18] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 68 97: JIT compiled System.Linq.Enumerable+EnumerablePartition`1[System.__Canon]:SkipBeforeFirst(System.Collections.Generic.IEnumerator`1[System.__Canon]) [Tier0, IL size=13, code size=68] ; Assembly listing for method System.Linq.Enumerable+EnumerablePartition`1[System.__Canon]:SkipBefore(int,System.Collections.Generic.IEnumerator`1[System.__Canon]):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x0, [fp, #0x20] str w1, [fp, #0x1C] str x2, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x20] ldr w1, [fp, #0x1C] ldr x2, [fp, #0x10] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr w1, [fp, #0x1C] cmp w0, w1 cset x0, eq G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 76 98: JIT compiled System.Linq.Enumerable+EnumerablePartition`1[System.__Canon]:SkipBefore(int,System.Collections.Generic.IEnumerator`1[System.__Canon]) [Tier0, IL size=11, code size=76] ; Assembly listing for method System.Linq.Enumerable+EnumerablePartition`1[System.__Canon]:SkipAndCount(int,System.Collections.Generic.IEnumerator`1[System.__Canon]):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x0, [fp, #0x20] str w1, [fp, #0x1C] str x2, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x20] ldr w1, [fp, #0x1C] ldr x2, [fp, #0x10] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 64 99: JIT compiled System.Linq.Enumerable+EnumerablePartition`1[System.__Canon]:SkipAndCount(int,System.Collections.Generic.IEnumerator`1[System.__Canon]) [Tier0, IL size=8, code size=64] ; Assembly listing for method System.Linq.Enumerable+EnumerablePartition`1[System.__Canon]:SkipAndCount(uint,System.Collections.Generic.IEnumerator`1[System.__Canon]):uint ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x0, [fp, #0x30] str w1, [fp, #0x2C] str x2, [fp, #0x20] G_M000_IG02: str wzr, [fp, #0x1C] mov w0, #0xD1FFAB1E str w0, [fp, #0x10] b G_M000_IG06 G_M000_IG03: ldr x0, [fp, #0x20] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG05 ldr w0, [fp, #0x1C] G_M000_IG04: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG05: ldr w0, [fp, #0x1C] add w0, w0, #1 str w0, [fp, #0x1C] G_M000_IG06: ldr w0, [fp, #0x10] sub w0, w0, #1 str w0, [fp, #0x10] ldr w0, [fp, #0x10] cmp w0, #0 bgt G_M000_IG08 G_M000_IG07: add x0, fp, #16 mov w1, #18 bl CORINFO_HELP_PATCHPOINT G_M000_IG08: ldr w0, [fp, #0x1C] ldr w11, [fp, #0x2C] cmp w0, w11 blo G_M000_IG03 ldr w0, [fp, #0x2C] G_M000_IG09: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 156 100: JIT compiled System.Linq.Enumerable+EnumerablePartition`1[System.__Canon]:SkipAndCount(uint,System.Collections.Generic.IEnumerator`1[System.__Canon]) [Tier0, IL size=24, code size=156] ; Assembly listing for method System.Linq.Enumerable+d__247`1[System.__Canon]:MoveNext():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x90]! mov fp, sp str xzr, [fp, #0x68] str xzr, [fp, #0x10] add x1, sp, #144 str x1, [fp, #0x88] str x0, [fp, #0x80] str x0, [fp, #0x78] G_M000_IG02: ldr x0, [fp, #0x78] ldr w0, [x0, #0x38] str w0, [fp, #0x70] mov w0, #0xD1FFAB1E str w0, [fp, #0x30] ldr w0, [fp, #0x70] cmp w0, #2 bhi G_M000_IG03 ldr w0, [fp, #0x70] mov w0, w0 adr x1, [@RWD00] ldr w1, [x1, x0, LSL #2] adr x2, [G_M000_IG02] add x1, x1, x2 br x1 G_M000_IG03: str wzr, [fp, #0x74] b G_M000_IG26 G_M000_IG04: ldr x0, [fp, #0x78] movn w1, #0 str w1, [x0, #0x38] ldr x0, [fp, #0x78] ldr x0, [x0] str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] cbz x0, G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x28] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] str x0, [fp, #0x50] b G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x50] G_M000_IG07: ldr x0, [fp, #0x50] str x0, [fp, #0x48] ldr x0, [fp, #0x78] ldr x0, [x0, #0x10] ldr x11, [fp, #0x48] ldr x1, [fp, #0x48] ldr x1, [x1] blr x1 ldr x14, [fp, #0x78] add x14, x14, #48 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x78] movn w1, #2 str w1, [x0, #0x38] b G_M000_IG21 G_M000_IG08: ldr x0, [fp, #0x78] ldr x0, [x0] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x10] cbz x0, G_M000_IG10 G_M000_IG09: ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x10] str x0, [fp, #0x40] b G_M000_IG11 G_M000_IG10: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x40] G_M000_IG11: ldr x0, [fp, #0x40] str x0, [fp, #0x38] ldr x0, [fp, #0x78] ldr x0, [x0, #0x30] ldr x11, [fp, #0x38] ldr x1, [fp, #0x38] ldr x1, [x1] blr x1 str x0, [fp, #0x68] ldr x0, [fp, #0x78] ldr x0, [x0, #0x20] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x08] ldr x1, [fp, #0x68] ldr x2, [fp, #0x10] ldr x2, [x2, #0x18] blr x2 cbnz w0, G_M000_IG21 ldr x14, [fp, #0x78] add x14, x14, #8 ldr x15, [fp, #0x68] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x78] mov w1, #1 str w1, [x0, #0x38] mov w1, #1 str w1, [fp, #0x74] b G_M000_IG26 G_M000_IG12: ldr x0, [fp, #0x78] movn w1, #2 str w1, [x0, #0x38] b G_M000_IG18 G_M000_IG13: ldr x0, [fp, #0x78] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x10] cbz x0, G_M000_IG15 G_M000_IG14: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x10] str x0, [fp, #0x60] b G_M000_IG16 G_M000_IG15: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x60] G_M000_IG16: ldr x0, [fp, #0x60] str x0, [fp, #0x58] ldr x0, [fp, #0x78] ldr x0, [x0, #0x30] ldr x11, [fp, #0x58] ldr x1, [fp, #0x58] ldr x1, [x1] blr x1 ldr x14, [fp, #0x78] add x14, x14, #8 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x78] mov w1, #2 str w1, [x0, #0x38] mov w0, #1 str w0, [fp, #0x74] b G_M000_IG26 G_M000_IG17: ldr x0, [fp, #0x78] movn w1, #2 str w1, [x0, #0x38] G_M000_IG18: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG20 G_M000_IG19: add x0, fp, #48 mov w1, #156 bl CORINFO_HELP_PATCHPOINT G_M000_IG20: ldr x0, [fp, #0x78] ldr x0, [x0, #0x30] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG13 str wzr, [fp, #0x74] b G_M000_IG24 G_M000_IG21: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG23 G_M000_IG22: add x0, fp, #48 mov w1, #173 bl CORINFO_HELP_PATCHPOINT G_M000_IG23: ldr x0, [fp, #0x78] ldr x0, [x0, #0x30] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG08 ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 b G_M000_IG25 G_M000_IG24: ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 b G_M000_IG26 G_M000_IG25: ldr x0, [fp, #0x78] str xzr, [x0, #0x30] str wzr, [fp, #0x74] b G_M000_IG26 G_M000_IG26: ldr w0, [fp, #0x74] G_M000_IG27: ldp fp, lr, [sp], #0x90 ret lr G_M000_IG28: stp fp, lr, [sp, #-0x20]! add x3, fp, #144 str x3, [sp, #0x18] G_M000_IG29: ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG30: ldp fp, lr, [sp], #0x20 ret lr RWD00 dd G_M000_IG04 - G_M000_IG02 dd G_M000_IG12 - G_M000_IG02 dd G_M000_IG17 - G_M000_IG02 ; Total bytes of code 904 101: JIT compiled System.Linq.Enumerable+d__247`1[System.__Canon]:MoveNext() [Tier0, IL size=222, code size=904] ; Assembly listing for method BenchmarkDotNet.Autogenerated.UniqueProgramName+<>c:b__1_0(System.String):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 60 102: JIT compiled BenchmarkDotNet.Autogenerated.UniqueProgramName+<>c:b__1_0(System.String) [Tier0, IL size=12, code size=60] ; Assembly listing for method System.Linq.Enumerable+d__247`1[System.__Canon]:System.Collections.Generic.IEnumerator.get_Current():System.__Canon:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 103: JIT compiled System.Linq.Enumerable+d__247`1[System.__Canon]:System.Collections.Generic.IEnumerator.get_Current() [Tier0, IL size=7, code size=28] ; Assembly listing for method System.Linq.Enumerable+d__247`1[System.__Canon]:System.IDisposable.Dispose():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp add x1, sp, #48 str x1, [fp, #0x28] str x0, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x20] ldr w0, [x0, #0x38] str w0, [fp, #0x1C] ldr w0, [fp, #0x1C] cmn w0, #3 beq G_M000_IG03 ldr w0, [fp, #0x1C] sub w0, w0, #1 cmp w0, #1 bhi G_M000_IG06 G_M000_IG03: b G_M000_IG04 G_M000_IG04: ldr x0, [fp, #0x28] bl G_M000_IG07 G_M000_IG05: nop G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG07: stp fp, lr, [sp, #-0x20]! add x3, fp, #48 str x3, [sp, #0x18] G_M000_IG08: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG09: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 128 104: JIT compiled System.Linq.Enumerable+d__247`1[System.__Canon]:System.IDisposable.Dispose() [Tier0, IL size=29, code size=128] ; Assembly listing for method System.Linq.Enumerable+d__247`1[System.__Canon]:<>m__Finally1():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movn w11, #0 str w11, [x0, #0x38] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] cbz x0, G_M000_IG03 ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 72 105: JIT compiled System.Linq.Enumerable+d__247`1[System.__Canon]:<>m__Finally1() [Tier0, IL size=27, code size=72] ; Assembly listing for method (dynamicClass):InvokeStub_EventSourceAttribute.set_Guid(System.Object,System.Object,ulong):System.Object ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp mov x0, x1 G_M000_IG02: ldr x1, [x2] ldr x1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 mov x0, xzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 56 106: JIT compiled (dynamicClass):InvokeStub_EventSourceAttribute.set_Guid(System.Object,System.Object,ulong) [FullOpts, IL size=25, code size=56] ; Assembly listing for method (dynamicClass):InvokeStub_EventSourceAttribute.set_Name(System.Object,System.Object,ulong):System.Object ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp mov x0, x1 G_M000_IG02: ldr x1, [x2] ldr x1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 mov x0, xzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 56 107: JIT compiled (dynamicClass):InvokeStub_EventSourceAttribute.set_Name(System.Object,System.Object,ulong) [FullOpts, IL size=25, code size=56] ; Assembly listing for method BenchmarkDotNet.Autogenerated.Runnable_0:Run(BenchmarkDotNet.Engines.IHost,System.String) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: sub sp, sp, #0xD1FFAB1E stp fp, lr, [sp] mov fp, sp movi v16.16b, #0 add x9, fp, #80 add x10, fp, #0xD1FFAB1E stp q16, q16, [x9, #-0x40] stp q16, q16, [x9, #-0x20] bfm x9, xzr, #0, #5 dczva x9 add x9, x9, #64 cmp x9, x10 blo pc-16 (-4 instructions) stp q16, q16, [x10] stp q16, q16, [x10, #0x20] add x2, sp, #0xD1FFAB1E str x2, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] str x1, [fp, #0xD1FFAB1E] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0xD0] ldr x0, [fp, #0xD0] ldr x1, [fp, #0xD0] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x20] blr x1 str x0, [fp, #0xC8] ldr x0, [fp, #0xC8] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0xD1FFAB1E] mov w0, #0xD1FFAB1E str w0, [fp, #0xD8] G_M000_IG03: b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0xD1FFAB1E] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xC0] ldr x1, [fp, #0xC0] ldr x0, [fp, #0xD1FFAB1E] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 G_M000_IG05: ldr w0, [fp, #0xD8] sub w0, w0, #1 str w0, [fp, #0xD8] ldr w0, [fp, #0xD8] cmp w0, #0 bgt G_M000_IG07 G_M000_IG06: add x0, fp, #216 mov w1, #56 bl CORINFO_HELP_PATCHPOINT G_M000_IG07: ldr x0, [fp, #0xD1FFAB1E] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG04 b G_M000_IG08 G_M000_IG08: ldr x0, [fp, #0xD1FFAB1E] bl G_M000_IG21 G_M000_IG09: nop G_M000_IG10: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD1FFAB1E] str x1, [fp, #0xD1FFAB1E] stp xzr, xzr, [fp, #0xD1FFAB1E] str wzr, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] add x0, fp, #0xD1FFAB1E movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xA0] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x98] ldp x0, x1, [fp, #0xD1FFAB1E] stp x0, x1, [fp, #0xA8] ldr w0, [fp, #0xD1FFAB1E] str w0, [fp, #0xB8] ldr x0, [fp, #0xA0] ldr x1, [fp, #0x98] add x2, fp, #168 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 str xzr, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] add x0, fp, #0xD1FFAB1E ldr d0, [@RWD00] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr d0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x90] ldr x0, [fp, #0x90] ldr x1, [fp, #0xD1FFAB1E] mov w2, #20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x88] ldr x0, [fp, #0x88] ldr x1, [fp, #0xD1FFAB1E] mov w2, #15 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x80] ldr x0, [fp, #0x80] ldr x1, [fp, #0xD1FFAB1E] mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x78] ldr x1, [fp, #0x78] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x70] ldr x1, [fp, #0x70] ldr x0, [fp, #0xD1FFAB1E] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 ldr x0, [fp, #0xD1FFAB1E] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E G_M000_IG11: movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x68] ldr x0, [fp, #0x68] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG13 G_M000_IG12: ldp fp, lr, [sp] add sp, sp, #0xD1FFAB1E ret lr G_M000_IG13: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xF8] ldr x0, [fp, #0xF8] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xF8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xF0] ldr x0, [fp, #0xF0] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xF0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xE8] ldr x0, [fp, #0xE8] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xE8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 G_M000_IG14: movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x1, [fp, #0xD1FFAB1E] ldr x1, [x1, #0x08] ldr x0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x1, [fp, #0xD1FFAB1E] ldr x1, [x1, #0x10] ldr x0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x1, [fp, #0xD1FFAB1E] ldr x1, [x1, #0x18] ldr x0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x1, [fp, #0xD1FFAB1E] ldr x1, [x1, #0x20] ldr x0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xD1FFAB1E] mov x1, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xD1FFAB1E] mov w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xE0] ldr x0, [fp, #0xE0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xE0] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xD1FFAB1E] G_M000_IG15: add x8, fp, #0xD1FFAB1E ldr x0, [fp, #0xD1FFAB1E] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x10] G_M000_IG16: ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x18] ldp q16, q17, [fp, #0xD1FFAB1E] stp q16, q17, [fp, #0x20] ldp q16, q17, [fp, #0xD1FFAB1E] stp q16, q17, [fp, #0x40] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x60] G_M000_IG17: ldr x0, [fp, #0x10] add x1, fp, #24 movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 b G_M000_IG18 G_M000_IG18: ldr x0, [fp, #0xD1FFAB1E] bl G_M000_IG24 G_M000_IG19: nop G_M000_IG20: ldp fp, lr, [sp] add sp, sp, #0xD1FFAB1E ret lr G_M000_IG21: stp fp, lr, [sp, #-0x20]! add x3, fp, #0xD1FFAB1E str x3, [sp, #0x18] G_M000_IG22: ldr x0, [fp, #0xD1FFAB1E] cbz x0, G_M000_IG23 ldr x0, [fp, #0xD1FFAB1E] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG23: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG24: stp fp, lr, [sp, #-0x20]! add x3, fp, #0xD1FFAB1E str x3, [sp, #0x18] G_M000_IG25: ldr x0, [fp, #0xD1FFAB1E] cbz x0, G_M000_IG26 ldr x0, [fp, #0xD1FFAB1E] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG26: ldp fp, lr, [sp], #0x20 ret lr RWD00 dq 41ADCD6500000000h ; 250000000 ; Total bytes of code 2552 108: JIT compiled BenchmarkDotNet.Autogenerated.Runnable_0:Run(BenchmarkDotNet.Engines.IHost,System.String) [Tier0, IL size=492, code size=2552] ; Assembly listing for method BenchmarkDotNet.Autogenerated.Runnable_0:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xB0]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] stp xzr, xzr, [x9, #0x80] str x0, [fp, #0xA8] G_M000_IG02: ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xA0] ldr x0, [fp, #0xA0] ldr x1, [fp, #0xA8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x14, [fp, #0xA8] add x14, x14, #8 ldr x15, [fp, #0xA0] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #6 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x98] ldr x0, [fp, #0xA8] str x0, [fp, #0x90] ldr x0, [fp, #0x98] str x0, [fp, #0x88] ldr x0, [fp, #0x98] cbnz x0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #6 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x28] ldr x1, [fp, #0x28] ldr x0, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #6 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x30] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x30] str x14, [fp, #0x88] G_M000_IG03: ldr x14, [fp, #0x90] add x14, x14, #16 ldr x15, [fp, #0x88] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #6 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x80] ldr x0, [fp, #0xA8] str x0, [fp, #0x78] ldr x0, [fp, #0x80] str x0, [fp, #0x70] ldr x0, [fp, #0x80] cbnz x0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #6 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #6 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x38] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x38] str x14, [fp, #0x70] G_M000_IG04: ldr x14, [fp, #0x78] add x14, x14, #24 ldr x15, [fp, #0x70] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #6 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x68] ldr x0, [fp, #0xA8] str x0, [fp, #0x60] ldr x0, [fp, #0x68] str x0, [fp, #0x58] ldr x0, [fp, #0x68] cbnz x0, G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #6 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x40] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #6 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x40] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x40] str x14, [fp, #0x58] G_M000_IG05: ldr x14, [fp, #0x60] add x14, x14, #32 ldr x15, [fp, #0x58] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x50] ldr x0, [fp, #0x50] ldr x1, [fp, #0xA8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x14, [fp, #0xA8] add x14, x14, #40 ldr x15, [fp, #0x50] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] ldr x0, [fp, #0x48] ldr x1, [fp, #0xA8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x14, [fp, #0xA8] add x14, x14, #48 ldr x15, [fp, #0x48] bl CORINFO_HELP_ASSIGN_REF G_M000_IG06: ldp fp, lr, [sp], #0xB0 ret lr ; Total bytes of code 984 109: JIT compiled BenchmarkDotNet.Autogenerated.Runnable_0:.ctor() [Tier0, IL size=172, code size=984] ; Assembly listing for method System.Reflection.Invoke:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 110: JIT compiled System.Reflection.Invoke:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Autogenerated.Runnable_0+<>c:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 111: JIT compiled BenchmarkDotNet.Autogenerated.Runnable_0+<>c:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method BenchmarkDotNet.Autogenerated.Runnable_0+<>c:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 112: JIT compiled BenchmarkDotNet.Autogenerated.Runnable_0+<>c:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Engines.AnonymousPipesHost:WriteLine():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x1, [fp, #0x10] ldr x1, [x1] ldr x1, [x1, #0x60] ldr x1, [x1, #0x08] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 60 113: JIT compiled BenchmarkDotNet.Engines.AnonymousPipesHost:WriteLine() [Tier0, IL size=12, code size=60] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:GetCurrent():BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 68 114: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:GetCurrent() [Tier0, IL size=6, code size=68] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp add x9, fp, #56 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x0, [fp, #0x68] G_M000_IG02: ldr x0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x60] ldr x1, [fp, #0x60] ldr x0, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x58] ldr x1, [fp, #0x58] ldr x0, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x50] ldr x1, [fp, #0x50] ldr x0, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0x4C] ldr w1, [fp, #0x4C] ldr x0, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x40] ldr x1, [fp, #0x40] ldr x0, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x38] ldr x1, [fp, #0x38] ldr x0, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 bl System.Runtime.GCSettings:get_IsServerGC():bool str w0, [fp, #0x34] ldr w1, [fp, #0x34] ldr x0, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cmp w0, #0 cset x1, ne str w1, [fp, #0x30] ldr w1, [fp, #0x30] ldr x0, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 bl System.Diagnostics.Debugger:get_IsAttached():bool str w0, [fp, #0x2C] ldr w1, [fp, #0x2C] ldr x0, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0x1C] ldr w1, [fp, #0x1C] ldr x0, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 624 115: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:.ctor() [Tier0, IL size=131, code size=624] ; Assembly listing for method BenchmarkDotNet.Portability.RuntimeInformation:GetArchitecture():System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str wzr, [fp, #0x2C] str xzr, [fp, #0x20] str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0x2C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr w1, [fp, #0x2C] str w1, [x0, #0x08] ldr x0, [fp, #0x20] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x08] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 116 116: JIT compiled BenchmarkDotNet.Portability.RuntimeInformation:GetArchitecture() [Tier0, IL size=20, code size=116] ; Assembly listing for method BenchmarkDotNet.Portability.RuntimeInformation:GetCurrentPlatform():int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str wzr, [fp, #0x2C] str xzr, [fp, #0x20] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0x2C] ldr w0, [fp, #0x2C] cmp w0, #8 bhi G_M000_IG03 ldr w0, [fp, #0x2C] mov w0, w0 adr x1, [@RWD00] ldr w1, [x1, x0, LSL #2] adr x2, [G_M000_IG02] add x1, x1, x2 br x1 G_M000_IG03: b G_M000_IG19 G_M000_IG04: b G_M000_IG05 G_M000_IG05: mov w0, #3 G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG07: b G_M000_IG08 G_M000_IG08: mov w0, #4 G_M000_IG09: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG10: b G_M000_IG11 G_M000_IG11: mov w0, #2 G_M000_IG12: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG13: mov w0, #1 str w0, [fp, #0x1C] b G_M000_IG20 G_M000_IG14: mov w0, #5 str w0, [fp, #0x1C] b G_M000_IG20 G_M000_IG15: mov w0, #6 str w0, [fp, #0x1C] b G_M000_IG20 G_M000_IG16: mov w0, #7 str w0, [fp, #0x1C] b G_M000_IG20 G_M000_IG17: mov w0, #8 str w0, [fp, #0x1C] b G_M000_IG20 G_M000_IG18: mov w0, #9 str w0, [fp, #0x1C] b G_M000_IG20 G_M000_IG19: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x20] bl CORINFO_HELP_THROW G_M000_IG20: ldr w0, [fp, #0x1C] G_M000_IG21: ldp fp, lr, [sp], #0x30 ret lr RWD00 dd G_M000_IG13 - G_M000_IG02 dd G_M000_IG10 - G_M000_IG02 dd G_M000_IG04 - G_M000_IG02 dd G_M000_IG07 - G_M000_IG02 dd G_M000_IG14 - G_M000_IG02 dd G_M000_IG15 - G_M000_IG02 dd G_M000_IG16 - G_M000_IG02 dd G_M000_IG17 - G_M000_IG02 dd G_M000_IG18 - G_M000_IG02 ; Total bytes of code 268 117: JIT compiled BenchmarkDotNet.Portability.RuntimeInformation:GetCurrentPlatform() [Tier0, IL size=75, code size=268] ; Assembly listing for method System.UInt64:CreateTruncating[uint](uint):ulong ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str w0, [fp, #0x1C] G_M000_IG02: b G_M000_IG03 G_M000_IG03: add x1, fp, #16 ldr w0, [fp, #0x1C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG04 add x1, fp, #16 ldr w0, [fp, #0x1C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG04: ldr x0, [fp, #0x10] G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 112 118: JIT compiled System.UInt64:CreateTruncating[uint](uint) [Tier0, IL size=74, code size=112] ; Assembly listing for method System.UInt64:TryConvertFromTruncating[uint](uint,byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str w0, [fp, #0x5C] str x1, [fp, #0x50] G_M000_IG02: b G_M000_IG03 G_M000_IG03: b G_M000_IG04 G_M000_IG04: b G_M000_IG05 G_M000_IG05: b G_M000_IG06 G_M000_IG06: ldr w0, [fp, #0x5C] str w0, [fp, #0x30] ldr w0, [fp, #0x30] mov w0, w0 ldr x1, [fp, #0x50] str x0, [x1] mov w0, #1 G_M000_IG07: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 68 119: JIT compiled System.UInt64:TryConvertFromTruncating[uint](uint,byref) [Tier0, IL size=371, code size=68] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_Architecture(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #8 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 120: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_Architecture(System.String) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Portability.RuntimeInformation:GetRuntimeVersion():System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xD0]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] stp q16, q16, [x9, #0x80] stp xzr, xzr, [x9, #0xA0] str xzr, [x9, #0xB0] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x30] ldr x0, [fp, #0x30] ldr x1, [fp, #0x30] ldr x1, [x1] ldr x1, [x1, #0x50] ldr x1, [x1, #0x28] blr x1 str x0, [fp, #0x28] ldr x1, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x50] ldr x0, [fp, #0x50] str x0, [fp, #0x48] ldr x0, [fp, #0x50] cbnz x0, G_M000_IG03 str xzr, [fp, #0x40] b G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x40] G_M000_IG04: ldr x0, [fp, #0x40] str x0, [fp, #0xC8] ldr x0, [fp, #0xC8] cbz x0, G_M000_IG05 ldr x0, [fp, #0xC8] mov w1, #43 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 str w0, [fp, #0xC4] ldr w0, [fp, #0xC4] cmn w0, #1 beq G_M000_IG05 ldr x0, [fp, #0xC8] ldr w2, [fp, #0xC4] mov w1, wzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 str x0, [fp, #0xC8] G_M000_IG05: ldr x1, [fp, #0xC8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x38] b G_M000_IG17 G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG12 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x98] ldr x0, [fp, #0x98] str x0, [fp, #0x90] ldr x0, [fp, #0x98] cbnz x0, G_M000_IG07 str xzr, [fp, #0x88] b G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 mov w2, #56 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x88] G_M000_IG08: ldr x0, [fp, #0x88] str x0, [fp, #0xB8] ldr x0, [fp, #0xB8] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG16 ldr x0, [fp, #0xB8] mov x1, xzr mov x2, xzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 str x0, [fp, #0x80] ldr x0, [fp, #0x80] str x0, [fp, #0x78] ldr x0, [fp, #0x80] cbnz x0, G_M000_IG09 str xzr, [fp, #0x70] b G_M000_IG10 G_M000_IG09: ldr x0, [fp, #0x78] ldr x1, [fp, #0x78] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x08] blr x1 str x0, [fp, #0x70] G_M000_IG10: ldr x0, [fp, #0x70] str x0, [fp, #0xB0] ldr x0, [fp, #0xB0] cbz x0, G_M000_IG11 ldr x0, [fp, #0xB0] mov w1, #40 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 str w0, [fp, #0xAC] ldr x0, [fp, #0xB0] mov w1, #41 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 str w0, [fp, #0xA8] ldr w2, [fp, #0xAC] cmn w2, #1 beq G_M000_IG11 ldr w2, [fp, #0xA8] cmn w2, #1 beq G_M000_IG11 ldr w2, [fp, #0xA8] ldr w1, [fp, #0xAC] sub w2, w2, w1 sub w2, w2, #1 ldr w1, [fp, #0xAC] add w1, w1, #1 ldr x0, [fp, #0xB0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 str x0, [fp, #0x60] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, #1 bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x68] ldr x0, [fp, #0x68] mov w1, wzr ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG19 add x0, x0, x1, LSL #1 add x0, x0, #16 mov w1, #32 strh w1, [x0] ldr x0, [fp, #0x60] ldr x1, [fp, #0x68] mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 str x0, [fp, #0xA0] ldr x0, [fp, #0xA0] ldr w0, [x0, #0x08] cmp w0, #2 ble G_M000_IG11 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, #6 bl CORINFO_HELP_NEWARR_1_OBJ str x0, [fp, #0x58] ldr x0, [fp, #0xB0] ldr w2, [fp, #0xAC] mov w1, wzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 str x0, [fp, #0x20] ldr x2, [fp, #0x20] ldr x0, [fp, #0x58] mov x1, xzr bl CORINFO_HELP_ARRADDR_ST ldr x0, [fp, #0x58] mov x1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ARRADDR_ST ldr x2, [fp, #0xA0] mov w0, wzr ldr w1, [x2, #0x08] cmp w0, w1 bhs G_M000_IG19 add x2, x2, x0, LSL #3 add x2, x2, #16 ldr x2, [x2] ldr x0, [fp, #0x58] mov x1, #2 bl CORINFO_HELP_ARRADDR_ST ldr x0, [fp, #0x58] mov x1, #3 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ARRADDR_ST ldr x2, [fp, #0xA0] mov w0, #1 ldr w1, [x2, #0x08] cmp w0, w1 bhs G_M000_IG19 add x2, x2, x0, LSL #3 add x2, x2, #16 ldr x2, [x2] ldr x0, [fp, #0x58] mov x1, #4 bl CORINFO_HELP_ARRADDR_ST ldr x0, [fp, #0x58] mov x1, #5 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ARRADDR_ST ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xB0] G_M000_IG11: ldr x1, [fp, #0xB0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x38] b G_M000_IG17 G_M000_IG12: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG13 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x38] b G_M000_IG17 G_M000_IG13: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG14 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x38] b G_M000_IG17 G_M000_IG14: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG15 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x38] b G_M000_IG17 G_M000_IG15: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG16 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x38] b G_M000_IG17 G_M000_IG16: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x38] b G_M000_IG17 G_M000_IG17: ldr x0, [fp, #0x38] G_M000_IG18: ldp fp, lr, [sp], #0xD0 ret lr G_M000_IG19: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 1496 121: JIT compiled BenchmarkDotNet.Portability.RuntimeInformation:GetRuntimeVersion() [Tier0, IL size=371, code size=1496] ; Assembly listing for method BenchmarkDotNet.Portability.RuntimeInformation:get_IsWasm():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 36 122: JIT compiled BenchmarkDotNet.Portability.RuntimeInformation:get_IsWasm() [Tier0, IL size=6, code size=36] ; Assembly listing for method BenchmarkDotNet.Portability.RuntimeInformation:get_IsOldMono():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #231 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldrb w0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 52 123: JIT compiled BenchmarkDotNet.Portability.RuntimeInformation:get_IsOldMono() [Tier0, IL size=6, code size=52] ; Assembly listing for method BenchmarkDotNet.Portability.RuntimeInformation:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str wzr, [fp, #0x1C] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cmp x0, #0 cset x0, ne movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 strb w0, [x1] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cmp x0, #0 cset x0, ne movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 strb w0, [x1] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cmp w0, #0 cset x0, eq str w0, [fp, #0x1C] b G_M000_IG04 G_M000_IG03: str wzr, [fp, #0x1C] G_M000_IG04: ldr w0, [fp, #0x1C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 strb w0, [x1] G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 216 124: JIT compiled BenchmarkDotNet.Portability.RuntimeInformation:.cctor() [Tier0, IL size=66, code size=216] ; Assembly listing for method System.Buffers.ProbabilisticMap:IndexOfAny[System.SpanHelpers+DontNegate`1[ushort]](byref,int,byref,int):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp add x9, fp, #32 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] str x0, [fp, #0x78] str w1, [fp, #0x74] str x2, [fp, #0x68] str w3, [fp, #0x64] G_M000_IG02: stp xzr, xzr, [fp, #0x20] add x0, fp, #32 ldr x1, [fp, #0x68] ldr w2, [fp, #0x64] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp x0, x1, [fp, #0x20] stp x0, x1, [fp, #0x50] G_M000_IG04: mov w0, #0xD1FFAB1E str w0, [fp, #0x10] ldr w0, [fp, #0x74] ldr w1, [fp, #0x64] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG12 ldr x0, [fp, #0x78] ldr w1, [fp, #0x74] sxtw x1, w1 lsl x1, x1, #1 add x0, x0, x1 str x0, [fp, #0x40] ldr x0, [fp, #0x78] str x0, [fp, #0x38] b G_M000_IG08 G_M000_IG05: ldr x0, [fp, #0x38] ldrh w0, [x0] str w0, [fp, #0x34] ldr x0, [fp, #0x50] ldr x1, [fp, #0x58] ldr w2, [fp, #0x34] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG07 ldr x0, [fp, #0x38] ldr x2, [fp, #0x78] sub x0, x0, x2 lsr x0, x0, #1 G_M000_IG06: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG07: ldr x0, [fp, #0x38] add x0, x0, #2 str x0, [fp, #0x38] G_M000_IG08: ldr w0, [fp, #0x10] sub w0, w0, #1 str w0, [fp, #0x10] ldr w0, [fp, #0x10] cmp w0, #0 bgt G_M000_IG10 G_M000_IG09: add x0, fp, #16 mov w1, #74 bl CORINFO_HELP_PATCHPOINT G_M000_IG10: ldr x0, [fp, #0x38] ldr x1, [fp, #0x40] cmp x0, x1 bne G_M000_IG05 movn w0, #0 G_M000_IG11: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG12: b G_M000_IG13 G_M000_IG13: ldr x2, [fp, #0x50] ldr x3, [fp, #0x58] add x4, fp, #72 ldr x0, [fp, #0x78] ldr w1, [fp, #0x74] movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 str w0, [fp, #0x1C] ldr w0, [fp, #0x1C] cbz w0, G_M000_IG15 ldr w0, [fp, #0x48] G_M000_IG14: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG15: ldr x0, [fp, #0x78] ldr w1, [fp, #0x74] ldr x2, [fp, #0x68] ldr w3, [fp, #0x64] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG16: ldp fp, lr, [sp], #0x80 ret lr ; Total bytes of code 440 125: JIT compiled System.Buffers.ProbabilisticMap:IndexOfAny[System.SpanHelpers+DontNegate`1[ushort]](byref,int,byref,int) [Tier0, IL size=148, code size=440] ; Assembly listing for method System.Buffers.ProbabilisticMap:ShouldUseSimpleLoop(int,int):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str w0, [fp, #0x1C] str w1, [fp, #0x18] G_M000_IG02: ldr w0, [fp, #0x1C] cmp w0, #8 blt G_M000_IG06 ldr w0, [fp, #0x1C] cmp w0, #20 bge G_M000_IG04 ldr w0, [fp, #0x1C] ldr w1, [fp, #0x18] asr w1, w1, #1 cmp w0, w1 cset x0, lt G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: mov w0, wzr G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG06: mov w0, #1 G_M000_IG07: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 92 126: JIT compiled System.Buffers.ProbabilisticMap:ShouldUseSimpleLoop(int,int) [Tier0, IL size=24, code size=92] ; Assembly listing for method System.Buffers.IndexOfAnyAsciiSearcher:TryIndexOfAny(byref,int,System.ReadOnlySpan`1[ushort],byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str w1, [fp, #0x34] str x2, [fp, #0x20] str x3, [fp, #0x28] str x4, [fp, #0x18] G_M000_IG02: ldr x2, [fp, #0x20] ldr x3, [fp, #0x28] ldr x0, [fp, #0x38] ldr w1, [fp, #0x34] ldr x4, [fp, #0x18] movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 76 127: JIT compiled System.Buffers.IndexOfAnyAsciiSearcher:TryIndexOfAny(byref,int,System.ReadOnlySpan`1[ushort],byref) [Tier0, IL size=15, code size=76] ; Assembly listing for method System.Buffers.IndexOfAnyAsciiSearcher:TryIndexOfAny[System.Buffers.IndexOfAnyAsciiSearcher+DontNegate](byref,int,System.ReadOnlySpan`1[ushort],byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x78] str w1, [fp, #0x74] str x2, [fp, #0x60] str x3, [fp, #0x68] str x4, [fp, #0x58] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG07 movi v16.4s, #0 str q16, [fp, #0x40] ldr x0, [fp, #0x60] ldr x1, [fp, #0x68] add x2, fp, #64 add x3, fp, #56 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 cbz w0, G_M000_IG07 ldr x0, [fp, #0x58] str x0, [fp, #0x30] str wzr, [fp, #0x2C] b G_M000_IG03 G_M000_IG03: ldr x0, [fp, #0x30] str x0, [fp, #0x20] ldr w0, [fp, #0x2C] ldr w1, [fp, #0x38] uxtb w1, w1 and w0, w0, w1 cbnz w0, G_M000_IG04 ldr x0, [fp, #0x20] str x0, [fp, #0x18] ldr x0, [fp, #0x78] ldr w1, [fp, #0x74] ldr q0, [fp, #0x40] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x14] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] str x0, [fp, #0x18] ldr x0, [fp, #0x78] ldr w1, [fp, #0x74] ldr q0, [fp, #0x40] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x14] G_M000_IG05: ldr x0, [fp, #0x18] ldr w1, [fp, #0x14] str w1, [x0] mov w0, #1 G_M000_IG06: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG07: ldr x0, [fp, #0x58] str wzr, [x0] mov w0, wzr G_M000_IG08: ldp fp, lr, [sp], #0x80 ret lr ; Total bytes of code 292 128: JIT compiled System.Buffers.IndexOfAnyAsciiSearcher:TryIndexOfAny[System.Buffers.IndexOfAnyAsciiSearcher+DontNegate](byref,int,System.ReadOnlySpan`1[ushort],byref) [Tier0, IL size=68, code size=292] ; Assembly listing for method System.Buffers.IndexOfAnyAsciiSearcher:TryComputeBitmap(System.ReadOnlySpan`1[ushort],ulong,byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp str xzr, [fp, #0x38] str x0, [fp, #0x60] str x1, [fp, #0x68] str x2, [fp, #0x58] str x3, [fp, #0x50] G_M000_IG02: ldr x0, [fp, #0x58] str x0, [fp, #0x48] G_M000_IG03: ldp x0, x1, [fp, #0x60] stp x0, x1, [fp, #0x38] G_M000_IG04: str wzr, [fp, #0x34] mov w0, #0xD1FFAB1E str w0, [fp, #0x18] b G_M000_IG08 G_M000_IG05: ldr w0, [fp, #0x34] ldr w1, [fp, #0x40] cmp w0, w1 bhs G_M000_IG12 ldr x0, [fp, #0x38] ldr w1, [fp, #0x34] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #127 ble G_M000_IG07 ldr x0, [fp, #0x50] strb wzr, [x0] mov w0, wzr G_M000_IG06: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG07: ldr w0, [fp, #0x30] asr w0, w0, #4 str w0, [fp, #0x2C] ldr w0, [fp, #0x30] and w0, w0, #15 str w0, [fp, #0x28] ldr x0, [fp, #0x48] ldr w1, [fp, #0x28] mov w1, w1 add x0, x0, x1 str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldrb w0, [x0] ldr w1, [fp, #0x2C] mov w2, #1 lsl w1, w2, w1 uxtb w1, w1 orr w0, w0, w1 ldr x1, [fp, #0x20] strb w0, [x1] ldr w0, [fp, #0x34] add w0, w0, #1 str w0, [fp, #0x34] G_M000_IG08: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG10 G_M000_IG09: add x0, fp, #24 mov w1, #61 bl CORINFO_HELP_PATCHPOINT G_M000_IG10: ldr w0, [fp, #0x34] ldr w1, [fp, #0x40] cmp w0, w1 blt G_M000_IG05 ldr x0, [fp, #0x58] ldrb w0, [x0] and w0, w0, #1 cmp w0, #0 cset x0, ne ldr x1, [fp, #0x50] strb w0, [x1] mov w0, #1 G_M000_IG11: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG12: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 324 129: JIT compiled System.Buffers.IndexOfAnyAsciiSearcher:TryComputeBitmap(System.ReadOnlySpan`1[ushort],ulong,byref) [Tier0, IL size=82, code size=324] ; Assembly listing for method System.Buffers.IndexOfAnyAsciiSearcher:IndexOfAnyLookup[System.Buffers.IndexOfAnyAsciiSearcher+DontNegate,System.Buffers.IndexOfAnyAsciiSearcher+Default](System.Runtime.Intrinsics.Vector128`1[short],System.Runtime.Intrinsics.Vector128`1[short],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xC0]! mov fp, sp str q0, [fp, #0xB0] str q1, [fp, #0xA0] str q2, [fp, #0x90] G_M000_IG02: b G_M000_IG03 G_M000_IG03: ldr q0, [fp, #0xB0] uqxtn v0.8b, v0.8h ldr q1, [fp, #0xA0] uqxtn2 v0.16b, v1.8h str q0, [fp, #0x30] b G_M000_IG04 G_M000_IG04: ldr q0, [fp, #0x30] str q0, [fp, #0x80] ldr q0, [fp, #0x80] ldr q1, [fp, #0x90] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str q0, [fp, #0x70] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG06 ldr q0, [fp, #0xB0] ldr q1, [@RWD00] cmhi v0.8h, v1.8h, v0.8h str q0, [fp, #0x60] ldr q0, [fp, #0xA0] ldr q1, [@RWD00] cmhi v0.8h, v1.8h, v0.8h str q0, [fp, #0x50] ldr q0, [fp, #0x60] ldr q1, [fp, #0x50] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str q0, [fp, #0x20] ldr q0, [fp, #0x20] str q0, [fp, #0x10] b G_M000_IG05 G_M000_IG05: ldr q0, [fp, #0x10] str q0, [fp, #0x40] ldr q0, [fp, #0x70] ldr q16, [fp, #0x40] and v0.16b, v0.16b, v16.16b str q0, [fp, #0x70] G_M000_IG06: ldr q0, [fp, #0x70] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG07: ldp fp, lr, [sp], #0xC0 ret lr RWD00 dq 0080008000800080h, 0080008000800080h ; Total bytes of code 244 130: JIT compiled System.Buffers.IndexOfAnyAsciiSearcher:IndexOfAnyLookup[System.Buffers.IndexOfAnyAsciiSearcher+DontNegate,System.Buffers.IndexOfAnyAsciiSearcher+Default](System.Runtime.Intrinsics.Vector128`1[short],System.Runtime.Intrinsics.Vector128`1[short],System.Runtime.Intrinsics.Vector128`1[ubyte]) [Tier0, IL size=158, code size=244] ; Assembly listing for method System.Buffers.IndexOfAnyAsciiSearcher:IndexOfAnyLookupCore(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! mov fp, sp str q0, [fp, #0x90] str q1, [fp, #0x80] G_M000_IG02: ldr q0, [fp, #0x90] ldr q1, [@RWD00] and v0.16b, v0.16b, v1.16b str q0, [fp, #0x20] b G_M000_IG03 G_M000_IG03: ldr q0, [fp, #0x20] str q0, [fp, #0x70] b G_M000_IG04 G_M000_IG04: ldr q0, [fp, #0x90] sshr v0.16b, v0.16b, #4 str q0, [fp, #0x10] ldr q0, [fp, #0x10] str q0, [fp, #0x60] ldr q0, [fp, #0x80] ldr q1, [fp, #0x70] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str q0, [fp, #0x50] ldr q0, [@RWD16] ldr q1, [fp, #0x60] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str q0, [fp, #0x40] ldr q0, [fp, #0x50] ldr q16, [fp, #0x40] and v0.16b, v0.16b, v16.16b str q0, [fp, #0x30] ldr q0, [fp, #0x30] G_M000_IG05: ldp fp, lr, [sp], #0xA0 ret lr RWD00 dq 0F0F0F0F0F0F0F0Fh, 0F0F0F0F0F0F0F0Fh RWD16 dq 8040201008040201h, 0000000000000000h ; Total bytes of code 160 131: JIT compiled System.Buffers.IndexOfAnyAsciiSearcher:IndexOfAnyLookupCore(System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]) [Tier0, IL size=122, code size=160] ; Assembly listing for method System.Buffers.IndexOfAnyAsciiSearcher+Default:get_NeedleContainsZero():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 132: JIT compiled System.Buffers.IndexOfAnyAsciiSearcher+Default:get_NeedleContainsZero() [Tier0, IL size=2, code size=20] ; Assembly listing for method System.Buffers.IndexOfAnyAsciiSearcher+DontNegate:NegateIfNeeded(System.Runtime.Intrinsics.Vector128`1[ubyte]):System.Runtime.Intrinsics.Vector128`1[ubyte] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str q0, [fp, #0x10] G_M000_IG02: ldr q0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 24 133: JIT compiled System.Buffers.IndexOfAnyAsciiSearcher+DontNegate:NegateIfNeeded(System.Runtime.Intrinsics.Vector128`1[ubyte]) [Tier0, IL size=2, code size=24] ; Assembly listing for method BenchmarkDotNet.Portability.RuntimeInformation:get_IsMono():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #231 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldrb w0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 52 134: JIT compiled BenchmarkDotNet.Portability.RuntimeInformation:get_IsMono() [Tier0, IL size=6, code size=52] ; Assembly listing for method BenchmarkDotNet.Portability.RuntimeInformation:get_IsNewMono():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldrb w0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 32 135: JIT compiled BenchmarkDotNet.Portability.RuntimeInformation:get_IsNewMono() [Tier0, IL size=6, code size=32] ; Assembly listing for method BenchmarkDotNet.Portability.RuntimeInformation:get_IsFullFramework():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 136: JIT compiled BenchmarkDotNet.Portability.RuntimeInformation:get_IsFullFramework() [Tier0, IL size=2, code size=20] ; Assembly listing for method BenchmarkDotNet.Portability.RuntimeInformation:get_IsNetCore():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cmp w0, #5 bge G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 mov w2, #5 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 cbz w0, G_M000_IG05 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x20] ldr x1, [x1] ldr x1, [x1, #0x50] ldr x1, [x1, #0x28] blr x1 str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x1, [x1] ldr x1, [x1, #0x48] ldr x1, [x1, #0x30] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cmp w0, #0 cset x0, eq G_M000_IG04: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG05: mov w0, wzr G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 260 137: JIT compiled BenchmarkDotNet.Portability.RuntimeInformation:get_IsNetCore() [Tier0, IL size=62, code size=260] ; Assembly listing for method System.SpanHelpers:NonPackedIndexOfAnyValueType[short,System.SpanHelpers+DontNegate`1[short]](byref,short,short,short,int):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 24 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: cmp w4, #8 bge G_M000_IG22 G_M000_IG03: mov x5, xzr cmp w4, #4 blt G_M000_IG13 sxth w6, w1 align [0 bytes for IG04] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG04: sub w4, w4, #4 lsl x7, x5, #1 add x7, x0, x7 ldrsh w8, [x7] cmp w8, w6 beq G_M000_IG21 G_M000_IG05: sxth w9, w2 cmp w8, w9 beq G_M000_IG21 sxth w10, w3 cmp w8, w10 cset x8, eq tst w8, #255 bne G_M000_IG21 G_M000_IG06: ldrsh w8, [x7, #0x02] cmp w8, w6 ccmp w8, w9, z, ne beq G_M000_IG20 G_M000_IG07: cmp w8, w10 cset x8, eq tst w8, #255 bne G_M000_IG20 G_M000_IG08: ldrsh w8, [x7, #0x04] cmp w8, w6 ccmp w8, w9, z, ne beq G_M000_IG19 G_M000_IG09: cmp w8, w10 cset x8, eq tst w8, #255 bne G_M000_IG19 G_M000_IG10: ldrsh w8, [x7, #0x06] cmp w8, w6 ccmp w8, w9, z, ne beq G_M000_IG18 G_M000_IG11: cmp w8, w10 cset x8, eq tst w8, #255 bne G_M000_IG18 G_M000_IG12: add x5, x5, #4 cmp w4, #4 bge G_M000_IG04 G_M000_IG13: cmp w4, #0 ble G_M000_IG28 sxth w6, w1 align [0 bytes for IG14] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG14: sub w4, w4, #1 lsl x9, x5, #1 ldrsh w8, [x0, x9] cmp w8, w6 beq G_M000_IG21 G_M000_IG15: sxth w9, w2 cmp w8, w9 beq G_M000_IG21 sxth w10, w3 cmp w8, w10 cset x1, eq tst w1, #255 bne G_M000_IG21 G_M000_IG16: add x5, x5, #1 cmp w4, #0 bgt G_M000_IG14 G_M000_IG17: b G_M000_IG28 G_M000_IG18: add w5, w5, #3 b G_M000_IG26 G_M000_IG19: add w5, w5, #2 b G_M000_IG26 G_M000_IG20: add w5, w5, #1 b G_M000_IG26 G_M000_IG21: b G_M000_IG26 G_M000_IG22: sxth w6, w1 dup v16.8h, w6 sxth w9, w2 dup v17.8h, w9 sxth w10, w3 dup v18.8h, w10 mov x1, x0 sub w5, w4, #8 sbfiz x2, x5, #1, #32 add x3, x1, x2 align [4 bytes for IG23] align [4 bytes] align [0 bytes] align [0 bytes] G_M000_IG23: ldr q19, [x1] cmeq v20.8h, v16.8h, v19.8h cmeq v21.8h, v17.8h, v19.8h orr v20.8h, v20.8h, v21.8h cmeq v19.8h, v18.8h, v19.8h orr v19.8h, v20.8h, v19.8h umaxp v20.4s, v19.4s, v19.4s umov x5, v20.d[0] cmp x5, #0 bne G_M000_IG25 add x1, x1, #16 cmp x1, x3 bls G_M000_IG23 G_M000_IG24: mov w0, w4 tst w0, #7 beq G_M000_IG28 ldr q19, [x3] cmeq v16.8h, v16.8h, v19.8h cmeq v17.8h, v17.8h, v19.8h orr v16.8h, v16.8h, v17.8h cmeq v17.8h, v18.8h, v19.8h orr v19.8h, v16.8h, v17.8h umaxp v16.4s, v19.4s, v19.4s umov x1, v16.d[0] cmp x1, #0 beq G_M000_IG28 lsr x0, x2, #1 ldr q16, [@RWD00] and v19.8h, v19.8h, v16.8h ldr q16, [@RWD16] ushl v16.8h, v19.8h, v16.8h addv h16, v16.8h umov w1, v16.h[0] rbit w1, w1 clz w1, w1 add w5, w0, w1 b G_M000_IG26 G_M000_IG25: sub x5, x1, x0 lsr x0, x5, #1 ldr q16, [@RWD00] and v16.8h, v19.8h, v16.8h ldr q17, [@RWD16] ushl v16.8h, v16.8h, v17.8h addv h16, v16.8h umov w1, v16.h[0] rbit w1, w1 clz w1, w1 add w5, w0, w1 G_M000_IG26: mov w0, w5 G_M000_IG27: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG28: movn w0, #0 G_M000_IG29: ldp fp, lr, [sp], #0x10 ret lr RWD00 dq 8000800080008000h, 8000800080008000h RWD16 dq FFF4FFF3FFF2FFF1h, FFF8FFF7FFF6FFF5h ; Total bytes of code 568 138: JIT compiled System.SpanHelpers:NonPackedIndexOfAnyValueType[short,System.SpanHelpers+DontNegate`1[short]](byref,short,short,short,int) [Tier1, IL size=1399, code size=568] ; Assembly listing for method BenchmarkDotNet.Portability.RuntimeInformation:GetNetCoreVersion():System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xB0]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] stp xzr, xzr, [x9, #0x80] str xzr, [x9, #0x90] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x48] ldr x0, [fp, #0x48] ldr x1, [fp, #0x48] ldr x1, [x1] ldr x1, [x1, #0x50] ldr x1, [x1, #0x28] blr x1 str x0, [fp, #0x40] ldr x0, [fp, #0x40] ldr x1, [fp, #0x40] ldr x1, [x1] ldr x1, [x1, #0x48] ldr x1, [x1, #0x30] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xA8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x38] ldr x0, [fp, #0x38] ldr x1, [fp, #0x38] ldr x1, [x1] ldr x1, [x1, #0x50] ldr x1, [x1, #0x28] blr x1 str x0, [fp, #0x30] ldr x0, [fp, #0x30] ldr x1, [fp, #0x30] ldr x1, [x1] ldr x1, [x1, #0x48] ldr x1, [x1, #0x30] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xA0] add x0, fp, #152 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x58] ldr x0, [fp, #0x98] str x0, [fp, #0x50] ldr x0, [fp, #0x58] mov w1, #5 mov w2, wzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x50] ldr x1, [fp, #0x58] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG04 add x0, fp, #112 mov w1, #8 mov w2, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x0, fp, #112 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #112 ldr x2, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x0, fp, #112 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x28] ldr x1, [fp, #0x28] add x0, fp, #112 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #112 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #112 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0xB0 ret lr G_M000_IG04: ldr x0, [fp, #0x98] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x60] b G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x98] ldr x1, [fp, #0x98] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x08] blr x1 str x0, [fp, #0x60] G_M000_IG06: ldr x0, [fp, #0x60] str x0, [fp, #0x68] add x0, fp, #112 mov w1, #30 mov w2, #3 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x0, fp, #112 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #112 ldr x1, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #112 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x1, [fp, #0x20] add x0, fp, #112 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #112 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xA0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] add x0, fp, #112 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #112 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #112 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG07: ldp fp, lr, [sp], #0xB0 ret lr ; Total bytes of code 1100 139: JIT compiled BenchmarkDotNet.Portability.RuntimeInformation:GetNetCoreVersion() [Tier0, IL size=285, code size=1100] ; Assembly listing for method System.Diagnostics.FileVersionInfo:GetVersionInfo(System.String):System.Diagnostics.FileVersionInfo ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG03 ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x28] G_M000_IG03: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG05 G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x18] bl CORINFO_HELP_THROW G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x20] G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 220 140: JIT compiled System.Diagnostics.FileVersionInfo:GetVersionInfo(System.String) [Tier0, IL size=38, code size=220] ; Assembly listing for method System.SpanHelpers:NonPackedContainsValueType[short](byref,short,int):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 13 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: cmp w2, #8 bge G_M000_IG07 G_M000_IG03: mov x3, xzr cmp w2, #4 blt G_M000_IG04 sub w2, w2, #4 lsl x4, x3, #1 ldrsh w5, [x0, x4] sxth w6, w1 cmp w5, w6 beq G_M000_IG10 add x5, x4, #2 ldrsh w5, [x0, x5] cmp w5, w6 beq G_M000_IG10 add x5, x4, #4 ldrsh w5, [x0, x5] cmp w5, w6 beq G_M000_IG10 add x4, x4, #6 ldrsh w4, [x0, x4] cmp w4, w6 beq G_M000_IG10 add x3, x3, #4 G_M000_IG04: cmp w2, #0 ble G_M000_IG12 sxth w6, w1 align [4 bytes for IG05] align [4 bytes] align [4 bytes] align [0 bytes] G_M000_IG05: sub w2, w2, #1 lsl x1, x3, #1 ldrsh w1, [x0, x1] cmp w1, w6 beq G_M000_IG10 add x3, x3, #1 cmp w2, #0 bgt G_M000_IG05 G_M000_IG06: b G_M000_IG12 G_M000_IG07: sxth w6, w1 dup v16.8h, w6 sub w1, w2, #8 ubfiz x1, x1, #1, #32 add x1, x0, x1 align [0 bytes for IG08] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG08: ldr q17, [x0] cmeq v17.8h, v16.8h, v17.8h umaxp v17.4s, v17.4s, v17.4s umov x3, v17.d[0] cmp x3, #0 bne G_M000_IG10 add x0, x0, #16 cmp x0, x1 bls G_M000_IG08 G_M000_IG09: mov w0, w2 tst w0, #7 beq G_M000_IG12 ldr q17, [x1] cmeq v16.8h, v16.8h, v17.8h umaxp v16.4s, v16.4s, v16.4s umov x0, v16.d[0] cmp x0, #0 beq G_M000_IG12 G_M000_IG10: mov w0, #1 G_M000_IG11: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG12: mov w0, wzr G_M000_IG13: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 280 141: JIT compiled System.SpanHelpers:NonPackedContainsValueType[short](byref,short,int) [Tier1, IL size=601, code size=280] ; Assembly listing for method System.Diagnostics.FileVersionInfo:.ctor(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str xzr, [fp, #0x18] add x2, sp, #96 str x2, [fp, #0x58] str x0, [fp, #0x50] str x1, [fp, #0x48] G_M000_IG02: ldr x0, [fp, #0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x50] add x14, x14, #8 ldr x15, [fp, #0x48] bl CORINFO_HELP_ASSIGN_REF ldr x1, [fp, #0x50] ldr x1, [x1, #0x08] add x2, fp, #56 mov w0, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str w0, [fp, #0x44] ldr w0, [fp, #0x44] cbz w0, G_M000_IG11 ldr w0, [fp, #0x44] mov w0, w0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x30] G_M000_IG03: ldr x1, [fp, #0x50] ldr x1, [x1, #0x08] ldr w3, [fp, #0x44] ldr x4, [fp, #0x30] mov w0, #3 mov w2, wzr movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 cbz w0, G_M000_IG08 ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x28] add x0, fp, #40 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x2, [fp, #0x18] ldr x1, [fp, #0x30] ldr x0, [fp, #0x50] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 cbnz w0, G_M000_IG07 ldr w0, [fp, #0x28] movz w1, #0xD1FFAB1E movk w1, #0xD1FFAB1E LSL #16 cmp w0, w1 beq G_M000_IG04 ldr x0, [fp, #0x50] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 cbnz w0, G_M000_IG07 G_M000_IG04: ldr w0, [fp, #0x28] movz w1, #0xD1FFAB1E movk w1, #0xD1FFAB1E LSL #16 cmp w0, w1 beq G_M000_IG05 ldr x0, [fp, #0x50] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 cbnz w0, G_M000_IG07 G_M000_IG05: ldr w0, [fp, #0x28] mov w1, #0xD1FFAB1E cmp w0, w1 beq G_M000_IG06 ldr x0, [fp, #0x50] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str w0, [fp, #0x24] b G_M000_IG08 G_M000_IG06: str wzr, [fp, #0x24] b G_M000_IG08 G_M000_IG07: mov w0, #1 str w0, [fp, #0x24] G_M000_IG08: b G_M000_IG09 G_M000_IG09: ldr x0, [fp, #0x58] bl G_M000_IG12 G_M000_IG10: nop G_M000_IG11: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG12: stp fp, lr, [sp, #-0x20]! add x3, fp, #96 str x3, [sp, #0x18] G_M000_IG13: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG14: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 576 142: JIT compiled System.Diagnostics.FileVersionInfo:.ctor(System.String) [Tier0, IL size=168, code size=576] ; Assembly listing for method Interop+Version:GetFileVersionInfoSizeEx(uint,System.String,byref):uint ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! stp x19, x20, [sp, #0xC0] stp x21, x22, [sp, #0xD0] stp x23, x24, [sp, #0xE0] stp x25, x26, [sp, #0xF0] stp x27, x28, [sp, #0xD1FFAB1E] mov fp, sp str xzr, [fp, #0x90] str xzr, [fp, #0x80] str w0, [fp, #0xBC] str x1, [fp, #0xB0] str x2, [fp, #0xA8] G_M000_IG02: add x0, fp, #32 mov x1, x12 bl CORINFO_HELP_INIT_PINVOKE_FRAME str x0, [fp, #0x70] mov x0, sp str x0, [fp, #0x40] mov x0, fp str x0, [fp, #0x50] ldr x0, [fp, #0xA8] str x0, [fp, #0x90] ldr x0, [fp, #0x90] str x0, [fp, #0x68] ldr x0, [fp, #0x68] str x0, [fp, #0x98] ldr x0, [fp, #0xB0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x80] ldr x0, [fp, #0x80] str x0, [fp, #0x60] ldr x0, [fp, #0x60] str x0, [fp, #0x88] ldr w0, [fp, #0xBC] ldr x1, [fp, #0x88] ldr x2, [fp, #0x98] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 str x3, [fp, #0x30] adr x3, [G_M000_IG05] str x3, [fp, #0x48] ldr x3, [fp, #0x70] add x4, fp, #32 str x4, [x3, #0x10] ldr x3, [fp, #0x70] strb wzr, [x3, #0x0C] G_M000_IG03: movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG04: blr x3 G_M000_IG05: mov w19, w0 ldr x0, [fp, #0x70] mov w1, #1 strb w1, [x0, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG06 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG06: ldr x0, [fp, #0x70] ldr x1, [fp, #0x28] str x1, [x0, #0x10] str w19, [fp, #0xA4] str xzr, [fp, #0x80] str xzr, [fp, #0x90] ldr w0, [fp, #0xA4] str w0, [fp, #0x7C] b G_M000_IG07 G_M000_IG07: ldr w0, [fp, #0x7C] G_M000_IG08: ldp x27, x28, [sp, #0xD1FFAB1E] ldp x25, x26, [sp, #0xF0] ldp x23, x24, [sp, #0xE0] ldp x21, x22, [sp, #0xD0] ldp x19, x20, [sp, #0xC0] ldp fp, lr, [sp], #0xD1FFAB1E ret lr ; Total bytes of code 336 143: JIT compiled Interop+Version:GetFileVersionInfoSizeEx(uint,System.String,byref) [Tier0, IL size=41, code size=336] ; Assembly listing for method Interop+Version:GetFileVersionInfoEx(uint,System.String,uint,uint,ulong):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x100]! stp x19, x20, [sp, #0xB0] stp x21, x22, [sp, #0xC0] stp x23, x24, [sp, #0xD0] stp x25, x26, [sp, #0xE0] stp x27, x28, [sp, #0xF0] mov fp, sp str xzr, [fp, #0x78] str w0, [fp, #0xAC] str x1, [fp, #0xA0] str w2, [fp, #0x9C] str w3, [fp, #0x98] str x4, [fp, #0x90] G_M000_IG02: add x0, fp, #32 mov x1, x12 bl CORINFO_HELP_INIT_PINVOKE_FRAME str x0, [fp, #0x68] mov x0, sp str x0, [fp, #0x40] mov x0, fp str x0, [fp, #0x50] ldr x0, [fp, #0xA0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x78] ldr x0, [fp, #0x78] str x0, [fp, #0x60] ldr x0, [fp, #0x60] str x0, [fp, #0x80] ldr w0, [fp, #0xAC] ldr x1, [fp, #0x80] ldr w2, [fp, #0x9C] ldr w3, [fp, #0x98] ldr x4, [fp, #0x90] movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 str x5, [fp, #0x30] adr x5, [G_M000_IG05] str x5, [fp, #0x48] ldr x5, [fp, #0x68] add x6, fp, #32 str x6, [x5, #0x10] ldr x5, [fp, #0x68] strb wzr, [x5, #0x0C] G_M000_IG03: movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] G_M000_IG04: blr x5 G_M000_IG05: mov w19, w0 ldr x0, [fp, #0x68] mov w1, #1 strb w1, [x0, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG06 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG06: ldr x0, [fp, #0x68] ldr x1, [fp, #0x28] str x1, [x0, #0x10] str w19, [fp, #0x88] str xzr, [fp, #0x78] ldr w0, [fp, #0x88] cmp w0, #0 cset x0, ne str w0, [fp, #0x8C] ldr w0, [fp, #0x8C] str w0, [fp, #0x74] b G_M000_IG07 G_M000_IG07: ldr w0, [fp, #0x74] uxtb w0, w0 G_M000_IG08: ldp x27, x28, [sp, #0xF0] ldp x25, x26, [sp, #0xE0] ldp x23, x24, [sp, #0xD0] ldp x21, x22, [sp, #0xC0] ldp x19, x20, [sp, #0xB0] ldp fp, lr, [sp], #0xD1FFAB1E ret lr ; Total bytes of code 340 144: JIT compiled Interop+Version:GetFileVersionInfoEx(uint,System.String,uint,uint,ulong) [Tier0, IL size=32, code size=340] ; Assembly listing for method System.Diagnostics.FileVersionInfo:GetLanguageAndCodePage(ulong):uint ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] G_M000_IG02: add x2, fp, #32 add x3, fp, #24 ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 cbz w0, G_M000_IG04 ldr x0, [fp, #0x20] ldrh w0, [x0] lsl w0, w0, #16 ldr x1, [fp, #0x20] mov w2, #2 sxtw x2, w2 ldrh w1, [x1, x2] add w0, w0, w1 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: movz w0, #0xD1FFAB1E movk w0, #0xD1FFAB1E LSL #16 G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 116 145: JIT compiled System.Diagnostics.FileVersionInfo:GetLanguageAndCodePage(ulong) [Tier0, IL size=34, code size=116] ; Assembly listing for method Interop+Version:VerQueryValue(ulong,System.String,byref,byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! stp x19, x20, [sp, #0xE0] stp x21, x22, [sp, #0xF0] stp x23, x24, [sp, #0xD1FFAB1E] stp x25, x26, [sp, #0xD1FFAB1E] stp x27, x28, [sp, #0xD1FFAB1E] mov fp, sp str xzr, [fp, #0xA8] str xzr, [fp, #0x98] str xzr, [fp, #0x88] str x0, [fp, #0xD8] str x1, [fp, #0xD0] str x2, [fp, #0xC8] str x3, [fp, #0xC0] G_M000_IG02: add x0, fp, #32 mov x1, x12 bl CORINFO_HELP_INIT_PINVOKE_FRAME str x0, [fp, #0x78] mov x0, sp str x0, [fp, #0x40] mov x0, fp str x0, [fp, #0x50] ldr x0, [fp, #0xC8] str xzr, [x0] ldr x0, [fp, #0xC0] str x0, [fp, #0xA8] ldr x0, [fp, #0xA8] str x0, [fp, #0x70] ldr x0, [fp, #0x70] str x0, [fp, #0xB0] ldr x0, [fp, #0xC8] str x0, [fp, #0x98] ldr x0, [fp, #0x98] str x0, [fp, #0x68] ldr x0, [fp, #0x68] str x0, [fp, #0xA0] ldr x0, [fp, #0xD0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x88] ldr x0, [fp, #0x88] str x0, [fp, #0x60] ldr x0, [fp, #0x60] str x0, [fp, #0x90] ldr x0, [fp, #0xD8] ldr x1, [fp, #0x90] ldr x2, [fp, #0xA0] ldr x3, [fp, #0xB0] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 str x4, [fp, #0x30] adr x4, [G_M000_IG05] str x4, [fp, #0x48] ldr x4, [fp, #0x78] add x5, fp, #32 str x5, [x4, #0x10] ldr x4, [fp, #0x78] strb wzr, [x4, #0x0C] G_M000_IG03: movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] G_M000_IG04: blr x4 G_M000_IG05: mov w19, w0 ldr x0, [fp, #0x78] mov w1, #1 strb w1, [x0, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG06 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG06: ldr x0, [fp, #0x78] ldr x1, [fp, #0x28] str x1, [x0, #0x10] str w19, [fp, #0xB8] str xzr, [fp, #0x88] str xzr, [fp, #0x98] str xzr, [fp, #0xA8] ldr w0, [fp, #0xB8] cmp w0, #0 cset x0, ne str w0, [fp, #0xBC] ldr w0, [fp, #0xBC] str w0, [fp, #0x84] b G_M000_IG07 G_M000_IG07: ldr w0, [fp, #0x84] uxtb w0, w0 G_M000_IG08: ldp x27, x28, [sp, #0xD1FFAB1E] ldp x25, x26, [sp, #0xD1FFAB1E] ldp x23, x24, [sp, #0xD1FFAB1E] ldp x21, x22, [sp, #0xF0] ldp x19, x20, [sp, #0xE0] ldp fp, lr, [sp], #0xD1FFAB1E ret lr ; Total bytes of code 404 146: JIT compiled Interop+Version:VerQueryValue(ulong,System.String,byref,byref) [Tier0, IL size=69, code size=404] ; Assembly listing for method System.Number:Int32ToHexChars[ushort](ulong,uint,int,int):ulong ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str x0, [fp, #0x58] str w1, [fp, #0x54] str w2, [fp, #0x50] str w3, [fp, #0x4C] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x10] b G_M000_IG08 G_M000_IG03: ldr w0, [fp, #0x10] sub w0, w0, #1 str w0, [fp, #0x10] ldr w0, [fp, #0x10] cmp w0, #0 bgt G_M000_IG05 G_M000_IG04: add x0, fp, #16 mov w1, #2 bl CORINFO_HELP_PATCHPOINT G_M000_IG05: ldr w0, [fp, #0x54] and w0, w0, #15 str w0, [fp, #0x48] ldr x0, [fp, #0x58] mov w1, #2 sxtw x1, w1 sub x0, x0, x1 str x0, [fp, #0x38] ldr x0, [fp, #0x38] str x0, [fp, #0x58] ldr x0, [fp, #0x38] str x0, [fp, #0x30] ldr w0, [fp, #0x48] str w0, [fp, #0x2C] ldr w0, [fp, #0x48] cmp w0, #10 blt G_M000_IG06 ldr x0, [fp, #0x30] str x0, [fp, #0x20] ldr w0, [fp, #0x2C] str w0, [fp, #0x1C] ldr w0, [fp, #0x50] str w0, [fp, #0x18] b G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x30] str x0, [fp, #0x20] ldr w0, [fp, #0x2C] str w0, [fp, #0x1C] mov w0, #48 str w0, [fp, #0x18] G_M000_IG07: ldr w0, [fp, #0x1C] ldr w1, [fp, #0x18] add w0, w0, w1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x20] strh w0, [x1] ldr w0, [fp, #0x54] lsr w0, w0, #4 str w0, [fp, #0x54] G_M000_IG08: ldr w0, [fp, #0x4C] sub w0, w0, #1 str w0, [fp, #0x44] ldr w0, [fp, #0x4C] sub w0, w0, #1 str w0, [fp, #0x4C] ldr w0, [fp, #0x44] tbz w0, #31, G_M000_IG03 ldr w0, [fp, #0x54] cbnz w0, G_M000_IG03 ldr x0, [fp, #0x58] G_M000_IG09: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 296 147: JIT compiled System.Number:Int32ToHexChars[ushort](ulong,uint,int,int) [Tier0, IL size=66, code size=296] ; Assembly listing for method System.Diagnostics.FileVersionInfo:GetVersionInfoForCodePage(ulong,System.String):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: sub sp, sp, #0xD1FFAB1E stp fp, lr, [sp, #0xD1FFAB1E] add fp, sp, #0xD1FFAB1E movi v16.16b, #0 sub x9, fp, #0xD1FFAB1E mov x10, #184 stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40]! subs x10, x10, #64 bge pc-16 (-4 instructions) stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str xzr, [x9, #0x50] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 movn xip1, #0xD1FFAB1E str x3, [fp, xip1] str x0, [fp, #-0x08] str x1, [fp, #-0x10] str x2, [fp, #-0x18] G_M000_IG02: stp xzr, xzr, [fp, #-0xB0] sub x0, fp, #176 ldp x1, xzr, [sp], #0xD1FFAB1E mov x1, sp mov w2, #0xD1FFAB1E movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp x0, x4, [fp, #-0xB0] stp x0, x4, [fp, #-0x70] G_M000_IG04: ldp x0, x4, [fp, #-0x70] stp x0, x4, [fp, #-0x28] G_M000_IG05: str xzr, [fp, #-0x78] G_M000_IG06: ldp x0, x4, [fp, #-0x28] stp x0, x4, [fp, #-0x70] G_M000_IG07: ldr x4, [fp, #-0x70] ldr x5, [fp, #-0x68] sub x0, fp, #160 ldr x3, [fp, #-0x78] mov w1, #31 mov w2, #1 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 ldr x1, [fp, #-0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x1, [fp, #-0x70] ldr x2, [fp, #-0x68] sub x3, fp, #160 ldr x0, [fp, #-0x78] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 str x0, [fp, #-0xB8] ldr x1, [fp, #-0xB8] ldr x0, [fp, #-0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #-0x08] add x14, x14, #16 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF str xzr, [fp, #-0x78] G_M000_IG08: ldp x0, x4, [fp, #-0x28] stp x0, x4, [fp, #-0x70] G_M000_IG09: ldr x4, [fp, #-0x70] ldr x5, [fp, #-0x68] sub x0, fp, #160 ldr x3, [fp, #-0x78] mov w1, #35 mov w2, #1 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 ldr x1, [fp, #-0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x1, [fp, #-0x70] ldr x2, [fp, #-0x68] sub x3, fp, #160 ldr x0, [fp, #-0x78] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 str x0, [fp, #-0xC0] ldr x1, [fp, #-0xC0] ldr x0, [fp, #-0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #-0x08] add x14, x14, #24 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF str xzr, [fp, #-0x78] G_M000_IG10: ldp x0, x4, [fp, #-0x28] stp x0, x4, [fp, #-0x70] G_M000_IG11: ldr x4, [fp, #-0x70] ldr x5, [fp, #-0x68] sub x0, fp, #160 ldr x3, [fp, #-0x78] mov w1, #31 mov w2, #1 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 ldr x1, [fp, #-0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x1, [fp, #-0x70] ldr x2, [fp, #-0x68] sub x3, fp, #160 ldr x0, [fp, #-0x78] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 str x0, [fp, #-0xC8] ldr x1, [fp, #-0xC8] ldr x0, [fp, #-0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #-0x08] add x14, x14, #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF str xzr, [fp, #-0x78] G_M000_IG12: ldp x0, x4, [fp, #-0x28] stp x0, x4, [fp, #-0x70] G_M000_IG13: ldr x4, [fp, #-0x70] ldr x5, [fp, #-0x68] sub x0, fp, #160 ldr x3, [fp, #-0x78] mov w1, #32 mov w2, #1 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 ldr x1, [fp, #-0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x1, [fp, #-0x70] ldr x2, [fp, #-0x68] sub x3, fp, #160 ldr x0, [fp, #-0x78] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 str x0, [fp, #-0xD0] ldr x1, [fp, #-0xD0] ldr x0, [fp, #-0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #-0x08] add x14, x14, #40 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF str xzr, [fp, #-0x78] G_M000_IG14: ldp x0, x4, [fp, #-0x28] stp x0, x4, [fp, #-0x70] G_M000_IG15: ldr x4, [fp, #-0x70] ldr x5, [fp, #-0x68] sub x0, fp, #160 ldr x3, [fp, #-0x78] mov w1, #34 mov w2, #1 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 ldr x1, [fp, #-0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x1, [fp, #-0x70] ldr x2, [fp, #-0x68] sub x3, fp, #160 ldr x0, [fp, #-0x78] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 str x0, [fp, #-0xD8] ldr x1, [fp, #-0xD8] ldr x0, [fp, #-0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #-0x08] add x14, x14, #48 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF str xzr, [fp, #-0x78] G_M000_IG16: ldp x0, x4, [fp, #-0x28] stp x0, x4, [fp, #-0x70] G_M000_IG17: ldr x4, [fp, #-0x70] ldr x5, [fp, #-0x68] sub x0, fp, #160 ldr x3, [fp, #-0x78] mov w1, #36 mov w2, #1 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 ldr x1, [fp, #-0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x1, [fp, #-0x70] ldr x2, [fp, #-0x68] sub x3, fp, #160 ldr x0, [fp, #-0x78] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 str x0, [fp, #-0xE0] ldr x1, [fp, #-0xE0] ldr x0, [fp, #-0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #-0x08] add x14, x14, #56 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF str xzr, [fp, #-0x78] G_M000_IG18: ldp x0, x4, [fp, #-0x28] stp x0, x4, [fp, #-0x70] G_M000_IG19: ldr x4, [fp, #-0x70] ldr x5, [fp, #-0x68] sub x0, fp, #160 ldr x3, [fp, #-0x78] mov w1, #31 mov w2, #1 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 ldr x1, [fp, #-0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x1, [fp, #-0x70] ldr x2, [fp, #-0x68] sub x3, fp, #160 ldr x0, [fp, #-0x78] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 str x0, [fp, #-0xE8] ldr x1, [fp, #-0xE8] ldr x0, [fp, #-0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #-0x08] add x14, x14, #64 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF str xzr, [fp, #-0x78] G_M000_IG20: ldp x0, x4, [fp, #-0x28] stp x0, x4, [fp, #-0x70] G_M000_IG21: ldr x4, [fp, #-0x70] ldr x5, [fp, #-0x68] sub x0, fp, #160 ldr x3, [fp, #-0x78] mov w1, #34 mov w2, #1 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 ldr x1, [fp, #-0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x1, [fp, #-0x70] ldr x2, [fp, #-0x68] sub x3, fp, #160 ldr x0, [fp, #-0x78] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 str x0, [fp, #-0xF0] ldr x1, [fp, #-0xF0] ldr x0, [fp, #-0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #-0x08] add x14, x14, #72 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF str xzr, [fp, #-0x78] G_M000_IG22: ldp x0, x4, [fp, #-0x28] stp x0, x4, [fp, #-0x70] G_M000_IG23: ldr x4, [fp, #-0x70] ldr x5, [fp, #-0x68] sub x0, fp, #160 ldr x3, [fp, #-0x78] mov w1, #28 mov w2, #1 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 ldr x1, [fp, #-0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x1, [fp, #-0x70] ldr x2, [fp, #-0x68] sub x3, fp, #160 ldr x0, [fp, #-0x78] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 str x0, [fp, #-0xF8] ldr x1, [fp, #-0xF8] ldr x0, [fp, #-0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #-0x08] add x14, x14, #80 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF str xzr, [fp, #-0x78] G_M000_IG24: ldp x0, x4, [fp, #-0x28] stp x0, x4, [fp, #-0x70] G_M000_IG25: ldr x4, [fp, #-0x70] ldr x5, [fp, #-0x68] sub x0, fp, #160 ldr x3, [fp, #-0x78] mov w1, #35 mov w2, #1 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 ldr x1, [fp, #-0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x1, [fp, #-0x70] ldr x2, [fp, #-0x68] sub x3, fp, #160 ldr x0, [fp, #-0x78] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 str x0, [fp, #-0x100] ldr x1, [fp, #-0x100] ldr x0, [fp, #-0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #-0x08] add x14, x14, #88 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF str xzr, [fp, #-0x78] G_M000_IG26: ldp x0, x4, [fp, #-0x28] stp x0, x4, [fp, #-0x70] G_M000_IG27: ldr x4, [fp, #-0x70] ldr x5, [fp, #-0x68] sub x0, fp, #160 ldr x3, [fp, #-0x78] mov w1, #32 mov w2, #1 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 ldr x1, [fp, #-0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x1, [fp, #-0x70] ldr x2, [fp, #-0x68] sub x3, fp, #160 ldr x0, [fp, #-0x78] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 movn xip1, #0xD1FFAB1E str x0, [fp, xip1] movn xip1, #0xD1FFAB1E ldr x1, [fp, xip1] ldr x0, [fp, #-0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #-0x08] add x14, x14, #96 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF str xzr, [fp, #-0x78] G_M000_IG28: ldp x0, x4, [fp, #-0x28] stp x0, x4, [fp, #-0x70] G_M000_IG29: ldr x4, [fp, #-0x70] ldr x5, [fp, #-0x68] sub x0, fp, #160 ldr x3, [fp, #-0x78] mov w1, #32 mov w2, #1 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 ldr x1, [fp, #-0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #160 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x1, [fp, #-0x70] ldr x2, [fp, #-0x68] sub x3, fp, #160 ldr x0, [fp, #-0x78] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 movn xip1, #0xD1FFAB1E str x0, [fp, xip1] movn xip1, #0xD1FFAB1E ldr x1, [fp, xip1] ldr x0, [fp, #-0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #-0x08] add x14, x14, #104 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #-0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #-0x08] add x14, x14, #112 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF sub x8, fp, #96 ldr x0, [fp, #-0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w0, [fp, #-0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #-0x08] str w0, [x1, #0x78] ldr w0, [fp, #-0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #-0x08] str w0, [x1, #0x7C] ldr w0, [fp, #-0x54] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #-0x08] str w0, [x1, #0x80] ldr w0, [fp, #-0x54] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #-0x08] str w0, [x1, #0x84] ldr w0, [fp, #-0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #-0x08] str w0, [x1, #0x88] ldr w0, [fp, #-0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #-0x08] str w0, [x1, #0x8C] ldr w0, [fp, #-0x4C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #-0x08] str w0, [x1, #0x90] ldr w0, [fp, #-0x4C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #-0x08] str w0, [x1, #0x94] ldr w0, [fp, #-0x44] and w0, w0, #1 cmp w0, #0 cset x0, ne ldr x1, [fp, #-0x08] strb w0, [x1, #0x98] ldr w0, [fp, #-0x44] and w0, w0, #4 cmp w0, #0 cset x0, ne ldr x1, [fp, #-0x08] strb w0, [x1, #0x99] ldr w0, [fp, #-0x44] and w0, w0, #8 cmp w0, #0 cset x0, ne ldr x1, [fp, #-0x08] strb w0, [x1, #0x9A] ldr w0, [fp, #-0x44] and w0, w0, #2 cmp w0, #0 cset x0, ne ldr x1, [fp, #-0x08] strb w0, [x1, #0x9B] ldr w0, [fp, #-0x44] and w0, w0, #32 cmp w0, #0 cset x0, ne ldr x1, [fp, #-0x08] strb w0, [x1, #0x9C] ldr x0, [fp, #-0x08] ldr x0, [x0, #0x20] movz x1, #8 movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 movn xip1, #0xD1FFAB1E G_M000_IG30: ldr xip1, [fp, xip1] cmp xip0, xip1 beq G_M000_IG31 bl CORINFO_HELP_FAIL_FAST G_M000_IG31: sub sp, fp, #0xD1FFAB1E ldp fp, lr, [sp, #0xD1FFAB1E] add sp, sp, #0xD1FFAB1E ret lr ; Total bytes of code 3568 148: JIT compiled System.Diagnostics.FileVersionInfo:GetVersionInfoForCodePage(ulong,System.String) [Tier0, IL size=1107, code size=3568] ; Assembly listing for method System.Diagnostics.FileVersionInfo:GetFileVersionString(ulong,System.String):System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: add x2, fp, #24 add x3, fp, #16 ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 cbz w0, G_M000_IG04 ldr x0, [fp, #0x18] cbz x0, G_M000_IG04 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: movz x0, #8 movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 116 149: JIT compiled System.Diagnostics.FileVersionInfo:GetFileVersionString(ulong,System.String) [Tier0, IL size=31, code size=116] ; Assembly listing for method System.Diagnostics.FileVersionInfo:GetFileVersionLanguage(ulong):System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: sub sp, sp, #224 stp x19, x20, [sp, #0x80] stp x21, x22, [sp, #0x90] stp x23, x24, [sp, #0xA0] stp x25, x26, [sp, #0xB0] stp x27, x28, [sp, #0xC0] stp fp, lr, [sp, #0xD0] add fp, sp, #208 str xzr, [fp, #-0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [fp, #-0x88] str x0, [fp, #-0x58] G_M000_IG02: sub x0, fp, #200 mov x1, x12 bl CORINFO_HELP_INIT_PINVOKE_FRAME str x0, [fp, #-0x80] mov x0, sp str x0, [fp, #-0xA8] mov x0, fp str x0, [fp, #-0x98] ldr x0, [fp, #-0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 lsr w0, w0, #16 str w0, [fp, #-0x5C] ldp x0, xzr, [sp], #0xD1FFAB1E mov x0, sp str x0, [fp, #-0x68] ldr w0, [fp, #-0x5C] ldr x1, [fp, #-0x68] mov w2, #0xD1FFAB1E movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 str x3, [fp, #-0xB8] adr x3, [G_M000_IG05] str x3, [fp, #-0xA0] ldr x3, [fp, #-0x80] sub x4, fp, #200 str x4, [x3, #0x10] ldr x3, [fp, #-0x80] strb wzr, [x3, #0x0C] G_M000_IG03: movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG04: blr x3 G_M000_IG05: mov w19, w0 ldr x0, [fp, #-0x80] mov w1, #1 strb w1, [x0, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG06 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG06: ldr x0, [fp, #-0x80] ldr x2, [fp, #-0xC0] str x2, [x0, #0x10] str w19, [fp, #-0x6C] ldr x0, [fp, #-0x68] ldr w2, [fp, #-0x6C] mov w1, wzr bl System.String:.ctor(ulong,int,int):this str x0, [fp, #-0x78] b G_M000_IG07 G_M000_IG07: ldr x0, [fp, #-0x78] movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #-0x88] cmp xip0, xip1 beq G_M000_IG08 bl CORINFO_HELP_FAIL_FAST G_M000_IG08: sub sp, fp, #208 ldp fp, lr, [sp, #0xD0] ldp x27, x28, [sp, #0xC0] ldp x25, x26, [sp, #0xB0] ldp x23, x24, [sp, #0xA0] ldp x21, x22, [sp, #0x90] ldp x19, x20, [sp, #0x80] add sp, sp, #224 ret lr ; Total bytes of code 360 150: JIT compiled System.Diagnostics.FileVersionInfo:GetFileVersionLanguage(ulong) [Tier0, IL size=41, code size=360] ; Assembly listing for method System.Diagnostics.FileVersionInfo:GetFixedFileInfo(ulong):Interop+Version+VS_FIXEDFILEINFO ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp str x0, [fp, #0x60] str x8, [fp, #0x68] G_M000_IG02: add x2, fp, #88 add x3, fp, #80 ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 cbz w0, G_M000_IG04 ldr x0, [fp, #0x58] ldr x1, [fp, #0x68] ldp q16, q17, [x0] stp q16, q17, [x1] ldr q16, [x0, #0x20] str q16, [x1, #0x20] ldr w2, [x0, #0x30] str w2, [x1, #0x30] G_M000_IG03: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG04: stp xzr, xzr, [fp, #0x18] stp xzr, xzr, [fp, #0x28] stp xzr, xzr, [fp, #0x38] str wzr, [fp, #0x48] ldr x0, [fp, #0x68] G_M000_IG05: add x1, fp, #24 ldp q16, q17, [x1] stp q16, q17, [x0] ldr q16, [x1, #0x20] str q16, [x0, #0x20] ldr w2, [x1, #0x30] str w2, [x0, #0x30] G_M000_IG06: ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 160 151: JIT compiled System.Diagnostics.FileVersionInfo:GetFixedFileInfo(ulong) [Tier0, IL size=34, code size=160] ; Assembly listing for method System.Diagnostics.FileVersionInfo:HIWORD(uint):uint ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str w0, [fp, #0x1C] G_M000_IG02: ldr w0, [fp, #0x1C] lsr w0, w0, #16 and w0, w0, #0xD1FFAB1E G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 32 152: JIT compiled System.Diagnostics.FileVersionInfo:HIWORD(uint) [Tier0, IL size=11, code size=32] ; Assembly listing for method System.Diagnostics.FileVersionInfo:LOWORD(uint):uint ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str w0, [fp, #0x1C] G_M000_IG02: ldr w0, [fp, #0x1C] and w0, w0, #0xD1FFAB1E G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 153: JIT compiled System.Diagnostics.FileVersionInfo:LOWORD(uint) [Tier0, IL size=8, code size=28] ; Assembly listing for method BenchmarkDotNet.Environments.CoreRuntime:TryGetVersion(byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x90]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp xzr, xzr, [x9, #0x60] str x0, [fp, #0x88] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cmp w0, #5 blt G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr x14, [fp, #0x88] mov x15, x0 bl CORINFO_HELP_CHECKED_ASSIGN_REF b G_M000_IG11 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x40] ldr x0, [fp, #0x40] ldr x1, [fp, #0x88] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG04 b G_M000_IG11 G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x38] ldr x0, [fp, #0x38] ldr x1, [fp, #0x38] ldr x1, [x1] ldr x1, [x1, #0x50] ldr x1, [x1, #0x28] blr x1 str x0, [fp, #0x30] ldr x0, [fp, #0x30] ldr x1, [fp, #0x30] ldr x1, [x1] ldr x1, [x1, #0x48] ldr x1, [x1, #0x30] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x80] ldr x0, [fp, #0x80] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x78] ldr x0, [fp, #0x80] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x28] ldr x1, [fp, #0x28] ldr x0, [fp, #0x78] ldr x2, [fp, #0x88] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 cbz w0, G_M000_IG05 b G_M000_IG11 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x70] ldr x1, [fp, #0x70] str x1, [fp, #0x68] ldr x1, [fp, #0x70] cbnz x1, G_M000_IG06 str xzr, [fp, #0x50] b G_M000_IG08 G_M000_IG06: ldr x1, [fp, #0x68] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x60] ldr x0, [fp, #0x60] str x0, [fp, #0x58] ldr x0, [fp, #0x60] cbnz x0, G_M000_IG07 str xzr, [fp, #0x50] b G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x50] G_M000_IG08: ldr x0, [fp, #0x50] ldr x1, [fp, #0x88] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG09 b G_M000_IG11 G_M000_IG09: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG13 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x88] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG10 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x88] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x4C] b G_M000_IG16 G_M000_IG10: b G_M000_IG11 G_M000_IG11: mov w0, #1 G_M000_IG12: ldp fp, lr, [sp], #0x90 ret lr G_M000_IG13: ldr x0, [fp, #0x88] str xzr, [x0] b G_M000_IG14 G_M000_IG14: mov w0, wzr G_M000_IG15: ldp fp, lr, [sp], #0x90 ret lr G_M000_IG16: ldr w0, [fp, #0x4C] uxtb w0, w0 G_M000_IG17: ldp fp, lr, [sp], #0x90 ret lr ; Total bytes of code 776 154: JIT compiled BenchmarkDotNet.Environments.CoreRuntime:TryGetVersion(byref) [Tier0, IL size=173, code size=776] ; Assembly listing for method System.Version:TryFormatCore[ushort](System.Span`1[ushort],int,byref):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0xC0]! mov fp, sp add x9, fp, #32 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str x0, [fp, #0xB8] str x1, [fp, #0xA8] str x2, [fp, #0xB0] str w3, [fp, #0xA4] str x4, [fp, #0x98] G_M000_IG02: ldr w0, [fp, #0xA4] str w0, [fp, #0x90] mov w0, #0xD1FFAB1E str w0, [fp, #0x18] ldr w0, [fp, #0x90] cmp w0, #4 bhi G_M000_IG04 ldr w0, [fp, #0x90] cmp w0, #3 bhs G_M000_IG05 b G_M000_IG09 G_M000_IG03: ldr w0, [fp, #0x90] cmp w0, #4 beq G_M000_IG08 b G_M000_IG09 G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 b G_M000_IG09 G_M000_IG05: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG07 G_M000_IG06: add x0, fp, #24 mov w1, #30 bl CORINFO_HELP_PATCHPOINT G_M000_IG07: ldr x0, [fp, #0xB8] ldr w0, [x0, #0x10] cmn w0, #1 bne G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 b G_M000_IG09 G_M000_IG08: ldr x0, [fp, #0xB8] ldr w0, [x0, #0x14] cmn w0, #1 bne G_M000_IG09 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG09: str wzr, [fp, #0x94] str wzr, [fp, #0x8C] b G_M000_IG27 G_M000_IG10: ldr w0, [fp, #0x8C] cbz w0, G_M000_IG15 add x0, fp, #168 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG12 ldr x0, [fp, #0x98] str wzr, [x0] mov w0, wzr G_M000_IG11: ldp fp, lr, [sp], #0xC0 ret lr G_M000_IG12: ldr w0, [fp, #0xB0] cmp w0, #0 bls G_M000_IG31 ldr x0, [fp, #0xA8] str x0, [fp, #0x30] mov w0, #46 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x30] strh w0, [x1] add x0, fp, #168 mov w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x20] str x1, [fp, #0x28] G_M000_IG13: ldp x0, x1, [fp, #0x20] stp x0, x1, [fp, #0xA8] G_M000_IG14: ldr w0, [fp, #0x94] add w0, w0, #1 str w0, [fp, #0x94] G_M000_IG15: ldr w0, [fp, #0x8C] cmp w0, #2 bhi G_M000_IG16 ldr w0, [fp, #0x8C] mov w0, w0 adr x1, [@RWD00] ldr w1, [x1, x0, LSL #2] adr x2, [G_M000_IG02] add x1, x1, x2 br x1 G_M000_IG16: b G_M000_IG20 G_M000_IG17: ldr x0, [fp, #0xB8] ldr w0, [x0, #0x08] str w0, [fp, #0x78] b G_M000_IG21 G_M000_IG18: ldr x0, [fp, #0xB8] ldr w0, [x0, #0x0C] str w0, [fp, #0x78] b G_M000_IG21 G_M000_IG19: ldr x0, [fp, #0xB8] ldr w0, [x0, #0x10] str w0, [fp, #0x78] b G_M000_IG21 G_M000_IG20: ldr x0, [fp, #0xB8] ldr w0, [x0, #0x14] str w0, [fp, #0x78] G_M000_IG21: ldr w0, [fp, #0x78] str w0, [fp, #0x88] b G_M000_IG22 G_M000_IG22: ldr w0, [fp, #0x88] str w0, [fp, #0x70] ldr x0, [fp, #0xA8] ldr x1, [fp, #0xB0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x50] str x1, [fp, #0x58] stp xzr, xzr, [fp, #0x60] ldr x1, [fp, #0x50] ldr x2, [fp, #0x58] ldr x4, [fp, #0x60] ldr x5, [fp, #0x68] add x3, fp, #128 add x0, fp, #112 mov x6, xzr movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 str w0, [fp, #0x4C] ldr w0, [fp, #0x4C] uxtb w0, w0 str w0, [fp, #0x7C] ldr w0, [fp, #0x7C] cbnz w0, G_M000_IG24 ldr x0, [fp, #0x98] str wzr, [x0] mov w0, wzr G_M000_IG23: ldp fp, lr, [sp], #0xC0 ret lr G_M000_IG24: ldr w0, [fp, #0x94] ldr w1, [fp, #0x80] add w0, w0, w1 str w0, [fp, #0x94] add x0, fp, #168 ldr w1, [fp, #0x80] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x38] str x1, [fp, #0x40] G_M000_IG25: ldp x0, x1, [fp, #0x38] stp x0, x1, [fp, #0xA8] G_M000_IG26: ldr w0, [fp, #0x8C] add w0, w0, #1 str w0, [fp, #0x8C] G_M000_IG27: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG29 G_M000_IG28: add x0, fp, #24 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG29: ldr w0, [fp, #0x8C] ldr w1, [fp, #0xA4] cmp w0, w1 blt G_M000_IG10 ldr x0, [fp, #0x98] ldr w1, [fp, #0x94] str w1, [x0] mov w0, #1 G_M000_IG30: ldp fp, lr, [sp], #0xC0 ret lr G_M000_IG31: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 RWD00 dd G_M000_IG17 - G_M000_IG02 dd G_M000_IG18 - G_M000_IG02 dd G_M000_IG19 - G_M000_IG02 ; Total bytes of code 868 155: JIT compiled System.Version:TryFormatCore[ushort](System.Span`1[ushort],int,byref) [Tier0, IL size=331, code size=868] ; Assembly listing for method System.Runtime.InteropServices.MemoryMarshal:Cast[ushort,ushort](System.Span`1[ushort]):System.Span`1[ushort] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x40] str x1, [fp, #0x48] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: mov w0, #2 str w0, [fp, #0x3C] mov w0, #2 str w0, [fp, #0x38] ldr w0, [fp, #0x48] str w0, [fp, #0x34] ldr w0, [fp, #0x3C] ldr w1, [fp, #0x38] cmp w0, w1 bne G_M000_IG05 ldr w0, [fp, #0x34] str w0, [fp, #0x30] b G_M000_IG07 G_M000_IG05: ldr w0, [fp, #0x3C] cmp w0, #1 bne G_M000_IG06 ldr w0, [fp, #0x34] ldr w1, [fp, #0x38] cmp w1, #0 beq G_M000_IG09 udiv w0, w0, w1 str w0, [fp, #0x30] b G_M000_IG07 G_M000_IG06: ldr w0, [fp, #0x34] mov w0, w0 ldr w1, [fp, #0x3C] mov w1, w1 mul x0, x0, x1 ldr w1, [fp, #0x38] mov w1, w1 cmp x1, #0 beq G_M000_IG09 udiv x0, x0, x1 str x0, [fp, #0x28] ldr x0, [fp, #0x28] tst x0, #0xD1FFAB1E bne G_M000_IG10 str w0, [fp, #0x30] G_M000_IG07: stp xzr, xzr, [fp, #0x18] add x0, fp, #24 ldr x1, [fp, #0x40] ldr w2, [fp, #0x30] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] ldr x1, [fp, #0x20] G_M000_IG08: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG09: bl CORINFO_HELP_THROWDIVZERO G_M000_IG10: bl CORINFO_HELP_OVERFLOW brk_windows #0 ; Total bytes of code 348 156: JIT compiled System.Runtime.InteropServices.MemoryMarshal:Cast[ushort,ushort](System.Span`1[ushort]) [Tier0, IL size=115, code size=348] ; Assembly listing for method System.Char:System.IUtfChar.CastFrom(ushort):ushort ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str w0, [fp, #0x1C] G_M000_IG02: ldr w0, [fp, #0x1C] uxth w0, w0 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 157: JIT compiled System.Char:System.IUtfChar.CastFrom(ushort) [Tier0, IL size=2, code size=28] ; Assembly listing for method System.Diagnostics.FileVersionInfo:get_FileVersion():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 158: JIT compiled System.Diagnostics.FileVersionInfo:get_FileVersion() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_RuntimeVersion(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #24 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 159: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_RuntimeVersion(System.String) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Portability.RuntimeInformation:GetConfiguration():System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 strh w0, [fp, #0x18] add x0, fp, #24 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: add x0, fp, #24 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG07: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 172 160: JIT compiled BenchmarkDotNet.Portability.RuntimeInformation:GetConfiguration() [Tier0, IL size=47, code size=172] ; Assembly listing for method BenchmarkDotNet.Extensions.AssemblyExtensions:IsDebug(System.Reflection.Assembly):System.Nullable`1[bool] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 64 161: JIT compiled BenchmarkDotNet.Extensions.AssemblyExtensions:IsDebug(System.Reflection.Assembly) [Tier0, IL size=12, code size=64] ; Assembly listing for method BenchmarkDotNet.Extensions.AssemblyExtensions:GetDebuggableAttribute(System.Reflection.Assembly):System.Diagnostics.DebuggableAttribute ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] cbnz x0, G_M000_IG04 mov x0, xzr G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x20] ldr x1, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 152 162: JIT compiled BenchmarkDotNet.Extensions.AssemblyExtensions:GetDebuggableAttribute(System.Reflection.Assembly) [Tier0, IL size=22, code size=152] ; Assembly listing for method System.Linq.Enumerable:OfType[System.__Canon](System.Collections.IEnumerable):System.Collections.Generic.IEnumerable`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x0, [fp, #0x20] str x1, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG06: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG07: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 148 163: JIT compiled System.Linq.Enumerable:OfType[System.__Canon](System.Collections.IEnumerable) [Tier0, IL size=17, code size=148] ; Assembly listing for method System.Linq.Enumerable:OfTypeIterator[System.__Canon](System.Collections.IEnumerable):System.Collections.Generic.IEnumerable`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x20] str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x18] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x18] G_M000_IG05: ldr x0, [fp, #0x18] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] movn w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x20] add x14, x14, #24 ldr x15, [fp, #0x28] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x20] G_M000_IG06: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 152 164: JIT compiled System.Linq.Enumerable:OfTypeIterator[System.__Canon](System.Collections.IEnumerable) [Tier0, IL size=15, code size=152] ; Assembly listing for method System.Linq.Enumerable+d__65`1[System.__Canon]:.ctor(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x18] ldr w1, [fp, #0x14] str w1, [x0, #0x28] bl System.Environment:get_CurrentManagedThreadId():int ldr x1, [fp, #0x18] str w0, [x1, #0x2C] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 72 165: JIT compiled System.Linq.Enumerable+d__65`1[System.__Canon]:.ctor(int) [Tier0, IL size=25, code size=72] ; Assembly listing for method System.Linq.Enumerable:SingleOrDefault[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon]):System.__Canon ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x2, [fp, #0x30] ldr x2, [x2, #0x10] ldr x2, [x2, #0x10] str x2, [fp, #0x18] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x18] G_M000_IG05: add x2, fp, #32 ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG06: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 120 166: JIT compiled System.Linq.Enumerable:SingleOrDefault[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon]) [Tier0, IL size=9, code size=120] ; Assembly listing for method System.Linq.Enumerable:TryGetSingle[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],byref):System.__Canon ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0xC0]! mov fp, sp add x9, fp, #104 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] add x3, sp, #192 str x3, [fp, #0xB8] str x0, [fp, #0xB0] str x0, [fp, #0xA8] str x1, [fp, #0xA0] str x2, [fp, #0x98] G_M000_IG02: ldr x0, [fp, #0xA0] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0xA8] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0xA8] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x60] b G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x60] G_M000_IG06: ldr x0, [fp, #0x60] ldr x1, [fp, #0xA0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x90] ldr x0, [fp, #0x90] cbz x0, G_M000_IG18 ldr x0, [fp, #0xA8] ldr x0, [x0, #0x10] ldr x0, [x0, #0x28] cbz x0, G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0xA8] ldr x0, [x0, #0x10] ldr x0, [x0, #0x28] str x0, [fp, #0x38] b G_M000_IG09 G_M000_IG08: ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x38] G_M000_IG09: ldr x0, [fp, #0x38] str x0, [fp, #0x30] ldr x0, [fp, #0x90] ldr x11, [fp, #0x30] ldr x1, [fp, #0x30] ldr x1, [x1] blr x1 str w0, [fp, #0x8C] ldr w0, [fp, #0x8C] cbz w0, G_M000_IG10 ldr w0, [fp, #0x8C] cmp w0, #1 beq G_M000_IG12 b G_M000_IG34 G_M000_IG10: ldr x0, [fp, #0x98] strb wzr, [x0] str xzr, [fp, #0x80] ldr x0, [fp, #0x80] G_M000_IG11: ldp fp, lr, [sp], #0xC0 ret lr G_M000_IG12: ldr x0, [fp, #0x98] mov w1, #1 strb w1, [x0] ldr x0, [fp, #0xA8] ldr x0, [x0, #0x10] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] cmp x0, #48 ble G_M000_IG15 G_M000_IG13: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] cbz x0, G_M000_IG15 G_M000_IG14: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] str x0, [fp, #0x28] b G_M000_IG16 G_M000_IG15: ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x28] G_M000_IG16: ldr x0, [fp, #0x28] str x0, [fp, #0x20] ldr x0, [fp, #0x90] ldr x11, [fp, #0x20] mov w1, wzr ldr x2, [fp, #0x20] ldr x2, [x2] blr x2 G_M000_IG17: ldp fp, lr, [sp], #0xC0 ret lr G_M000_IG18: ldr x0, [fp, #0xA8] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] cbz x0, G_M000_IG20 G_M000_IG19: ldr x0, [fp, #0xA8] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] str x0, [fp, #0x58] b G_M000_IG21 G_M000_IG20: ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x58] G_M000_IG21: ldr x0, [fp, #0x58] str x0, [fp, #0x50] ldr x0, [fp, #0xA0] ldr x11, [fp, #0x50] ldr x1, [fp, #0x50] ldr x1, [x1] blr x1 str x0, [fp, #0x78] G_M000_IG22: ldr x0, [fp, #0x78] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG23 ldr x0, [fp, #0x98] strb wzr, [x0] str xzr, [fp, #0x80] b G_M000_IG28 G_M000_IG23: ldr x0, [fp, #0xA8] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] cbz x0, G_M000_IG25 G_M000_IG24: ldr x0, [fp, #0xA8] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] str x0, [fp, #0x48] b G_M000_IG26 G_M000_IG25: ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x48] G_M000_IG26: ldr x0, [fp, #0x48] str x0, [fp, #0x40] ldr x0, [fp, #0x78] ldr x11, [fp, #0x40] ldr x1, [fp, #0x40] ldr x1, [x1] blr x1 str x0, [fp, #0x70] ldr x0, [fp, #0x78] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG27 ldr x0, [fp, #0x98] mov w1, #1 strb w1, [x0] ldr x0, [fp, #0x70] str x0, [fp, #0x80] b G_M000_IG30 G_M000_IG27: b G_M000_IG32 G_M000_IG28: ldr x0, [fp, #0xB8] bl G_M000_IG38 G_M000_IG29: b G_M000_IG36 G_M000_IG30: ldr x0, [fp, #0xB8] bl G_M000_IG38 G_M000_IG31: b G_M000_IG36 G_M000_IG32: ldr x0, [fp, #0xB8] bl G_M000_IG38 G_M000_IG33: nop G_M000_IG34: ldr x0, [fp, #0x98] strb wzr, [x0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str xzr, [fp, #0x68] ldr x0, [fp, #0x68] G_M000_IG35: ldp fp, lr, [sp], #0xC0 ret lr G_M000_IG36: ldr x0, [fp, #0x80] G_M000_IG37: ldp fp, lr, [sp], #0xC0 ret lr G_M000_IG38: stp fp, lr, [sp, #-0x20]! add x3, fp, #192 str x3, [sp, #0x18] G_M000_IG39: ldr x0, [fp, #0x78] cbz x0, G_M000_IG40 ldr x0, [fp, #0x78] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG40: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 880 167: JIT compiled System.Linq.Enumerable:TryGetSingle[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],byref) [Tier0, IL size=147, code size=880] ; Assembly listing for method System.Linq.Enumerable+d__65`1[System.__Canon]:System.Collections.Generic.IEnumerable.GetEnumerator():System.Collections.Generic.IEnumerator`1[System.__Canon]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str x0, [fp, #0x38] str x0, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x30] ldr w0, [x0, #0x28] cmn w0, #2 bne G_M000_IG03 ldr x0, [fp, #0x30] ldr w0, [x0, #0x2C] str w0, [fp, #0x1C] bl System.Environment:get_CurrentManagedThreadId():int ldr w1, [fp, #0x1C] cmp w0, w1 bne G_M000_IG03 ldr x0, [fp, #0x30] str wzr, [x0, #0x28] ldr x0, [fp, #0x30] str x0, [fp, #0x28] b G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x30] ldr x0, [x0] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] mov w1, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x20] str x14, [fp, #0x28] G_M000_IG04: ldr x14, [fp, #0x30] ldr x15, [x14, #0x18] ldr x14, [fp, #0x28] add x14, x14, #16 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x28] G_M000_IG05: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 172 168: JIT compiled System.Linq.Enumerable+d__65`1[System.__Canon]:System.Collections.Generic.IEnumerable.GetEnumerator() [Tier0, IL size=55, code size=172] ; Assembly listing for method System.Linq.Enumerable+d__65`1[System.__Canon]:MoveNext():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] add x1, sp, #80 str x1, [fp, #0x48] str x0, [fp, #0x40] str x0, [fp, #0x38] G_M000_IG02: ldr x0, [fp, #0x38] ldr w0, [x0, #0x28] str w0, [fp, #0x30] mov w0, #0xD1FFAB1E str w0, [fp, #0x18] ldr w0, [fp, #0x30] cbz w0, G_M000_IG03 ldr w0, [fp, #0x30] cmp w0, #1 beq G_M000_IG05 str wzr, [fp, #0x34] b G_M000_IG09 G_M000_IG03: ldr x0, [fp, #0x38] movn w11, #0 str w11, [x0, #0x28] ldr x0, [fp, #0x38] ldr x0, [x0, #0x10] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 ldr x14, [fp, #0x38] add x14, x14, #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x38] movn w1, #2 str w1, [x0, #0x28] b G_M000_IG06 G_M000_IG04: ldr x0, [fp, #0x38] ldr x0, [x0, #0x20] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x28] ldr x0, [fp, #0x38] ldr x0, [x0] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz x0, G_M000_IG06 ldr x0, [fp, #0x38] ldr x0, [x0] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x20] ldr x14, [fp, #0x38] add x14, x14, #8 ldr x15, [fp, #0x20] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x38] mov w1, #1 str w1, [x0, #0x28] mov w1, #1 str w1, [fp, #0x34] b G_M000_IG09 G_M000_IG05: ldr x0, [fp, #0x38] movn w1, #2 str w1, [x0, #0x28] G_M000_IG06: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG08 G_M000_IG07: add x0, fp, #24 mov w1, #105 bl CORINFO_HELP_PATCHPOINT G_M000_IG08: ldr x0, [fp, #0x38] ldr x0, [x0, #0x20] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG04 ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x38] str xzr, [x0, #0x20] str wzr, [fp, #0x34] b G_M000_IG09 G_M000_IG09: ldr w0, [fp, #0x34] G_M000_IG10: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG11: stp fp, lr, [sp, #-0x20]! add x3, fp, #80 str x3, [sp, #0x18] G_M000_IG12: ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG13: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 496 169: JIT compiled System.Linq.Enumerable+d__65`1[System.__Canon]:MoveNext() [Tier0, IL size=144, code size=496] ; Assembly listing for method System.Linq.Enumerable+d__65`1[System.__Canon]:System.Collections.Generic.IEnumerator.get_Current():System.__Canon:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 170: JIT compiled System.Linq.Enumerable+d__65`1[System.__Canon]:System.Collections.Generic.IEnumerator.get_Current() [Tier0, IL size=7, code size=28] ; Assembly listing for method System.Linq.Enumerable+d__65`1[System.__Canon]:<>m__Finally1():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: ldr x1, [fp, #0x18] movn w0, #0 str w0, [x1, #0x28] ldr x1, [fp, #0x18] ldr x1, [x1, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x10] ldr x0, [fp, #0x10] cbz x0, G_M000_IG03 ldr x0, [fp, #0x10] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 112 171: JIT compiled System.Linq.Enumerable+d__65`1[System.__Canon]:<>m__Finally1() [Tier0, IL size=29, code size=112] ; Assembly listing for method System.Linq.Enumerable+d__65`1[System.__Canon]:System.IDisposable.Dispose():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp add x1, sp, #48 str x1, [fp, #0x28] str x0, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x20] ldr w0, [x0, #0x28] str w0, [fp, #0x1C] ldr w0, [fp, #0x1C] cmn w0, #3 beq G_M000_IG03 ldr w0, [fp, #0x1C] cmp w0, #1 bne G_M000_IG06 G_M000_IG03: b G_M000_IG04 G_M000_IG04: ldr x0, [fp, #0x28] bl G_M000_IG07 G_M000_IG05: nop G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG07: stp fp, lr, [sp, #-0x20]! add x3, fp, #48 str x3, [sp, #0x18] G_M000_IG08: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG09: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 124 172: JIT compiled System.Linq.Enumerable+d__65`1[System.__Canon]:System.IDisposable.Dispose() [Tier0, IL size=27, code size=124] ; Assembly listing for method BenchmarkDotNet.Extensions.AssemblyExtensions:IsJitTrackingEnabled(System.Diagnostics.DebuggableAttribute):System.Nullable`1[bool] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] cbnz x0, G_M000_IG04 strh wzr, [fp, #0x20] ldr w0, [fp, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: strh wzr, [fp, #0x18] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x14] ldr w1, [fp, #0x14] add x0, fp, #24 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [fp, #0x18] G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 112 173: JIT compiled BenchmarkDotNet.Extensions.AssemblyExtensions:IsJitTrackingEnabled(System.Diagnostics.DebuggableAttribute) [Tier0, IL size=25, code size=112] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_Configuration(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #16 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 174: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_Configuration(System.String) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Portability.RuntimeInformation:HasRyuJit():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG04 mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG06 mov w0, #1 G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x10] ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x18] mov w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cmp w0, #0 cset x0, eq G_M000_IG07: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG08: mov w0, wzr G_M000_IG09: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 276 175: JIT compiled BenchmarkDotNet.Portability.RuntimeInformation:HasRyuJit() [Tier0, IL size=59, code size=276] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_HasRyuJit(bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr x0, [fp, #0x18] ldr w1, [fp, #0x14] strb w1, [x0, #0x39] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 36 176: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_HasRyuJit(bool) [Tier0, IL size=8, code size=36] ; Assembly listing for method BenchmarkDotNet.Portability.RuntimeInformation:GetJitInfo():System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x18] b G_M000_IG11 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbnz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG05 G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x18] b G_M000_IG11 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbnz w0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG07 G_M000_IG06: movz x0, #8 movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x18] b G_M000_IG11 G_M000_IG07: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbnz w0, G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG09 G_M000_IG08: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x18] b G_M000_IG11 G_M000_IG09: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG10 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x18] b G_M000_IG11 G_M000_IG10: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x18] b G_M000_IG11 G_M000_IG11: ldr x0, [fp, #0x18] G_M000_IG12: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 336 177: JIT compiled BenchmarkDotNet.Portability.RuntimeInformation:GetJitInfo() [Tier0, IL size=92, code size=336] ; Assembly listing for method BenchmarkDotNet.Portability.RuntimeInformation:get_IsNativeAOT():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cmp w0, #5 blt G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x1, [x1] ldr x1, [x1, #0x50] ldr x1, [x1, #0x28] blr x1 str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x1, [fp, #0x10] ldr x1, [x1] ldr x1, [x1, #0x48] ldr x1, [x1, #0x30] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cmp w0, #0 cset x0, eq G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: mov w0, wzr G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 208 178: JIT compiled BenchmarkDotNet.Portability.RuntimeInformation:get_IsNativeAOT() [Tier0, IL size=51, code size=208] ; Assembly listing for method BenchmarkDotNet.Portability.RuntimeInformation:get_IsNetNative():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 mov w2, #5 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 88 179: JIT compiled BenchmarkDotNet.Portability.RuntimeInformation:get_IsNetNative() [Tier0, IL size=17, code size=88] ; Assembly listing for method BenchmarkDotNet.Portability.RuntimeInformation:get_IsAot():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cmp w0, #0 cset x0, eq G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 44 180: JIT compiled BenchmarkDotNet.Portability.RuntimeInformation:get_IsAot() [Tier0, IL size=9, code size=44] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_JitInfo(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #32 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 181: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_JitInfo(System.String) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:GetShortInfo():System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x18] b G_M000_IG14 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x18] b G_M000_IG14 G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x18] b G_M000_IG14 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x18] b G_M000_IG14 G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG07 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x18] b G_M000_IG14 G_M000_IG07: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x18] b G_M000_IG14 G_M000_IG08: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG09 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x18] b G_M000_IG14 G_M000_IG09: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG10 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x18] b G_M000_IG14 G_M000_IG10: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG11 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x18] b G_M000_IG14 G_M000_IG11: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG12 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x18] b G_M000_IG14 G_M000_IG12: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG13 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x18] b G_M000_IG14 G_M000_IG13: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x18] b G_M000_IG14 G_M000_IG14: ldr x0, [fp, #0x18] G_M000_IG15: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 536 182: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:GetShortInfo() [Tier0, IL size=149, code size=536] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsX86Avx2Supported():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 183: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsX86Avx2Supported() [Tier0, IL size=6, code size=20] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsX86AvxSupported():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 184: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsX86AvxSupported() [Tier0, IL size=6, code size=20] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsX86Sse42Supported():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 185: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsX86Sse42Supported() [Tier0, IL size=6, code size=20] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsX86Sse41Supported():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 186: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsX86Sse41Supported() [Tier0, IL size=6, code size=20] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsX86Ssse3Supported():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 187: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsX86Ssse3Supported() [Tier0, IL size=6, code size=20] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsX86Sse3Supported():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 188: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsX86Sse3Supported() [Tier0, IL size=6, code size=20] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsX86Sse2Supported():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 189: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsX86Sse2Supported() [Tier0, IL size=6, code size=20] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsX86SseSupported():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 190: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsX86SseSupported() [Tier0, IL size=6, code size=20] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsX86BaseSupported():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 191: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsX86BaseSupported() [Tier0, IL size=6, code size=20] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsArmAdvSimdSupported():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, #1 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 192: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsArmAdvSimdSupported() [Tier0, IL size=6, code size=20] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_HardwareIntrinsicsShort(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #40 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 193: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_HardwareIntrinsicsShort(System.String) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_IsServerGC(bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr x0, [fp, #0x18] ldr w1, [fp, #0x14] strb w1, [x0, #0x3A] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 36 194: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_IsServerGC(bool) [Tier0, IL size=8, code size=36] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_IsConcurrentGC(bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr x0, [fp, #0x18] ldr w1, [fp, #0x14] strb w1, [x0, #0x3B] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 36 195: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_IsConcurrentGC(bool) [Tier0, IL size=8, code size=36] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_HasAttachedDebugger(bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr x0, [fp, #0x18] ldr w1, [fp, #0x14] strb w1, [x0, #0x38] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 36 196: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_HasAttachedDebugger(bool) [Tier0, IL size=8, code size=36] ; Assembly listing for method BenchmarkDotNet.Engines.GcStats:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x0, [x1] stp xzr, xzr, [fp, #0x10] stp xzr, xzr, [fp, #0x20] add x0, fp, #16 mov w1, wzr mov w2, wzr mov w3, wzr mov x4, xzr mov x5, xzr movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldp q16, q17, [fp, #0x10] stp q16, q17, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 124 197: JIT compiled BenchmarkDotNet.Engines.GcStats:.cctor() [Tier0, IL size=28, code size=124] ; Assembly listing for method BenchmarkDotNet.Engines.GcStats:CalculateAllocationQuantumSize():long ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x28] str wzr, [fp, #0x24] str xzr, [fp, #0x18] G_M000_IG02: str wzr, [fp, #0x24] mov w0, #0xD1FFAB1E str w0, [fp, #0x10] G_M000_IG03: ldr w0, [fp, #0x10] sub w0, w0, #1 str w0, [fp, #0x10] ldr w0, [fp, #0x10] cmp w0, #0 bgt G_M000_IG05 G_M000_IG04: add x0, fp, #16 mov w1, #2 bl CORINFO_HELP_PATCHPOINT G_M000_IG05: ldr w0, [fp, #0x24] add w0, w0, #1 str w0, [fp, #0x20] ldr w0, [fp, #0x24] add w0, w0, #1 str w0, [fp, #0x24] ldr w0, [fp, #0x20] cmp w0, #10 ble G_M000_IG06 mov x0, #0xD1FFAB1E str x0, [fp, #0x28] b G_M000_IG07 G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 mov w0, wzr movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov w0, wzr movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x28] sub x0, x0, x1 str x0, [fp, #0x28] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x28] cmp x0, #0 ble G_M000_IG03 G_M000_IG07: ldr x0, [fp, #0x28] G_M000_IG08: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 332 198: JIT compiled BenchmarkDotNet.Engines.GcStats:CalculateAllocationQuantumSize() [Tier0, IL size=68, code size=332] ; Assembly listing for method BenchmarkDotNet.Engines.GcStats:.ctor(int,int,int,long,long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str w1, [fp, #0x34] str w2, [fp, #0x30] str w3, [fp, #0x2C] str x4, [fp, #0x20] str x5, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x38] ldr w1, [fp, #0x34] str w1, [x0] ldr x0, [fp, #0x38] ldr w1, [fp, #0x30] str w1, [x0, #0x04] ldr x0, [fp, #0x38] ldr w1, [fp, #0x2C] str w1, [x0, #0x08] ldr x0, [fp, #0x38] ldr x1, [fp, #0x20] str x1, [x0, #0x10] ldr x0, [fp, #0x38] ldr x1, [fp, #0x18] str x1, [x0, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 100 199: JIT compiled BenchmarkDotNet.Engines.GcStats:.ctor(int,int,int,long,long) [Tier0, IL size=38, code size=100] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_GCAllocationQuantum(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] str x1, [x0, #0x30] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 36 200: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_GCAllocationQuantum(long) [Tier0, IL size=8, code size=36] ; Assembly listing for method BenchmarkDotNet.Portability.RuntimeInformation:get_IsRunningInContainer():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 92 201: JIT compiled BenchmarkDotNet.Portability.RuntimeInformation:get_IsRunningInContainer() [Tier0, IL size=21, code size=92] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_InDocker(bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr x0, [fp, #0x18] ldr w1, [fp, #0x14] strb w1, [x0, #0x3C] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 36 202: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:set_InDocker(bool) [Tier0, IL size=8, code size=36] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:ToFormattedString():System.Collections.Generic.IEnumerable`1[System.String]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] movn w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x10] add x14, x14, #16 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 92 203: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:ToFormattedString() [Tier0, IL size=15, code size=92] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+d__49:.ctor(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x18] ldr w1, [fp, #0x14] str w1, [x0, #0x18] bl System.Environment:get_CurrentManagedThreadId():int ldr x1, [fp, #0x18] str w0, [x1, #0x1C] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 72 204: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+d__49:.ctor(int) [Tier0, IL size=25, code size=72] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+d__49:System.Collections.Generic.IEnumerable.GetEnumerator():System.Collections.Generic.IEnumerator`1[System.String]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] ldr w0, [x0, #0x18] cmn w0, #2 bne G_M000_IG03 ldr x0, [fp, #0x28] ldr w0, [x0, #0x1C] str w0, [fp, #0x14] bl System.Environment:get_CurrentManagedThreadId():int ldr w1, [fp, #0x14] cmp w0, w1 bne G_M000_IG03 ldr x0, [fp, #0x28] str wzr, [x0, #0x18] ldr x0, [fp, #0x28] str x0, [fp, #0x20] b G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] mov w1, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x18] str x14, [fp, #0x20] ldr x14, [fp, #0x28] ldr x15, [x14, #0x10] ldr x14, [fp, #0x20] add x14, x14, #16 bl CORINFO_HELP_ASSIGN_REF G_M000_IG04: ldr x0, [fp, #0x20] G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 172 205: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+d__49:System.Collections.Generic.IEnumerable.GetEnumerator() [Tier0, IL size=55, code size=172] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+d__49:MoveNext():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str xzr, [x9, #0x30] str x0, [fp, #0x48] G_M000_IG02: ldr x0, [fp, #0x48] ldr w0, [x0, #0x18] str w0, [fp, #0x44] ldr x0, [fp, #0x48] ldr x0, [x0, #0x10] str x0, [fp, #0x38] ldr w0, [fp, #0x44] cmp w0, #4 bhi G_M000_IG03 ldr w0, [fp, #0x44] mov w0, w0 adr x1, [@RWD00] ldr w1, [x1, x0, LSL #2] adr x2, [G_M000_IG02] add x1, x1, x2 br x1 G_M000_IG03: b G_M000_IG11 G_M000_IG04: ldr x0, [fp, #0x48] movn w1, #0 str w1, [x0, #0x18] ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x48] mov w1, #1 str w1, [x0, #0x18] b G_M000_IG08 G_M000_IG05: ldr x0, [fp, #0x48] movn w1, #0 str w1, [x0, #0x18] ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x20] ldr x1, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x48] add x14, x14, #8 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x48] mov w1, #2 str w1, [x0, #0x18] b G_M000_IG08 G_M000_IG06: ldr x0, [fp, #0x48] movn w1, #0 str w1, [x0, #0x18] ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x28] ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x3, [fp, #0x18] ldr x1, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x14, [fp, #0x48] add x14, x14, #8 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x48] mov w1, #3 str w1, [x0, #0x18] b G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x48] movn w1, #0 str w1, [x0, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x10] ldr x3, [fp, #0x10] ldr x1, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x14, [fp, #0x48] add x14, x14, #8 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x48] mov w1, #4 str w1, [x0, #0x18] b G_M000_IG08 G_M000_IG08: mov w0, #1 G_M000_IG09: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG10: ldr x0, [fp, #0x48] movn w1, #0 str w1, [x0, #0x18] b G_M000_IG11 G_M000_IG11: mov w0, wzr G_M000_IG12: ldp fp, lr, [sp], #0x50 ret lr RWD00 dd G_M000_IG04 - G_M000_IG02 dd G_M000_IG05 - G_M000_IG02 dd G_M000_IG06 - G_M000_IG02 dd G_M000_IG07 - G_M000_IG02 dd G_M000_IG10 - G_M000_IG02 ; Total bytes of code 612 206: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+d__49:MoveNext() [Tier0, IL size=217, code size=612] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+d__49:System.Collections.Generic.IEnumerator.get_Current():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 207: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+d__49:System.Collections.Generic.IEnumerator.get_Current() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:GetRuntimeInfo():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xC0]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] stp q16, q16, [x9, #0x80] str x0, [fp, #0xB8] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, #4 bl CORINFO_HELP_NEWARR_1_OBJ str x0, [fp, #0x80] ldr x0, [fp, #0xB8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x50] ldr x2, [fp, #0x50] ldr x0, [fp, #0x80] mov x1, xzr bl CORINFO_HELP_ARRADDR_ST ldr x0, [fp, #0xB8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x48] ldr x2, [fp, #0x48] ldr x0, [fp, #0x80] mov x1, #1 bl CORINFO_HELP_ARRADDR_ST ldr x0, [fp, #0xB8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x40] ldr x2, [fp, #0x40] ldr x0, [fp, #0x80] mov x1, #2 bl CORINFO_HELP_ARRADDR_ST ldr x0, [fp, #0xB8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x38] ldr x2, [fp, #0x38] ldr x0, [fp, #0x80] mov x1, #3 bl CORINFO_HELP_ARRADDR_ST movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x78] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x70] ldr x0, [fp, #0x80] str x0, [fp, #0x68] ldr x0, [fp, #0x78] str x0, [fp, #0x60] ldr x0, [fp, #0x78] cbnz x0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x30] ldr x1, [fp, #0x30] ldr x0, [fp, #0x58] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x58] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x2, [fp, #0x58] str x2, [fp, #0x60] G_M000_IG03: ldr x2, [fp, #0x60] ldr x1, [fp, #0x68] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x28] ldr x1, [fp, #0x28] ldr x0, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xB0] add x0, fp, #136 mov w1, #3 mov w2, #3 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xB8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x20] ldr x1, [fp, #0x20] add x0, fp, #136 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #136 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xB8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] add x0, fp, #136 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #136 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #136 ldr x1, [fp, #0xB0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #136 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldp fp, lr, [sp], #0xC0 ret lr ; Total bytes of code 820 208: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:GetRuntimeInfo() [Tier0, IL size=164, code size=820] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:get_JitInfo():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 209: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:get_JitInfo() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:get_HardwareIntrinsicsShort():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x28] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 210: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:get_HardwareIntrinsicsShort() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:GetConfigurationFlag():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG04 ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG04 ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: movz x0, #8 movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 208 211: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:GetConfigurationFlag() [Tier0, IL size=49, code size=208] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:get_Configuration():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 212: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:get_Configuration() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:GetDebuggerFlag():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG04 movz x0, #8 movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 80 213: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:GetDebuggerFlag() [Tier0, IL size=20, code size=80] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:get_HasAttachedDebugger():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldrb w0, [x0, #0x38] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 214: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:get_HasAttachedDebugger() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+<>c:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 215: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+<>c:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+<>c:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 216: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+<>c:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Linq.Enumerable:Where[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,bool]):System.Collections.Generic.IEnumerable`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xC0]! mov fp, sp add x9, fp, #40 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp xzr, xzr, [x9, #0x60] str xzr, [x9, #0x70] str x0, [fp, #0xB8] str x0, [fp, #0xB0] str x1, [fp, #0xA8] str x2, [fp, #0xA0] G_M000_IG02: ldr x0, [fp, #0xA8] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0xA0] cbnz x0, G_M000_IG04 mov w0, #12 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldr x0, [fp, #0xB0] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0xB0] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x78] b G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0xB0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x78] G_M000_IG07: ldr x0, [fp, #0x78] ldr x1, [fp, #0xA8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x98] ldr x0, [fp, #0x98] cbz x0, G_M000_IG08 ldr x0, [fp, #0x98] ldr x1, [fp, #0xA0] ldr x2, [fp, #0x98] ldr x2, [x2] ldr x2, [x2, #0x48] ldr x2, [x2, #0x10] blr x2 str x0, [fp, #0x28] b G_M000_IG33 G_M000_IG08: ldr x0, [fp, #0xB0] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] cbz x0, G_M000_IG10 G_M000_IG09: ldr x0, [fp, #0xB0] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] str x0, [fp, #0x70] b G_M000_IG11 G_M000_IG10: ldr x0, [fp, #0xB0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x70] G_M000_IG11: ldr x0, [fp, #0x70] ldr x1, [fp, #0xA8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x90] ldr x0, [fp, #0x90] cbz x0, G_M000_IG21 ldr x0, [fp, #0x90] ldr w0, [x0, #0x08] cbz w0, G_M000_IG16 ldr x0, [fp, #0xB0] ldr x0, [x0, #0x10] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x0, [x0, #0x08] cmp x0, #64 ble G_M000_IG14 G_M000_IG12: ldr x0, [fp, #0x20] ldr x0, [x0, #0x40] cbz x0, G_M000_IG14 G_M000_IG13: ldr x0, [fp, #0x20] ldr x0, [x0, #0x40] str x0, [fp, #0x30] b G_M000_IG15 G_M000_IG14: ldr x0, [fp, #0xB0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x30] G_M000_IG15: ldr x0, [fp, #0x30] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] ldr x0, [fp, #0x38] ldr x1, [fp, #0x90] ldr x2, [fp, #0xA0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x38] str x0, [fp, #0x80] ldr x0, [fp, #0x80] str x0, [fp, #0x28] b G_M000_IG33 G_M000_IG16: ldr x0, [fp, #0xB0] ldr x0, [x0, #0x10] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] cmp x0, #56 ble G_M000_IG19 G_M000_IG17: ldr x0, [fp, #0x18] ldr x0, [x0, #0x38] cbz x0, G_M000_IG19 G_M000_IG18: ldr x0, [fp, #0x18] ldr x0, [x0, #0x38] str x0, [fp, #0x40] b G_M000_IG20 G_M000_IG19: ldr x0, [fp, #0xB0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x40] G_M000_IG20: ldr x0, [fp, #0x40] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x28] b G_M000_IG33 G_M000_IG21: ldr x0, [fp, #0xB0] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] cbz x0, G_M000_IG23 G_M000_IG22: ldr x0, [fp, #0xB0] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] str x0, [fp, #0x68] b G_M000_IG24 G_M000_IG23: ldr x0, [fp, #0xB0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x68] G_M000_IG24: ldr x0, [fp, #0x68] ldr x1, [fp, #0xA8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x88] ldr x0, [fp, #0x88] cbz x0, G_M000_IG29 ldr x0, [fp, #0xB0] ldr x0, [x0, #0x10] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x08] cmp x0, #48 ble G_M000_IG27 G_M000_IG25: ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] cbz x0, G_M000_IG27 G_M000_IG26: ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] str x0, [fp, #0x48] b G_M000_IG28 G_M000_IG27: ldr x0, [fp, #0xB0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x48] G_M000_IG28: ldr x0, [fp, #0x48] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x50] ldr x0, [fp, #0x50] ldr x1, [fp, #0x88] ldr x2, [fp, #0xA0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x50] str x0, [fp, #0x28] b G_M000_IG33 G_M000_IG29: ldr x0, [fp, #0xB0] ldr x0, [x0, #0x10] ldr x0, [x0, #0x28] cbz x0, G_M000_IG31 G_M000_IG30: ldr x0, [fp, #0xB0] ldr x0, [x0, #0x10] ldr x0, [x0, #0x28] str x0, [fp, #0x58] b G_M000_IG32 G_M000_IG31: ldr x0, [fp, #0xB0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x58] G_M000_IG32: ldr x0, [fp, #0x58] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x60] ldr x0, [fp, #0x60] ldr x1, [fp, #0xA8] ldr x2, [fp, #0xA0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x60] str x0, [fp, #0x28] b G_M000_IG33 G_M000_IG33: ldr x0, [fp, #0x28] G_M000_IG34: ldp fp, lr, [sp], #0xC0 ret lr ; Total bytes of code 984 217: JIT compiled System.Linq.Enumerable:Where[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,bool]) [Tier0, IL size=94, code size=984] ; Assembly listing for method System.Linq.Enumerable+WhereArrayIterator`1[System.__Canon]:.ctor(System.__Canon[],System.Func`2[System.__Canon,bool]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] add x14, x14, #24 ldr x15, [fp, #0x20] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x28] add x14, x14, #32 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 218: JIT compiled System.Linq.Enumerable+WhereArrayIterator`1[System.__Canon]:.ctor(System.__Canon[],System.Func`2[System.__Canon,bool]) [Tier0, IL size=21, code size=84] ; Assembly listing for method System.Linq.Enumerable+Iterator`1[System.__Canon]:GetEnumerator():System.Collections.Generic.IEnumerator`1[System.__Canon]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] ldr w0, [x0, #0x14] cbnz w0, G_M000_IG03 ldr x0, [fp, #0x28] ldr w0, [x0, #0x10] str w0, [fp, #0x14] bl System.Environment:get_CurrentManagedThreadId():int ldr w1, [fp, #0x14] cmp w0, w1 beq G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x28] ldr x1, [fp, #0x28] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x28] blr x1 str x0, [fp, #0x18] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x28] str x0, [fp, #0x18] G_M000_IG05: ldr x0, [fp, #0x18] str x0, [fp, #0x20] ldr x0, [fp, #0x20] mov w1, #1 str w1, [x0, #0x14] ldr x0, [fp, #0x20] G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 132 219: JIT compiled System.Linq.Enumerable+Iterator`1[System.__Canon]:GetEnumerator() [Tier0, IL size=40, code size=132] ; Assembly listing for method System.Linq.Enumerable+WhereArrayIterator`1[System.__Canon]:MoveNext():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x10] str x0, [fp, #0x48] str x0, [fp, #0x40] G_M000_IG02: ldr x0, [fp, #0x40] ldr w0, [x0, #0x14] sub w0, w0, #1 str w0, [fp, #0x3C] ldr x0, [fp, #0x40] ldr x0, [x0, #0x18] str x0, [fp, #0x30] mov w0, #0xD1FFAB1E str w0, [fp, #0x18] b G_M000_IG05 G_M000_IG03: ldr x0, [fp, #0x30] ldr w1, [fp, #0x3C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG09 add x0, x0, x1, LSL #3 add x0, x0, #16 ldr x0, [x0] str x0, [fp, #0x28] ldr x0, [fp, #0x40] ldr w0, [x0, #0x14] str w0, [fp, #0x24] ldr w0, [fp, #0x24] add w0, w0, #1 ldr x1, [fp, #0x40] str w0, [x1, #0x14] ldr w0, [fp, #0x24] str w0, [fp, #0x3C] ldr x0, [fp, #0x40] ldr x0, [x0, #0x20] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x08] ldr x1, [fp, #0x28] ldr x2, [fp, #0x10] ldr x2, [x2, #0x18] blr x2 cbz w0, G_M000_IG05 ldr x14, [fp, #0x40] add x14, x14, #8 ldr x15, [fp, #0x28] bl CORINFO_HELP_ASSIGN_REF mov w0, #1 G_M000_IG04: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG05: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG07 G_M000_IG06: add x0, fp, #24 mov w1, #67 bl CORINFO_HELP_PATCHPOINT G_M000_IG07: ldr w0, [fp, #0x3C] ldr x1, [fp, #0x30] ldr w1, [x1, #0x08] cmp w0, w1 blo G_M000_IG03 ldr x0, [fp, #0x40] ldr x1, [fp, #0x40] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x30] blr x1 mov w0, wzr G_M000_IG08: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG09: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 308 220: JIT compiled System.Linq.Enumerable+WhereArrayIterator`1[System.__Canon]:MoveNext() [Tier0, IL size=81, code size=308] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+<>c:b__54_0(System.String):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x10] movz x1, #8 movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 60 221: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+<>c:b__54_0(System.String) [Tier0, IL size=12, code size=60] ; Assembly listing for method System.Linq.Enumerable+Iterator`1[System.__Canon]:get_Current():System.__Canon:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 222: JIT compiled System.Linq.Enumerable+Iterator`1[System.__Canon]:get_Current() [Tier0, IL size=7, code size=28] ; Assembly listing for method System.Linq.Enumerable+Iterator`1[System.__Canon]:Dispose():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] str xzr, [x0, #0x08] ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x14] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 223: JIT compiled System.Linq.Enumerable+Iterator`1[System.__Canon]:Dispose() [Tier0, IL size=20, code size=40] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:get_RuntimeVersion():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 224: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:get_RuntimeVersion() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:get_Architecture():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 225: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:get_Architecture() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:GetGcConcurrentFlag():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 80 226: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:GetGcConcurrentFlag() [Tier0, IL size=20, code size=80] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:get_IsConcurrentGC():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldrb w0, [x0, #0x3B] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 227: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:get_IsConcurrentGC() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:GetGcServerFlag():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 80 228: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:GetGcServerFlag() [Tier0, IL size=20, code size=80] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:get_IsServerGC():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldrb w0, [x0, #0x3A] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 229: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:get_IsServerGC() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:GetFullInfo(int):System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str w0, [fp, #0x1C] G_M000_IG02: ldr w0, [fp, #0x1C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x1, [fp, #0x10] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 88 230: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:GetFullInfo(int) [Tier0, IL size=17, code size=88] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:g__GetCurrentProcessInstructionSets|2_0(int):System.Collections.Generic.IEnumerable`1[System.String] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str w0, [fp, #0x1C] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] movn w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x10] ldr w1, [fp, #0x1C] str w1, [x0, #0x1C] ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 88 231: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:g__GetCurrentProcessInstructionSets|2_0(int) [Tier0, IL size=15, code size=88] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics+<g__GetCurrentProcessInstructionSets|2_0>d:.ctor(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x18] ldr w1, [fp, #0x14] str w1, [x0, #0x10] bl System.Environment:get_CurrentManagedThreadId():int ldr x1, [fp, #0x18] str w0, [x1, #0x14] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 72 232: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics+<g__GetCurrentProcessInstructionSets|2_0>d:.ctor(int) [Tier0, IL size=25, code size=72] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics+<g__GetCurrentProcessInstructionSets|2_0>d:System.Collections.Generic.IEnumerable.GetEnumerator():System.Collections.Generic.IEnumerator`1[System.String]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] ldr w0, [x0, #0x10] cmn w0, #2 bne G_M000_IG03 ldr x0, [fp, #0x28] ldr w0, [x0, #0x14] str w0, [fp, #0x14] bl System.Environment:get_CurrentManagedThreadId():int ldr w1, [fp, #0x14] cmp w0, w1 bne G_M000_IG03 ldr x0, [fp, #0x28] str wzr, [x0, #0x10] ldr x0, [fp, #0x28] str x0, [fp, #0x20] b G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] mov w1, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x18] str x0, [fp, #0x20] G_M000_IG04: ldr x0, [fp, #0x28] ldr w0, [x0, #0x1C] ldr x1, [fp, #0x20] str w0, [x1, #0x18] ldr x0, [fp, #0x20] G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 168 233: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics+<g__GetCurrentProcessInstructionSets|2_0>d:System.Collections.Generic.IEnumerable.GetEnumerator() [Tier0, IL size=55, code size=168] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics+<g__GetCurrentProcessInstructionSets|2_0>d:MoveNext():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str wzr, [fp, #0x14] str wzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x10] str w0, [fp, #0x14] ldr w0, [fp, #0x14] cmp w0, #26 bhi G_M000_IG03 ldr w0, [fp, #0x14] mov w0, w0 adr x1, [@RWD00] ldr w1, [x1, x0, LSL #2] adr x2, [G_M000_IG02] add x1, x1, x2 br x1 G_M000_IG03: b G_M000_IG61 G_M000_IG04: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] ldr x0, [fp, #0x18] ldr w0, [x0, #0x18] str w0, [fp, #0x10] ldr w0, [fp, #0x10] sub w0, w0, #1 cmp w0, #1 bls G_M000_IG05 ldr w0, [fp, #0x10] cmp w0, #4 beq G_M000_IG41 b G_M000_IG59 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG07 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #1 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG06: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] b G_M000_IG23 G_M000_IG07: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG09 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #2 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG08: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] b G_M000_IG23 G_M000_IG09: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG11 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #3 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG10: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] b G_M000_IG23 G_M000_IG11: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG13 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #4 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG12: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] b G_M000_IG23 G_M000_IG13: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG15 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #5 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG14: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] b G_M000_IG23 G_M000_IG15: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG17 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #6 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG16: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] b G_M000_IG23 G_M000_IG17: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG19 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #7 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG18: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] b G_M000_IG23 G_M000_IG19: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG21 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #8 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG20: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] b G_M000_IG23 G_M000_IG21: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG23 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #9 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG22: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] G_M000_IG23: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG25 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #10 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG24: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] G_M000_IG25: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG27 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #11 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG26: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] G_M000_IG27: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG29 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #12 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG28: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] G_M000_IG29: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG31 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #13 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG30: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] G_M000_IG31: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG33 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #14 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG32: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] G_M000_IG33: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG35 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #15 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG34: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] G_M000_IG35: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG37 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #16 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG36: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] G_M000_IG37: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG39 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #17 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG38: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] G_M000_IG39: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG60 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #18 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG40: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] b G_M000_IG60 G_M000_IG41: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG43 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #19 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG42: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] b G_M000_IG45 G_M000_IG43: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG45 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #20 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG44: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] G_M000_IG45: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG47 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #21 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG46: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] G_M000_IG47: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG49 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #22 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG48: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] G_M000_IG49: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG51 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #23 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG50: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] G_M000_IG51: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG53 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #24 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG52: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] G_M000_IG53: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG55 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #25 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG54: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] G_M000_IG55: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG60 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x1, [x0, #0x08] ldr x0, [fp, #0x18] mov w1, #26 str w1, [x0, #0x10] b G_M000_IG56 G_M000_IG56: mov w0, #1 G_M000_IG57: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG58: ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] b G_M000_IG60 G_M000_IG59: b G_M000_IG61 G_M000_IG60: b G_M000_IG61 G_M000_IG61: mov w0, wzr G_M000_IG62: ldp fp, lr, [sp], #0x20 ret lr RWD00 dd G_M000_IG04 - G_M000_IG02 dd G_M000_IG06 - G_M000_IG02 dd G_M000_IG08 - G_M000_IG02 dd G_M000_IG10 - G_M000_IG02 dd G_M000_IG12 - G_M000_IG02 dd G_M000_IG14 - G_M000_IG02 dd G_M000_IG16 - G_M000_IG02 dd G_M000_IG18 - G_M000_IG02 dd G_M000_IG20 - G_M000_IG02 dd G_M000_IG22 - G_M000_IG02 dd G_M000_IG24 - G_M000_IG02 dd G_M000_IG26 - G_M000_IG02 dd G_M000_IG28 - G_M000_IG02 dd G_M000_IG30 - G_M000_IG02 dd G_M000_IG32 - G_M000_IG02 dd G_M000_IG34 - G_M000_IG02 dd G_M000_IG36 - G_M000_IG02 dd G_M000_IG38 - G_M000_IG02 dd G_M000_IG40 - G_M000_IG02 dd G_M000_IG42 - G_M000_IG02 dd G_M000_IG44 - G_M000_IG02 dd G_M000_IG46 - G_M000_IG02 dd G_M000_IG48 - G_M000_IG02 dd G_M000_IG50 - G_M000_IG02 dd G_M000_IG52 - G_M000_IG02 dd G_M000_IG54 - G_M000_IG02 dd G_M000_IG58 - G_M000_IG02 ; Total bytes of code 2080 234: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics+<g__GetCurrentProcessInstructionSets|2_0>d:MoveNext() [Tier0, IL size=1104, code size=2080] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics+<g__GetCurrentProcessInstructionSets|2_0>d:System.Collections.Generic.IEnumerator.get_Current():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 235: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics+<g__GetCurrentProcessInstructionSets|2_0>d:System.Collections.Generic.IEnumerator.get_Current() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsArmAesSupported():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, #1 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 236: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsArmAesSupported() [Tier0, IL size=6, code size=20] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsArmCrc32Supported():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, #1 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 237: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsArmCrc32Supported() [Tier0, IL size=6, code size=20] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsArmDpSupported():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 238: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsArmDpSupported() [Tier0, IL size=6, code size=20] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsArmRdmSupported():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 239: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsArmRdmSupported() [Tier0, IL size=6, code size=20] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsArmSha1Supported():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, #1 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 240: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsArmSha1Supported() [Tier0, IL size=6, code size=20] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsArmSha256Supported():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, #1 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 241: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:get_IsArmSha256Supported() [Tier0, IL size=6, code size=20] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics+<g__GetCurrentProcessInstructionSets|2_0>d:System.IDisposable.Dispose():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 20 242: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics+<g__GetCurrentProcessInstructionSets|2_0>d:System.IDisposable.Dispose() [Tier0, IL size=1, code size=20] ; Assembly listing for method BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:GetVectorSize():System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] G_M000_IG02: b G_M000_IG03 G_M000_IG03: add x0, fp, #24 mov w1, #11 mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x0, fp, #24 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #24 mov w1, #8 lsl w1, w1, #4 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #24 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 160 243: JIT compiled BenchmarkDotNet.Portability.Cpu.HardwareIntrinsics:GetVectorSize() [Tier0, IL size=57, code size=160] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+d__49:System.IDisposable.Dispose():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 20 244: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+d__49:System.IDisposable.Dispose() [Tier0, IL size=1, code size=20] ; Assembly listing for method BenchmarkDotNet.Jobs.Job:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 48 245: JIT compiled BenchmarkDotNet.Jobs.Job:.ctor() [Tier0, IL size=8, code size=48] ; Assembly listing for method BenchmarkDotNet.Jobs.Job:.ctor(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str x0, [fp, #0x68] str x1, [fp, #0x60] G_M000_IG02: ldr x0, [fp, #0x68] ldr x1, [fp, #0x60] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x50] ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x50] ldr x1, [fp, #0x68] ldr x2, [fp, #0x58] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x40] ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x40] ldr x1, [fp, #0x68] ldr x2, [fp, #0x48] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x30] ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x30] ldr x1, [fp, #0x68] ldr x2, [fp, #0x38] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x20] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x20] ldr x1, [fp, #0x68] ldr x2, [fp, #0x28] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x10] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x10] ldr x1, [fp, #0x68] ldr x2, [fp, #0x18] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 672 246: JIT compiled BenchmarkDotNet.Jobs.Job:.ctor(System.String) [Tier0, IL size=88, code size=672] ; Assembly listing for method BenchmarkDotNet.Jobs.JobMode`1[System.__Canon]:.ctor(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 52 247: JIT compiled BenchmarkDotNet.Jobs.JobMode`1[System.__Canon]:.ctor(System.String) [Tier0, IL size=8, code size=52] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:.ctor(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 52 248: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:.ctor(System.String) [Tier0, IL size=8, code size=52] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:.ctor(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 156 249: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:.ctor(System.String) [Tier0, IL size=27, code size=156] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x18] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x18] add x14, x14, #8 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 136 250: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:.ctor() [Tier0, IL size=25, code size=136] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:set_Owner(BenchmarkDotNet.Characteristics.CharacteristicObject):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #16 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 251: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:set_Owner(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Jobs.Job:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xC0]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] stp q16, q16, [x9, #0x80] stp xzr, xzr, [x9, #0xA0] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xB8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] str x2, [fp, #0x60] ldr x2, [fp, #0x60] ldr x0, [fp, #0xB8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xB8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xB0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] str x2, [fp, #0x58] ldr x2, [fp, #0x58] ldr x0, [fp, #0xB0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xB0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xA8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] str x2, [fp, #0x50] ldr x2, [fp, #0x50] ldr x0, [fp, #0xA8] G_M000_IG03: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xA0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] str x2, [fp, #0x48] ldr x2, [fp, #0x48] ldr x0, [fp, #0xA0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xA0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x98] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] str x2, [fp, #0x40] ldr x2, [fp, #0x40] ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x90] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] str x2, [fp, #0x38] ldr x2, [fp, #0x38] ldr x0, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x88] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] str x2, [fp, #0x30] ldr x2, [fp, #0x30] ldr x0, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x80] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE G_M000_IG04: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] str x2, [fp, #0x28] ldr x2, [fp, #0x28] ldr x0, [fp, #0x80] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x80] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x78] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] str x2, [fp, #0x20] ldr x2, [fp, #0x20] ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x70] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] str x2, [fp, #0x18] ldr x2, [fp, #0x18] ldr x0, [fp, #0x70] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x15, [fp, #0x70] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x68] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] str x2, [fp, #0x10] ldr x2, [fp, #0x10] ldr x0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x15, [fp, #0x68] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG05: ldp fp, lr, [sp], #0xC0 ret lr ; Total bytes of code 1904 252: JIT compiled BenchmarkDotNet.Jobs.Job:.cctor() [Tier0, IL size=341, code size=1904] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[System.__Canon](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x0, [fp, #0x20] str x1, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 116 253: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[System.__Canon](System.String) [Tier0, IL size=7, code size=116] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,System.__Canon](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str x0, [fp, #0x48] str x0, [fp, #0x40] str x1, [fp, #0x38] G_M000_IG02: ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] ldr x0, [x0] bl CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE str x0, [fp, #0x28] str xzr, [fp, #0x30] ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] str x0, [fp, #0x18] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x40] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x18] G_M000_IG05: ldr x0, [fp, #0x18] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x38] ldr x2, [fp, #0x28] ldr x4, [fp, #0x30] mov x3, xzr mov w5, wzr mov w6, wzr movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x0, [fp, #0x20] G_M000_IG06: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 188 254: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,System.__Canon](System.String) [Tier0, IL size=29, code size=188] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon]:.ctor(System.String,System.Type,System.Func`3[System.__Canon,System.__Canon,System.__Canon],System.__Canon,bool,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x48] str x0, [fp, #0x40] str x1, [fp, #0x38] str x2, [fp, #0x30] str x3, [fp, #0x28] str x4, [fp, #0x20] str w5, [fp, #0x1C] str w6, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x40] ldr x0, [x0] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0] bl CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE str x0, [fp, #0x10] ldr x2, [fp, #0x10] ldr w5, [fp, #0x1C] uxtb w5, w5 ldr w6, [fp, #0x18] uxtb w6, w6 ldr x1, [fp, #0x38] ldr x0, [fp, #0x40] ldr x3, [fp, #0x30] ldr x4, [fp, #0x20] movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x14, [fp, #0x40] add x14, x14, #48 ldr x15, [fp, #0x28] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x40] add x14, x14, #56 ldr x15, [fp, #0x20] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 168 255: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon]:.ctor(System.String,System.Type,System.Func`3[System.__Canon,System.__Canon,System.__Canon],System.__Canon,bool,bool) [Tier0, IL size=45, code size=168] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:.ctor(System.String,System.Type,System.Type,System.Object,bool,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x0, [fp, #0x68] str x1, [fp, #0x60] str x2, [fp, #0x58] str x3, [fp, #0x50] str x4, [fp, #0x48] str w5, [fp, #0x44] str w6, [fp, #0x40] G_M000_IG02: ldr x0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x28] bl CORINFO_HELP_THROW G_M000_IG04: ldr x14, [fp, #0x58] cbnz x14, G_M000_IG06 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x30] bl CORINFO_HELP_THROW G_M000_IG06: ldr x14, [fp, #0x50] cbnz x14, G_M000_IG08 G_M000_IG07: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x38] bl CORINFO_HELP_THROW G_M000_IG08: ldr x14, [fp, #0x68] add x14, x14, #8 ldr x15, [fp, #0x60] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x68] add x14, x14, #16 ldr x15, [fp, #0x58] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x68] add x14, x14, #24 ldr x15, [fp, #0x50] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x68] add x14, x14, #32 ldr x15, [fp, #0x48] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x68] ldr w1, [fp, #0x44] strb w1, [x0, #0x28] ldr x0, [fp, #0x68] ldr w1, [fp, #0x40] strb w1, [x0, #0x29] G_M000_IG09: ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 468 256: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:.ctor(System.String,System.Type,System.Type,System.Object,bool,bool) [Tier0, IL size=111, code size=468] ; Assembly listing for method BenchmarkDotNet.Jobs.EnvironmentMode:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 mov w2, #1 mov w3, #1 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 mov w2, #1 mov w3, #2 movz x4, #0xD1FFAB1E G_M000_IG03: movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 mov w2, #2 mov w3, #2 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 mov w2, #2 mov w3, #1 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG04: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 976 257: JIT compiled BenchmarkDotNet.Jobs.EnvironmentMode:.cctor() [Tier0, IL size=209, code size=976] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[int](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[int] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x0, [fp, #0x20] str x1, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 116 258: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[int](System.String) [Tier0, IL size=7, code size=116] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,int](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[int] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str wzr, [fp, #0x24] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0] bl CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE str x0, [fp, #0x18] str wzr, [fp, #0x24] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x1, [fp, #0x28] ldr x2, [fp, #0x18] ldr w4, [fp, #0x24] mov x3, xzr mov w5, wzr mov w6, wzr movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 136 259: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,int](System.String) [Tier0, IL size=29, code size=136] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[int]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,int,int],int,bool,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] str x3, [fp, #0x30] str w4, [fp, #0x2C] str w5, [fp, #0x28] str w6, [fp, #0x24] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 str x4, [fp, #0x10] ldr x4, [fp, #0x18] ldr w6, [fp, #0x2C] str w6, [x4, #0x08] ldr x4, [fp, #0x18] ldr w6, [fp, #0x24] uxtb w6, w6 ldr w5, [fp, #0x28] uxtb w5, w5 ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x10] ldr x3, [fp, #0x38] movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x14, [fp, #0x48] add x14, x14, #48 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x48] ldr w1, [fp, #0x2C] str w1, [x0, #0x38] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 184 260: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[int]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,int,int],int,bool,bool) [Tier0, IL size=45, code size=184] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[int](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[int] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x0, [fp, #0x20] str x1, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 116 261: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[int](System.String) [Tier0, IL size=7, code size=116] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,int](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[int] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str wzr, [fp, #0x24] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0] bl CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE str x0, [fp, #0x18] str wzr, [fp, #0x24] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x1, [fp, #0x28] ldr x2, [fp, #0x18] ldr w4, [fp, #0x24] mov x3, xzr mov w5, wzr mov w6, wzr movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 136 262: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,int](System.String) [Tier0, IL size=29, code size=136] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[int]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,int,int],int,bool,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] str x3, [fp, #0x30] str w4, [fp, #0x2C] str w5, [fp, #0x28] str w6, [fp, #0x24] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 str x4, [fp, #0x10] ldr x4, [fp, #0x18] ldr w6, [fp, #0x2C] str w6, [x4, #0x08] ldr x4, [fp, #0x18] ldr w6, [fp, #0x24] uxtb w6, w6 ldr w5, [fp, #0x28] uxtb w5, w5 ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x10] ldr x3, [fp, #0x38] movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x14, [fp, #0x48] add x14, x14, #48 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x48] ldr w1, [fp, #0x2C] str w1, [x0, #0x38] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 184 263: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[int]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,int,int],int,bool,bool) [Tier0, IL size=45, code size=184] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[long](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[long] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x0, [fp, #0x20] str x1, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 116 264: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[long](System.String) [Tier0, IL size=7, code size=116] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,long](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[long] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0] bl CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE str x0, [fp, #0x18] str xzr, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x1, [fp, #0x28] ldr x2, [fp, #0x18] ldr x4, [fp, #0x20] mov x3, xzr mov w5, wzr mov w6, wzr movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 136 265: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,long](System.String) [Tier0, IL size=29, code size=136] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[long]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,long,long],long,bool,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] str x3, [fp, #0x30] str x4, [fp, #0x28] str w5, [fp, #0x24] str w6, [fp, #0x20] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 str x4, [fp, #0x10] ldr x4, [fp, #0x18] ldr x6, [fp, #0x28] str x6, [x4, #0x08] ldr x4, [fp, #0x18] ldr w6, [fp, #0x20] uxtb w6, w6 ldr w5, [fp, #0x24] uxtb w5, w5 ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x10] ldr x3, [fp, #0x38] movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x14, [fp, #0x48] add x14, x14, #48 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x48] ldr x1, [fp, #0x28] str x1, [x0, #0x38] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 184 266: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[long]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,long,long],long,bool,bool) [Tier0, IL size=45, code size=184] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[System.Nullable`1[System.Guid]](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[System.Nullable`1[System.Guid]] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x0, [fp, #0x20] str x1, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 116 267: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[System.Nullable`1[System.Guid]](System.String) [Tier0, IL size=7, code size=116] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,System.Nullable`1[System.Guid]](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[System.Nullable`1[System.Guid]] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str xzr, [x9, #0x50] str x0, [fp, #0x78] str x0, [fp, #0x70] str x1, [fp, #0x68] G_M000_IG02: ldr x0, [fp, #0x70] ldr x0, [x0, #0x10] ldr x0, [x0] bl CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE str x0, [fp, #0x48] stp xzr, xzr, [fp, #0x50] str wzr, [fp, #0x60] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x40] ldr x0, [fp, #0x40] str x0, [fp, #0x20] ldr x0, [fp, #0x68] str x0, [fp, #0x18] ldr x0, [fp, #0x48] str x0, [fp, #0x10] ldp x0, x1, [fp, #0x50] stp x0, x1, [fp, #0x28] ldr w0, [fp, #0x60] str w0, [fp, #0x38] ldr x0, [fp, #0x20] ldr x1, [fp, #0x18] ldr x2, [fp, #0x10] add x4, fp, #40 mov x3, xzr mov w5, wzr mov w6, wzr movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x0, [fp, #0x40] G_M000_IG03: ldp fp, lr, [sp], #0x80 ret lr ; Total bytes of code 192 268: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,System.Nullable`1[System.Guid]](System.String) [Tier0, IL size=29, code size=192] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[System.Nullable`1[System.Guid]]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,System.Nullable`1[System.Guid],System.Nullable`1[System.Guid]],System.Nullable`1[System.Guid],bool,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] str x3, [fp, #0x30] str x4, [fp, #0x28] str w5, [fp, #0x24] str w6, [fp, #0x20] G_M000_IG02: ldr x1, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_BOX_NULLABLE str x0, [fp, #0x18] ldr x4, [fp, #0x18] ldr w5, [fp, #0x24] uxtb w5, w5 ldr w6, [fp, #0x20] uxtb w6, w6 ldr x1, [fp, #0x40] ldr x3, [fp, #0x38] ldr x0, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x14, [fp, #0x48] add x14, x14, #48 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x28] ldr x1, [fp, #0x48] ldp x2, x3, [x0] stp x2, x3, [x1, #0x38] ldr w2, [x0, #0x10] str w2, [x1, #0x48] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 176 269: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[System.Nullable`1[System.Guid]]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,System.Nullable`1[System.Guid],System.Nullable`1[System.Guid]],System.Nullable`1[System.Guid],bool,bool) [Tier0, IL size=45, code size=176] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[bool](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[bool] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x0, [fp, #0x20] str x1, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 116 270: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[bool](System.String) [Tier0, IL size=7, code size=116] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,bool](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[bool] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str wzr, [fp, #0x24] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0] bl CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE str x0, [fp, #0x18] str wzr, [fp, #0x24] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x1, [fp, #0x28] ldr x2, [fp, #0x18] ldr w4, [fp, #0x24] mov x3, xzr mov w5, wzr mov w6, wzr movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 136 271: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,bool](System.String) [Tier0, IL size=29, code size=136] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[bool]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,bool,bool],bool,bool,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] str x3, [fp, #0x30] str w4, [fp, #0x2C] str w5, [fp, #0x28] str w6, [fp, #0x24] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 str x4, [fp, #0x10] ldr x4, [fp, #0x18] ldr w6, [fp, #0x2C] strb w6, [x4, #0x08] ldr x4, [fp, #0x18] ldr w6, [fp, #0x24] uxtb w6, w6 ldr w5, [fp, #0x28] uxtb w5, w5 ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x10] ldr x3, [fp, #0x38] movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x14, [fp, #0x48] add x14, x14, #48 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x48] ldr w1, [fp, #0x2C] strb w1, [x0, #0x2A] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 184 272: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[bool]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,bool,bool],bool,bool,bool) [Tier0, IL size=45, code size=184] ; Assembly listing for method BenchmarkDotNet.Jobs.EnvironmentMode:.ctor(System.String,int,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] str w3, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x28] ldr w1, [fp, #0x1C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x28] ldr w1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 116 273: JIT compiled BenchmarkDotNet.Jobs.EnvironmentMode:.ctor(System.String,int,int) [Tier0, IL size=22, code size=116] ; Assembly listing for method BenchmarkDotNet.Jobs.EnvironmentMode:.ctor(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x10] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x10] ldr x1, [fp, #0x28] ldr x2, [fp, #0x18] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 180 274: JIT compiled BenchmarkDotNet.Jobs.EnvironmentMode:.ctor(System.String) [Tier0, IL size=24, code size=180] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x2, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 mov w4, #1 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 176 275: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:.cctor() [Tier0, IL size=34, code size=176] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,System.__Canon](System.String,System.Func`3[System.__Canon,System.__Canon,System.__Canon],System.__Canon,bool):BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x18] str x0, [fp, #0x58] str x0, [fp, #0x50] str x1, [fp, #0x48] str x2, [fp, #0x40] str x3, [fp, #0x38] str w4, [fp, #0x34] G_M000_IG02: ldr x0, [fp, #0x50] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x50] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] str x0, [fp, #0x20] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x20] G_M000_IG05: ldr x0, [fp, #0x20] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x50] ldr x0, [x0, #0x10] ldr x0, [x0] bl CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE str x0, [fp, #0x18] ldr x2, [fp, #0x18] ldr w5, [fp, #0x34] uxtb w5, w5 ldr x1, [fp, #0x48] ldr x0, [fp, #0x28] ldr x3, [fp, #0x40] ldr x4, [fp, #0x38] mov w6, wzr movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x0, [fp, #0x28] G_M000_IG06: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 196 276: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,System.__Canon](System.String,System.Func`3[System.__Canon,System.__Canon,System.__Canon],System.__Canon,bool) [Tier0, IL size=21, code size=196] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon]:set_Item(BenchmarkDotNet.Characteristics.CharacteristicObject,System.__Canon):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] str x2, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x10] str x0, [fp, #0x18] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x18] G_M000_IG05: ldr x0, [fp, #0x28] ldr x1, [fp, #0x18] ldr x2, [fp, #0x30] ldr x3, [fp, #0x20] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] ldr wzr, [x0] blr x4 G_M000_IG06: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 152 277: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon]:set_Item(BenchmarkDotNet.Characteristics.CharacteristicObject,System.__Canon) [Tier0, IL size=9, code size=152] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue[System.__Canon](BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon],System.__Canon):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] str x3, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x28] ldr x1, [fp, #0x18] ldr x2, [fp, #0x10] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 64 278: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue[System.__Canon](BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon],System.__Canon) [Tier0, IL size=14, code size=64] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue(BenchmarkDotNet.Characteristics.Characteristic,System.Object):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] G_M000_IG02: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x40] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbz w0, G_M000_IG05 ldr x0, [fp, #0x40] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x20] ldr x1, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x30] ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x38] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x18] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x28] ldr x0, [fp, #0x30] ldr x1, [fp, #0x28] cmp x0, x1 beq G_M000_IG06 ldr x0, [fp, #0x30] cbz x0, G_M000_IG03 ldr x0, [fp, #0x30] ldr x1, [fp, #0x40] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldr x0, [fp, #0x28] cbz x0, G_M000_IG06 ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x28] ldr x2, [fp, #0x40] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG04: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG05: ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x38] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG06: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 436 279: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue(BenchmarkDotNet.Characteristics.Characteristic,System.Object) [Tier0, IL size=88, code size=436] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:AssertNotFrozen():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] str xzr, [x9, #0x40] str x0, [fp, #0x58] G_M000_IG02: ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG04 G_M000_IG03: add x0, fp, #48 mov w1, #55 mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x20] ldr x1, [fp, #0x20] add x0, fp, #48 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #48 ldr x2, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x18] ldr x1, [fp, #0x18] add x0, fp, #48 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x28] bl CORINFO_HELP_THROW G_M000_IG04: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 336 280: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:AssertNotFrozen() [Tier0, IL size=64, code size=336] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:get_Frozen():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x20] str x0, [fp, #0x18] ldr x0, [fp, #0x20] cbnz x0, G_M000_IG04 ldr x0, [fp, #0x28] ldrb w0, [x0, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 112 281: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:get_Frozen() [Tier0, IL size=23, code size=112] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:get_Owner():BenchmarkDotNet.Characteristics.CharacteristicObject:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 282: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:get_Owner() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:get_HasChildCharacteristics():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 64 283: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:get_HasChildCharacteristics() [Tier0, IL size=12, code size=64] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:get_CharacteristicType():System.Type:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 284: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:get_CharacteristicType() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicHelper:IsCharacteristicObjectSubclass(System.Type):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x2, [fp, #0x10] ldr x2, [x2] ldr x2, [x2, #0xB0] ldr x2, [x2, #0x18] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 88 285: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicHelper:IsCharacteristicObjectSubclass(System.Type) [Tier0, IL size=22, code size=88] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:SetValueCore(BenchmarkDotNet.Characteristics.Characteristic,System.Object):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! str x19, [sp, #0x98] mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp xzr, xzr, [x9, #0x60] str x0, [fp, #0x90] str x1, [fp, #0x88] str x2, [fp, #0x80] G_M000_IG02: ldr x0, [fp, #0x88] ldr x1, [fp, #0x80] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x19, [fp, #0x80] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] cmp x19, x0 beq G_M000_IG03 ldr x0, [fp, #0x80] cbnz x0, G_M000_IG05 G_M000_IG03: ldr x0, [fp, #0x90] ldr x0, [x0, #0x08] ldr x1, [fp, #0x88] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG04: ldr x19, [sp, #0x98] ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG05: ldr x0, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbz w0, G_M000_IG09 ldr x0, [fp, #0x90] ldr x0, [x0, #0x08] ldr x1, [fp, #0x88] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG07 G_M000_IG06: add x0, fp, #80 mov w1, #41 mov w2, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x40] ldr x1, [fp, #0x40] add x0, fp, #80 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #80 ldr x2, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x38] ldr x1, [fp, #0x38] add x0, fp, #80 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #80 ldr x2, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x30] ldr x1, [fp, #0x30] add x0, fp, #80 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] add x0, fp, #80 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x28] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x20] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] ldr x0, [fp, #0x48] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x48] bl CORINFO_HELP_THROW G_M000_IG07: ldr x0, [fp, #0x90] ldr x1, [fp, #0x88] ldr x2, [fp, #0x80] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x18] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x78] ldr x0, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x78] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x90] ldr x0, [x0, #0x08] ldr x1, [fp, #0x88] ldr x2, [fp, #0x78] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG08: ldr x19, [sp, #0x98] ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG09: ldr x0, [fp, #0x90] ldr x0, [x0, #0x08] ldr x1, [fp, #0x88] ldr x2, [fp, #0x80] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG10: ldr x19, [sp, #0x98] ldp fp, lr, [sp], #0xA0 ret lr ; Total bytes of code 888 286: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:SetValueCore(BenchmarkDotNet.Characteristics.Characteristic,System.Object) [Tier0, IL size=191, code size=888] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:AssertIsAssignable(BenchmarkDotNet.Characteristics.Characteristic,System.Object) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! str x19, [sp, #0x98] mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp xzr, xzr, [x9, #0x60] str x0, [fp, #0x90] str x1, [fp, #0x88] G_M000_IG02: ldr x19, [fp, #0x88] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] cmp x19, x0 beq G_M000_IG03 ldr x0, [fp, #0x88] cbnz x0, G_M000_IG06 G_M000_IG03: ldr x0, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbz w0, G_M000_IG05 G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x58] ldr x0, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x40] ldr x1, [fp, #0x40] ldr x0, [fp, #0x58] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x58] bl CORINFO_HELP_THROW G_M000_IG05: ldr x19, [sp, #0x98] ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG06: ldr x0, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x38] ldr x0, [fp, #0x38] ldr x1, [fp, #0x88] ldr x2, [fp, #0x38] ldr x2, [x2] ldr x2, [x2, #0xA0] ldr x2, [x2, #0x08] blr x2 cbnz w0, G_M000_IG08 G_M000_IG07: add x0, fp, #96 mov w1, #42 mov w2, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x30] ldr x1, [fp, #0x30] add x0, fp, #96 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #96 ldr x2, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] ldr x1, [fp, #0x28] add x0, fp, #96 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #96 ldr x2, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x20] ldr x1, [fp, #0x20] add x0, fp, #96 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #96 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x50] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] ldr x0, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x18] ldr x2, [fp, #0x18] ldr x1, [fp, #0x50] ldr x0, [fp, #0x48] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x48] bl CORINFO_HELP_THROW G_M000_IG08: ldr x19, [sp, #0x98] ldp fp, lr, [sp], #0xA0 ret lr ; Total bytes of code 728 287: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:AssertIsAssignable(BenchmarkDotNet.Characteristics.Characteristic,System.Object) [Tier0, IL size=133, code size=728] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 288: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method BenchmarkDotNet.Jobs.GcMode:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 289: JIT compiled BenchmarkDotNet.Jobs.GcMode:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Jobs.JobMode`1[System.__Canon]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 290: JIT compiled BenchmarkDotNet.Jobs.JobMode`1[System.__Canon]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 291: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:GetValue(BenchmarkDotNet.Characteristics.Characteristic):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] add x2, fp, #24 ldr x1, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 cbnz w0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] G_M000_IG03: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] ldr x2, [fp, #0x18] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG04: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 124 292: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:GetValue(BenchmarkDotNet.Characteristics.Characteristic) [Tier0, IL size=31, code size=124] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveCore(BenchmarkDotNet.Characteristics.Characteristic,System.Object):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] ldr x2, [fp, #0x18] ldr x3, [fp, #0x20] ldr x3, [x3] ldr x3, [x3, #0x40] ldr x3, [x3, #0x20] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 60 293: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveCore(BenchmarkDotNet.Characteristics.Characteristic,System.Object) [Tier0, IL size=9, code size=60] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon]:ResolveValueCore(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Object):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str xzr, [fp, #0x38] str xzr, [fp, #0x30] str xzr, [fp, #0x20] str xzr, [fp, #0x10] str x0, [fp, #0x58] str x0, [fp, #0x50] str x1, [fp, #0x48] str x2, [fp, #0x40] G_M000_IG02: ldr x0, [fp, #0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz x0, G_M000_IG04 ldr x0, [fp, #0x50] ldr x0, [x0] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0] str x0, [fp, #0x28] ldr x0, [fp, #0x50] ldr x1, [fp, #0x48] ldr x2, [fp, #0x40] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x30] ldr x1, [fp, #0x30] ldr x0, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG04: ldr x0, [fp, #0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x38] ldr x0, [fp, #0x50] ldr x0, [x0] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x50] ldr x1, [fp, #0x48] ldr x2, [fp, #0x40] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x10] ldr x2, [fp, #0x10] ldr x1, [fp, #0x48] ldr x0, [fp, #0x38] ldr x0, [x0, #0x08] ldr x3, [fp, #0x38] ldr x3, [x3, #0x18] blr x3 G_M000_IG05: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 320 294: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon]:ResolveValueCore(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Object) [Tier0, IL size=58, code size=320] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon]:get_Resolver():System.Func`3[System.__Canon,System.__Canon,System.__Canon]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 295: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon]:get_Resolver() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:ResolveValueCore(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Object):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] cmp x0, x1 beq G_M000_IG04 ldr x0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 92 296: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:ResolveValueCore(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Object) [Tier0, IL size=17, code size=92] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:get_FallbackValue():System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 297: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:get_FallbackValue() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:get_OwnerOrSelf():BenchmarkDotNet.Characteristics.CharacteristicObject:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x20] str x0, [fp, #0x18] ldr x0, [fp, #0x20] cbnz x0, G_M000_IG03 ldr x0, [fp, #0x28] str x0, [fp, #0x18] G_M000_IG03: ldr x0, [fp, #0x18] G_M000_IG04: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 298: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:get_OwnerOrSelf() [Tier0, IL size=12, code size=84] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:AttachToOwner(BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0xF0]! mov fp, sp movi v16.16b, #0 sub x9, fp, #16 mov x10, #128 stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40]! subs x10, x10, #64 bge pc-16 (-4 instructions) add x3, sp, #240 str x3, [fp, #0xE8] str x0, [fp, #0xE0] str x1, [fp, #0xD8] str x2, [fp, #0xD0] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x38] ldr x0, [fp, #0xD8] cbnz x0, G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x40] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x30] ldr x1, [fp, #0x30] ldr x0, [fp, #0x40] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x40] bl CORINFO_HELP_THROW G_M000_IG04: ldr x0, [fp, #0xE0] ldr x1, [fp, #0xE0] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x20] blr x1 cbz w0, G_M000_IG06 G_M000_IG05: add x0, fp, #168 mov w1, #59 mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] ldr x1, [fp, #0x28] add x0, fp, #168 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #168 ldr x2, [fp, #0xE0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x20] ldr x1, [fp, #0x20] add x0, fp, #168 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] add x0, fp, #168 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x48] bl CORINFO_HELP_THROW G_M000_IG06: ldr x0, [fp, #0xE0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 ldr x0, [fp, #0xE0] ldr x0, [x0, #0x08] str x0, [fp, #0x68] ldr x0, [fp, #0xD8] ldr x1, [fp, #0xD0] ldr x2, [fp, #0xE0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 add x8, fp, #128 ldr x0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 G_M000_IG07: b G_M000_IG11 G_M000_IG08: add x0, fp, #128 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x58] str x1, [fp, #0x60] G_M000_IG09: ldp x0, x1, [fp, #0x58] stp x0, x1, [fp, #0x70] G_M000_IG10: add x0, fp, #112 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x50] add x0, fp, #112 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x10] ldr x2, [fp, #0x10] ldr x1, [fp, #0x50] ldr x0, [fp, #0xD8] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG11: ldr w0, [fp, #0x38] sub w0, w0, #1 str w0, [fp, #0x38] ldr w0, [fp, #0x38] cmp w0, #0 bgt G_M000_IG13 G_M000_IG12: add x0, fp, #56 mov w1, #139 bl CORINFO_HELP_PATCHPOINT G_M000_IG13: add x0, fp, #128 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG08 b G_M000_IG14 G_M000_IG14: ldr x0, [fp, #0xE8] bl G_M000_IG17 G_M000_IG15: nop G_M000_IG16: ldp fp, lr, [sp], #0xF0 ret lr G_M000_IG17: stp fp, lr, [sp, #-0x20]! add x3, fp, #240 str x3, [sp, #0x18] G_M000_IG18: add x0, fp, #128 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG19: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 912 299: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:AttachToOwner(BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic) [Tier0, IL size=165, code size=912] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:get_IsPropertyBag():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 24 300: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:get_IsPropertyBag() [Tier0, IL size=2, code size=24] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:AssertIsNonFrozenRoot():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 68 301: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:AssertIsNonFrozenRoot() [Tier0, IL size=13, code size=68] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:AssertIsRoot():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] str xzr, [x9, #0x60] str x0, [fp, #0x78] G_M000_IG02: ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz x0, G_M000_IG04 G_M000_IG03: add x0, fp, #80 mov w1, #45 mov w2, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x40] ldr x1, [fp, #0x40] add x0, fp, #80 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #80 ldr x2, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x38] ldr x1, [fp, #0x38] add x0, fp, #80 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x30] ldr x2, [fp, #0x30] add x0, fp, #80 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] ldr x1, [fp, #0x28] add x0, fp, #80 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x20] add x0, fp, #80 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x48] bl CORINFO_HELP_THROW G_M000_IG04: ldp fp, lr, [sp], #0x80 ret lr ; Total bytes of code 520 302: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:AssertIsRoot() [Tier0, IL size=99, code size=520] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:SetValueOnAttach(BenchmarkDotNet.Characteristics.Characteristic,System.Object):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str x1, [fp, #0x30] str x2, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x30] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbz w0, G_M000_IG04 ldr x0, [fp, #0x38] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x10] ldr x1, [fp, #0x10] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x20] ldr x0, [fp, #0x20] str x0, [fp, #0x18] ldr x0, [fp, #0x20] cbnz x0, G_M000_IG03 b G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x18] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG04: ldr x0, [fp, #0x38] ldr x1, [fp, #0x30] ldr x2, [fp, #0x28] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG05: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 252 303: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:SetValueOnAttach(BenchmarkDotNet.Characteristics.Characteristic,System.Object) [Tier0, IL size=48, code size=252] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:SetOwnerCore(BenchmarkDotNet.Characteristics.CharacteristicObject):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x20] cbnz x0, G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x18] bl CORINFO_HELP_THROW G_M000_IG04: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x20] ldr x15, [x14, #0x08] ldr x14, [fp, #0x28] add x14, x14, #8 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x28] strb wzr, [x0, #0x18] G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 232 304: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:SetOwnerCore(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=53, code size=232] ; Assembly listing for method BenchmarkDotNet.Jobs.EnvironmentMode:set_Jit(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr w2, [fp, #0x24] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 104 305: JIT compiled BenchmarkDotNet.Jobs.EnvironmentMode:set_Jit(int) [Tier0, IL size=13, code size=104] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[int]:set_Item(BenchmarkDotNet.Characteristics.CharacteristicObject,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] G_M000_IG02: ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] ldr w2, [fp, #0x1C] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 64 306: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[int]:set_Item(BenchmarkDotNet.Characteristics.CharacteristicObject,int) [Tier0, IL size=9, code size=64] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x2, [fp, #0x10] ldr w0, [fp, #0x1C] str w0, [x2, #0x08] ldr x2, [fp, #0x10] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 307: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],int) [Tier0, IL size=14, code size=96] ; Assembly listing for method BenchmarkDotNet.Jobs.EnvironmentMode:set_Platform(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr w2, [fp, #0x24] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 104 308: JIT compiled BenchmarkDotNet.Jobs.EnvironmentMode:set_Platform(int) [Tier0, IL size=13, code size=104] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[int]:set_Item(BenchmarkDotNet.Characteristics.CharacteristicObject,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] G_M000_IG02: ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] ldr w2, [fp, #0x1C] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 64 309: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[int]:set_Item(BenchmarkDotNet.Characteristics.CharacteristicObject,int) [Tier0, IL size=9, code size=64] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x2, [fp, #0x10] ldr w0, [fp, #0x1C] str w0, [x2, #0x08] ldr x2, [fp, #0x10] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 310: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],int) [Tier0, IL size=14, code size=96] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:Freeze():System.__Canon:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x0, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x20] ldr x0, [x0] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0] str x0, [fp, #0x10] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 108 311: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:Freeze() [Tier0, IL size=12, code size=108] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:FreezeCore():BenchmarkDotNet.Characteristics.CharacteristicObject:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x18] ldrb w0, [x0, #0x18] cbnz w0, G_M000_IG03 ldr x0, [fp, #0x18] mov w1, #1 strb w1, [x0, #0x18] G_M000_IG03: ldr x0, [fp, #0x18] G_M000_IG04: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 72 312: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:FreezeCore() [Tier0, IL size=23, code size=72] ; Assembly listing for method BenchmarkDotNet.Jobs.Job:.ctor(System.String,BenchmarkDotNet.Characteristics.CharacteristicObject):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x28] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 313: JIT compiled BenchmarkDotNet.Jobs.Job:.ctor(System.String,BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=16, code size=84] ; Assembly listing for method BenchmarkDotNet.Jobs.EnvironmentMode:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 48 314: JIT compiled BenchmarkDotNet.Jobs.EnvironmentMode:.ctor() [Tier0, IL size=8, code size=48] ; Assembly listing for method BenchmarkDotNet.Jobs.RunMode:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 48 315: JIT compiled BenchmarkDotNet.Jobs.RunMode:.ctor() [Tier0, IL size=8, code size=48] ; Assembly listing for method BenchmarkDotNet.Jobs.RunMode:.ctor(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 52 316: JIT compiled BenchmarkDotNet.Jobs.RunMode:.ctor(System.String) [Tier0, IL size=8, code size=52] ; Assembly listing for method BenchmarkDotNet.Jobs.InfrastructureMode:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 317: JIT compiled BenchmarkDotNet.Jobs.InfrastructureMode:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Jobs.AccuracyMode:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 318: JIT compiled BenchmarkDotNet.Jobs.AccuracyMode:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Jobs.MetaMode:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 319: JIT compiled BenchmarkDotNet.Jobs.MetaMode:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:Apply(BenchmarkDotNet.Characteristics.CharacteristicObject):System.__Canon:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x20] str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x30] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 116 320: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:Apply(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=13, code size=116] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:ApplyCore(BenchmarkDotNet.Characteristics.CharacteristicObject):BenchmarkDotNet.Characteristics.CharacteristicObject:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x2, [fp, #0x18] ldr x1, [fp, #0x20] ldr x0, [fp, #0x28] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 92 321: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:ApplyCore(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=15, code size=92] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:GetCharacteristicsToApply(BenchmarkDotNet.Characteristics.CharacteristicObject):System.Collections.Generic.IEnumerable`1[BenchmarkDotNet.Characteristics.Characteristic]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str x1, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x28] ldr x0, [fp, #0x38] bl System.Object:GetType():System.Type:this str x0, [fp, #0x20] ldr x0, [fp, #0x30] ldr wzr, [x0] bl System.Object:GetType():System.Type:this str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG03 ldr x0, [fp, #0x38] ldr x1, [fp, #0x38] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x20] blr x1 cbnz w0, G_M000_IG03 ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x2, [fp, #0x10] ldr x1, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x28] G_M000_IG03: ldr x0, [fp, #0x28] G_M000_IG04: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 236 322: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:GetCharacteristicsToApply(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=49, code size=236] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:GetCharacteristicsToApply():System.Collections.Generic.IEnumerable`1[BenchmarkDotNet.Characteristics.Characteristic]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xB0]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] stp xzr, xzr, [x9, #0x80] str xzr, [x9, #0x90] str x0, [fp, #0xA8] G_M000_IG02: ldr x0, [fp, #0xA8] ldr x1, [fp, #0xA8] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x20] blr x1 cbnz w0, G_M000_IG05 ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x48] ldr x0, [fp, #0x40] str x0, [fp, #0x38] ldr x0, [fp, #0x48] str x0, [fp, #0x30] ldr x0, [fp, #0x48] cbnz x0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x28] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x2, [fp, #0x28] str x2, [fp, #0x30] G_M000_IG03: ldr x2, [fp, #0x30] ldr x1, [fp, #0x38] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG04: ldp fp, lr, [sp], #0xB0 ret lr G_M000_IG05: ldr x0, [fp, #0xA8] ldr x0, [x0, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x90] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x98] ldr x0, [fp, #0x90] str x0, [fp, #0x88] ldr x0, [fp, #0x98] str x0, [fp, #0x80] ldr x0, [fp, #0x98] cbnz x0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x50] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x50] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x2, [fp, #0x50] str x2, [fp, #0x80] G_M000_IG06: ldr x2, [fp, #0x80] ldr x1, [fp, #0x88] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x70] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x78] ldr x0, [fp, #0x70] str x0, [fp, #0x68] ldr x0, [fp, #0x78] str x0, [fp, #0x60] ldr x0, [fp, #0x78] cbnz x0, G_M000_IG07 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x58] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x58] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x2, [fp, #0x58] str x2, [fp, #0x60] G_M000_IG07: ldr x2, [fp, #0x60] ldr x1, [fp, #0x68] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0xA0] ldr x0, [fp, #0xA0] G_M000_IG08: ldp fp, lr, [sp], #0xB0 ret lr ; Total bytes of code 920 323: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:GetCharacteristicsToApply() [Tier0, IL size=137, code size=920] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicHelper:GetAllCharacteristics(BenchmarkDotNet.Characteristics.CharacteristicObject):System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Characteristics.Characteristic] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr wzr, [x0] bl System.Object:GetType():System.Type:this movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 52 324: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicHelper:GetAllCharacteristics(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=12, code size=52] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicHelper:GetAllCharacteristics(System.Type):System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Characteristics.Characteristic] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x20] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 248 325: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicHelper:GetAllCharacteristics(System.Type) [Tier0, IL size=38, code size=248] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicHelper:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x10] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 204 326: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicHelper:.cctor() [Tier0, IL size=31, code size=204] ; Assembly listing for method System.Collections.Concurrent.ConcurrentDictionary`2[System.__Canon,System.__Canon]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x0, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] str x0, [fp, #0x28] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x28] G_M000_IG05: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x24] ldr w1, [fp, #0x24] ldr x0, [fp, #0x30] mov w2, #31 mov w3, #1 mov x4, xzr movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 G_M000_IG06: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 172 327: JIT compiled System.Collections.Concurrent.ConcurrentDictionary`2[System.__Canon,System.__Canon]:.ctor() [Tier0, IL size=16, code size=172] ; Assembly listing for method System.Collections.Concurrent.ConcurrentDictionary`2[System.__Canon,System.__Canon]:get_DefaultConcurrencyLevel():int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 328: JIT compiled System.Collections.Concurrent.ConcurrentDictionary`2[System.__Canon,System.__Canon]:get_DefaultConcurrencyLevel() [Tier0, IL size=6, code size=40] ; Assembly listing for method System.Collections.Concurrent.ConcurrentDictionary`2[System.__Canon,System.__Canon]:.ctor(int,int,bool,System.Collections.Generic.IEqualityComparer`1[System.__Canon]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xF0]! mov fp, sp add x9, fp, #64 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] str xzr, [x9, #0x80] str x0, [fp, #0xE8] str x0, [fp, #0xE0] str w1, [fp, #0xDC] str w2, [fp, #0xD8] str w3, [fp, #0xD4] str x4, [fp, #0xC8] G_M000_IG02: ldr x0, [fp, #0xE0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov w0, #0xD1FFAB1E str w0, [fp, #0x50] ldr w0, [fp, #0xDC] cmp w0, #0 bgt G_M000_IG08 ldr w0, [fp, #0xDC] cmn w0, #1 beq G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x58] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x48] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x40] ldr x1, [fp, #0x48] ldr x2, [fp, #0x40] ldr x0, [fp, #0x58] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x58] bl CORINFO_HELP_THROW G_M000_IG04: ldr x0, [fp, #0xE0] ldr x0, [x0] str x0, [fp, #0x38] ldr x0, [fp, #0x38] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] cbz x0, G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x38] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] str x0, [fp, #0x60] b G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x60] G_M000_IG07: ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xDC] G_M000_IG08: ldr w0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [fp, #0xD8] ldr w1, [fp, #0xDC] cmp w0, w1 bge G_M000_IG09 ldr w0, [fp, #0xDC] str w0, [fp, #0xD8] G_M000_IG09: ldr w0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xD8] ldr w1, [fp, #0xDC] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_OBJ str x0, [fp, #0xC0] ldr x0, [fp, #0xC0] ldr x2, [fp, #0xC0] mov x1, xzr bl CORINFO_HELP_ARRADDR_ST mov w0, #1 str w0, [fp, #0xAC] b G_M000_IG11 G_M000_IG10: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x98] ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w1, [fp, #0xAC] sxtw x1, w1 ldr x0, [fp, #0xC0] ldr x2, [fp, #0x98] bl CORINFO_HELP_ARRADDR_ST ldr w1, [fp, #0xAC] add w1, w1, #1 str w1, [fp, #0xAC] G_M000_IG11: ldr w0, [fp, #0x50] sub w0, w0, #1 str w0, [fp, #0x50] ldr w0, [fp, #0x50] cmp w0, #0 bgt G_M000_IG13 G_M000_IG12: add x0, fp, #80 mov w1, #90 bl CORINFO_HELP_PATCHPOINT G_M000_IG13: ldr w0, [fp, #0xAC] ldr x1, [fp, #0xC0] ldr w1, [x1, #0x08] cmp w0, w1 blt G_M000_IG10 ldr x1, [fp, #0xC0] ldr w1, [x1, #0x08] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0xB8] ldr x0, [fp, #0xE0] ldr x0, [x0] str x0, [fp, #0x30] ldr x0, [fp, #0x30] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x20] cbz x0, G_M000_IG15 G_M000_IG14: ldr x1, [fp, #0x30] ldr x1, [x1, #0x30] ldr x1, [x1] ldr x1, [x1, #0x20] str x1, [fp, #0x90] b G_M000_IG16 G_M000_IG15: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x90] G_M000_IG16: ldr w1, [fp, #0xD8] sxtw x1, w1 ldr x0, [fp, #0x90] bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0xB0] b G_M000_IG17 G_M000_IG17: ldr x0, [fp, #0xC8] cbnz x0, G_M000_IG21 ldr x0, [fp, #0xE0] ldr x0, [x0] str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x28] cbz x0, G_M000_IG19 G_M000_IG18: ldr x0, [fp, #0x28] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x28] str x0, [fp, #0x68] b G_M000_IG20 G_M000_IG19: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x68] G_M000_IG20: ldr x0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xC8] G_M000_IG21: ldr x0, [fp, #0xE0] ldr x0, [x0] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 cmp x0, x1 bne G_M000_IG25 ldr x0, [fp, #0xC8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xA0] ldr x0, [fp, #0xA0] cbz x0, G_M000_IG25 ldr x0, [fp, #0xE0] ldr x0, [x0] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x38] cbz x0, G_M000_IG23 G_M000_IG22: ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x38] str x0, [fp, #0x70] b G_M000_IG24 G_M000_IG23: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x70] G_M000_IG24: ldr x0, [fp, #0x70] ldr x1, [fp, #0xA0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xC8] b G_M000_IG29 G_M000_IG25: ldr x0, [fp, #0xE0] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x28] cbz x0, G_M000_IG27 G_M000_IG26: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x28] str x0, [fp, #0x88] b G_M000_IG28 G_M000_IG27: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x88] G_M000_IG28: ldr x0, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0xC8] cmp x0, x1 bne G_M000_IG29 ldr x0, [fp, #0xE0] mov w1, #1 strb w1, [x0, #0x15] G_M000_IG29: ldr x0, [fp, #0xE0] ldr x0, [x0] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x30] cbz x0, G_M000_IG31 G_M000_IG30: ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x30] str x0, [fp, #0x78] b G_M000_IG32 G_M000_IG31: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x78] G_M000_IG32: ldr x0, [fp, #0x78] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x80] ldr x0, [fp, #0x80] ldr x1, [fp, #0xB0] ldr x2, [fp, #0xC0] ldr x3, [fp, #0xB8] ldr x4, [fp, #0xC8] movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 ldr x14, [fp, #0xE0] add x14, x14, #8 ldr x15, [fp, #0x80] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0xE0] ldr w1, [fp, #0xD4] strb w1, [x0, #0x14] ldr x0, [fp, #0xB0] ldr w0, [x0, #0x08] ldr x1, [fp, #0xC0] ldr w1, [x1, #0x08] cmp w1, #0 beq G_M000_IG36 cmn w1, #1 bne G_M000_IG33 cmp w0, #1 bvs G_M000_IG35 G_M000_IG33: sdiv w0, w0, w1 ldr x1, [fp, #0xE0] str w0, [x1, #0x10] G_M000_IG34: ldp fp, lr, [sp], #0xF0 ret lr G_M000_IG35: bl CORINFO_HELP_OVERFLOW G_M000_IG36: bl CORINFO_HELP_THROWDIVZERO brk_windows #0 ; Total bytes of code 1412 329: JIT compiled System.Collections.Concurrent.ConcurrentDictionary`2[System.__Canon,System.__Canon]:.ctor(int,int,bool,System.Collections.Generic.IEqualityComparer`1[System.__Canon]) [Tier0, IL size=264, code size=1412] ; Assembly listing for method System.Collections.HashHelpers:GetPrime(int):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp add x9, fp, #32 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] str xzr, [x9, #0x40] str w0, [fp, #0x6C] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x28] ldr w0, [fp, #0x6C] tbz w0, #31, G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x30] bl CORINFO_HELP_THROW G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x38] str x1, [fp, #0x40] G_M000_IG05: ldp x0, x1, [fp, #0x38] stp x0, x1, [fp, #0x58] G_M000_IG06: str wzr, [fp, #0x54] b G_M000_IG10 G_M000_IG07: ldr w0, [fp, #0x54] ldr w1, [fp, #0x60] cmp w0, w1 bhs G_M000_IG20 ldr x0, [fp, #0x58] ldr w1, [fp, #0x54] mov w1, w1 lsl x1, x1, #2 ldr w0, [x0, x1] str w0, [fp, #0x50] ldr w0, [fp, #0x50] ldr w1, [fp, #0x6C] cmp w0, w1 blt G_M000_IG09 ldr w0, [fp, #0x50] G_M000_IG08: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG09: ldr w0, [fp, #0x54] add w0, w0, #1 str w0, [fp, #0x54] G_M000_IG10: ldr w0, [fp, #0x28] sub w0, w0, #1 str w0, [fp, #0x28] ldr w0, [fp, #0x28] cmp w0, #0 bgt G_M000_IG12 G_M000_IG11: add x0, fp, #40 mov w1, #45 bl CORINFO_HELP_PATCHPOINT G_M000_IG12: ldr w0, [fp, #0x54] ldr w1, [fp, #0x60] cmp w0, w1 blt G_M000_IG07 ldr w0, [fp, #0x6C] orr w0, w0, #1 str w0, [fp, #0x4C] b G_M000_IG16 G_M000_IG13: ldr w0, [fp, #0x4C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG15 ldr w0, [fp, #0x4C] sub w0, w0, #1 str w0, [fp, #0x1C] ldr w0, [fp, #0x1C] mov w1, #101 sdiv w0, w0, w1 mov w1, #101 mul w0, w0, w1 ldr w1, [fp, #0x1C] sub w0, w1, w0 cbz w0, G_M000_IG15 ldr w0, [fp, #0x4C] G_M000_IG14: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG15: ldr w0, [fp, #0x4C] add w0, w0, #2 str w0, [fp, #0x4C] G_M000_IG16: ldr w0, [fp, #0x28] sub w0, w0, #1 str w0, [fp, #0x28] ldr w0, [fp, #0x28] cmp w0, #0 bgt G_M000_IG18 G_M000_IG17: add x0, fp, #40 mov w1, #83 bl CORINFO_HELP_PATCHPOINT G_M000_IG18: ldr w0, [fp, #0x4C] movn w1, #0xD1FFAB1E LSL #16 cmp w0, w1 blt G_M000_IG13 ldr w0, [fp, #0x6C] G_M000_IG19: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG20: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 488 330: JIT compiled System.Collections.HashHelpers:GetPrime(int) [Tier0, IL size=93, code size=488] ; Assembly listing for method System.Collections.HashHelpers:get_Primes():System.ReadOnlySpan`1[int] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_FIELDDESC_TO_STUBRUNTIMEFIELD str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] str x1, [fp, #0x20] ldr x0, [fp, #0x18] ldr x1, [fp, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 331: JIT compiled System.Collections.HashHelpers:get_Primes() [Tier0, IL size=11, code size=84] ; Assembly listing for method System.Runtime.CompilerServices.RuntimeHelpers:CreateSpan[int](System.RuntimeFieldHandle):System.ReadOnlySpan`1[int] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x38] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str x0, [fp, #0x48] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x20] ldr x1, [x1] ldr x1, [x1, #0x98] ldr x1, [x1, #0x08] blr x1 str x0, [fp, #0x38] stp xzr, xzr, [fp, #0x28] add x2, fp, #64 ldr x0, [fp, #0x48] ldr x1, [fp, #0x38] bl System.Runtime.CompilerServices.RuntimeHelpers:GetSpanDataFrom(System.RuntimeFieldHandle,System.RuntimeTypeHandle,byref):ulong str x0, [fp, #0x18] ldr x1, [fp, #0x18] add x0, fp, #40 ldr w2, [fp, #0x40] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x28] ldr x1, [fp, #0x30] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 140 332: JIT compiled System.Runtime.CompilerServices.RuntimeHelpers:CreateSpan[int](System.RuntimeFieldHandle) [Tier0, IL size=30, code size=140] ; Assembly listing for method System.Collections.Concurrent.ConcurrentDictionary`2+Tables[System.__Canon,System.__Canon]:.ctor(System.Collections.Concurrent.ConcurrentDictionary`2+VolatileNode[System.__Canon,System.__Canon][],System.Object[],int[],System.Collections.Generic.IEqualityComparer`1[System.__Canon]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x1, [fp, #0x30] str x2, [fp, #0x28] str x3, [fp, #0x20] str x4, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x38] add x14, x14, #16 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x38] add x14, x14, #24 ldr x15, [fp, #0x28] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x38] add x14, x14, #32 ldr x15, [fp, #0x20] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x38] add x14, x14, #8 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cmp w0, #8 bne G_M000_IG03 ldr x0, [fp, #0x30] ldr w0, [x0, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x38] str x0, [x1, #0x28] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 188 333: JIT compiled System.Collections.Concurrent.ConcurrentDictionary`2+Tables[System.__Canon,System.__Canon]:.ctor(System.Collections.Concurrent.ConcurrentDictionary`2+VolatileNode[System.__Canon,System.__Canon][],System.Object[],int[],System.Collections.Generic.IEqualityComparer`1[System.__Canon]) [Tier0, IL size=58, code size=188] ; Assembly listing for method System.Collections.HashHelpers:GetFastModMultiplier(uint):ulong ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str w0, [fp, #0x1C] G_M000_IG02: movn x0, #0 ldr w1, [fp, #0x1C] mov w1, w1 cmp x1, #0 beq G_M000_IG04 udiv x0, x0, x1 add x0, x0, #1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: bl CORINFO_HELP_THROWDIVZERO brk_windows #0 ; Total bytes of code 56 334: JIT compiled System.Collections.HashHelpers:GetFastModMultiplier(uint) [Tier0, IL size=9, code size=56] ; Assembly listing for method System.Collections.Concurrent.ConcurrentDictionary`2[System.__Canon,System.__Canon]:GetOrAdd(System.__Canon,System.Func`2[System.__Canon,System.__Canon]):System.__Canon:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp str xzr, [fp, #0x58] str xzr, [fp, #0x50] str xzr, [fp, #0x40] str xzr, [fp, #0x20] str x0, [fp, #0x78] str x0, [fp, #0x70] str x1, [fp, #0x68] str x2, [fp, #0x60] G_M000_IG02: ldr x0, [fp, #0x68] cbnz x0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG03: ldr x0, [fp, #0x60] cbnz x0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldr x0, [fp, #0x70] ldr x0, [x0, #0x08] dmb ishld str x0, [fp, #0x58] ldr x0, [fp, #0x58] ldr x0, [x0, #0x08] str x0, [fp, #0x50] ldr x0, [fp, #0x70] ldr x1, [fp, #0x50] ldr x2, [fp, #0x68] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str w0, [fp, #0x4C] ldr x0, [fp, #0x70] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] cbz x0, G_M000_IG06 G_M000_IG05: ldr x4, [fp, #0x18] ldr x4, [x4, #0x30] ldr x4, [x4] ldr x4, [x4, #0x18] str x4, [fp, #0x38] b G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x38] G_M000_IG07: add x4, fp, #64 ldr x0, [fp, #0x38] ldr x1, [fp, #0x58] ldr x2, [fp, #0x68] ldr w3, [fp, #0x4C] movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 cbnz w0, G_M000_IG08 str xzr, [fp, #0x30] add x0, fp, #48 ldr w1, [fp, #0x4C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x30] str x0, [fp, #0x28] ldr x0, [fp, #0x60] ldr x0, [x0, #0x08] ldr x1, [fp, #0x68] ldr x2, [fp, #0x60] ldr x2, [x2, #0x18] blr x2 str x0, [fp, #0x20] ldr x4, [fp, #0x20] add x7, fp, #64 ldr x1, [fp, #0x58] ldr x2, [fp, #0x68] ldr x3, [fp, #0x28] ldr x0, [fp, #0x70] mov w5, wzr mov w6, #1 movz x8, #0xD1FFAB1E movk x8, #0xD1FFAB1E LSL #16 movk x8, #0xD1FFAB1E LSL #32 ldr x8, [x8] blr x8 G_M000_IG08: ldr x0, [fp, #0x40] G_M000_IG09: ldp fp, lr, [sp], #0x80 ret lr ; Total bytes of code 428 335: JIT compiled System.Collections.Concurrent.ConcurrentDictionary`2[System.__Canon,System.__Canon]:GetOrAdd(System.__Canon,System.Func`2[System.__Canon,System.__Canon]) [Tier0, IL size=91, code size=428] ; Assembly listing for method System.Collections.Concurrent.ConcurrentDictionary`2[System.__Canon,System.__Canon]:GetHashCode(System.Collections.Generic.IEqualityComparer`1[System.__Canon],System.__Canon):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str x0, [fp, #0x48] str x0, [fp, #0x40] str x1, [fp, #0x38] str x2, [fp, #0x30] G_M000_IG02: b G_M000_IG03 G_M000_IG03: ldr x0, [fp, #0x40] ldrb w0, [x0, #0x15] cbnz w0, G_M000_IG08 ldr x0, [fp, #0x40] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x40] cbz x0, G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x40] str x0, [fp, #0x28] b G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x28] G_M000_IG06: ldr x0, [fp, #0x28] str x0, [fp, #0x20] ldr x0, [fp, #0x38] ldr x11, [fp, #0x20] ldr x1, [fp, #0x30] ldr x2, [fp, #0x20] ldr x2, [x2] blr x2 G_M000_IG07: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG08: ldr x0, [fp, #0x30] ldr x1, [fp, #0x30] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x18] blr x1 G_M000_IG09: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 192 336: JIT compiled System.Collections.Concurrent.ConcurrentDictionary`2[System.__Canon,System.__Canon]:GetHashCode(System.Collections.Generic.IEqualityComparer`1[System.__Canon],System.__Canon) [Tier0, IL size=72, code size=192] ; Assembly listing for method System.Collections.Concurrent.ConcurrentDictionary`2[System.__Canon,System.__Canon]:TryGetValueInternal(System.Collections.Concurrent.ConcurrentDictionary`2+Tables[System.__Canon,System.__Canon],System.__Canon,int,byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp str xzr, [fp, #0x38] str xzr, [fp, #0x30] str xzr, [fp, #0x28] str x0, [fp, #0x68] str x0, [fp, #0x60] str x1, [fp, #0x58] str x2, [fp, #0x50] str w3, [fp, #0x4C] str x4, [fp, #0x40] G_M000_IG02: ldr x0, [fp, #0x58] ldr x0, [x0, #0x08] str x0, [fp, #0x38] mov w0, #0xD1FFAB1E str w0, [fp, #0x10] b G_M000_IG03 G_M000_IG03: ldr x0, [fp, #0x60] ldr x1, [fp, #0x58] ldr w2, [fp, #0x4C] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x28] b G_M000_IG10 G_M000_IG04: ldr w0, [fp, #0x4C] ldr x1, [fp, #0x28] ldr w1, [x1, #0x20] cmp w0, w1 bne G_M000_IG09 ldr x0, [fp, #0x60] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x48] cbz x0, G_M000_IG06 G_M000_IG05: ldr x1, [fp, #0x60] ldr x1, [x1, #0x30] ldr x1, [x1] ldr x1, [x1, #0x48] str x1, [fp, #0x20] b G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x20] G_M000_IG07: ldr x1, [fp, #0x20] str x1, [fp, #0x18] ldr x1, [fp, #0x28] ldr x1, [x1, #0x08] ldr x0, [fp, #0x38] ldr x11, [fp, #0x18] ldr x2, [fp, #0x50] ldr x3, [fp, #0x18] ldr x3, [x3] blr x3 cbz w0, G_M000_IG09 ldr x14, [fp, #0x28] ldr x15, [x14, #0x10] ldr x14, [fp, #0x40] bl CORINFO_HELP_CHECKED_ASSIGN_REF mov w0, #1 G_M000_IG08: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG09: ldr x0, [fp, #0x28] ldr x0, [x0, #0x18] dmb ishld str x0, [fp, #0x28] G_M000_IG10: ldr w0, [fp, #0x10] sub w0, w0, #1 str w0, [fp, #0x10] ldr w0, [fp, #0x10] cmp w0, #0 bgt G_M000_IG12 G_M000_IG11: add x0, fp, #16 mov w1, #150 bl CORINFO_HELP_PATCHPOINT G_M000_IG12: ldr x0, [fp, #0x28] cbnz x0, G_M000_IG04 ldr x0, [fp, #0x40] str xzr, [x0] mov w0, wzr G_M000_IG13: ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 348 337: JIT compiled System.Collections.Concurrent.ConcurrentDictionary`2[System.__Canon,System.__Canon]:TryGetValueInternal(System.Collections.Concurrent.ConcurrentDictionary`2+Tables[System.__Canon,System.__Canon],System.__Canon,int,byref) [Tier0, IL size=162, code size=348] ; Assembly listing for method System.Collections.Concurrent.ConcurrentDictionary`2[System.__Canon,System.__Canon]:GetBucket(System.Collections.Concurrent.ConcurrentDictionary`2+Tables[System.__Canon,System.__Canon],int):System.Collections.Concurrent.ConcurrentDictionary`2+Node[System.__Canon,System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x20] str x0, [fp, #0x38] str x1, [fp, #0x30] str w2, [fp, #0x2C] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] str x0, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cmp w0, #8 bne G_M000_IG04 ldr x2, [fp, #0x30] ldr x2, [x2, #0x28] ldr x1, [fp, #0x20] ldr w1, [x1, #0x08] ldr w0, [fp, #0x2C] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x1, [fp, #0x20] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG06 add x0, x1, x0, LSL #3 add x0, x0, #16 ldar x0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG04: ldr w0, [fp, #0x2C] str w0, [fp, #0x1C] ldr x0, [fp, #0x20] ldr w0, [x0, #0x08] str w0, [fp, #0x18] ldr w0, [fp, #0x1C] ldr w1, [fp, #0x18] cmp w1, #0 beq G_M000_IG07 udiv w0, w0, w1 ldr w1, [fp, #0x18] mul w0, w0, w1 ldr w1, [fp, #0x1C] sub w0, w1, w0 ldr x1, [fp, #0x20] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG06 add x0, x1, x0, LSL #3 add x0, x0, #16 ldar x0, [x0] G_M000_IG05: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG06: bl CORINFO_HELP_RNGCHKFAIL G_M000_IG07: bl CORINFO_HELP_THROWDIVZERO brk_windows #0 ; Total bytes of code 244 338: JIT compiled System.Collections.Concurrent.ConcurrentDictionary`2[System.__Canon,System.__Canon]:GetBucket(System.Collections.Concurrent.ConcurrentDictionary`2+Tables[System.__Canon,System.__Canon],int) [Tier0, IL size=63, code size=244] ; Assembly listing for method System.Collections.HashHelpers:FastMod(uint,uint,ulong):uint ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str w0, [fp, #0x2C] str w1, [fp, #0x28] str x2, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x20] ldr w1, [fp, #0x2C] mov w1, w1 mul x0, x0, x1 lsr x0, x0, #32 add x0, x0, #1 ldr w1, [fp, #0x28] mov w1, w1 mul x0, x0, x1 lsr x0, x0, #32 str w0, [fp, #0x1C] ldr w0, [fp, #0x1C] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 76 339: JIT compiled System.Collections.HashHelpers:FastMod(uint,uint,ulong) [Tier0, IL size=20, code size=76] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicHelper:GetAllCharacteristicsCore(System.Type):System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Characteristics.Characteristic] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x18] str x0, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] ldr x2, [fp, #0x10] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 188 340: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicHelper:GetAllCharacteristicsCore(System.Type) [Tier0, IL size=25, code size=188] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicHelper:FillAllCharacteristicsCore(System.Type,System.Collections.Generic.List`1[BenchmarkDotNet.Characteristics.Characteristic],System.Collections.Generic.HashSet`1[BenchmarkDotNet.Characteristics.Characteristic]) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0xC0]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] stp xzr, xzr, [x9, #0x80] add x3, sp, #192 str x3, [fp, #0xB8] str x0, [fp, #0xB0] str x1, [fp, #0xA8] str x2, [fp, #0xA0] G_M000_IG02: ldr x0, [fp, #0xB0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x98] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x78] ldr x0, [fp, #0x98] str x0, [fp, #0x70] ldr x0, [fp, #0x78] str x0, [fp, #0x68] mov w0, #0xD1FFAB1E str w0, [fp, #0x38] ldr x0, [fp, #0x78] cbnz x0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x30] ldr x1, [fp, #0x30] ldr x0, [fp, #0x40] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x40] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x2, [fp, #0x40] str x2, [fp, #0x68] G_M000_IG03: ldr x2, [fp, #0x68] ldr x1, [fp, #0x70] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x90] G_M000_IG04: b G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x88] ldr x0, [fp, #0xA0] ldr x1, [fp, #0x88] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG06 ldr x0, [fp, #0xA8] ldr x1, [fp, #0x88] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG06: ldr w0, [fp, #0x38] sub w0, w0, #1 str w0, [fp, #0x38] ldr w0, [fp, #0x38] cmp w0, #0 bgt G_M000_IG08 G_M000_IG07: add x0, fp, #56 mov w1, #75 bl CORINFO_HELP_PATCHPOINT G_M000_IG08: ldr x0, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG05 b G_M000_IG09 G_M000_IG09: ldr x0, [fp, #0xB8] bl G_M000_IG21 G_M000_IG10: nop G_M000_IG11: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x60] ldr x0, [fp, #0x98] str x0, [fp, #0x58] ldr x0, [fp, #0x60] str x0, [fp, #0x50] ldr x0, [fp, #0x60] cbnz x0, G_M000_IG12 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x48] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x2, [fp, #0x48] str x2, [fp, #0x50] G_M000_IG12: ldr x2, [fp, #0x50] ldr x1, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x90] G_M000_IG13: b G_M000_IG15 G_M000_IG14: ldr x0, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x80] ldr x0, [fp, #0xA0] ldr x1, [fp, #0x80] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG15 ldr x0, [fp, #0xA8] ldr x1, [fp, #0x80] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x80] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x1, [fp, #0xA8] ldr x2, [fp, #0xA0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG15: ldr w0, [fp, #0x38] sub w0, w0, #1 str w0, [fp, #0x38] ldr w0, [fp, #0x38] cmp w0, #0 bgt G_M000_IG17 G_M000_IG16: add x0, fp, #56 mov w1, #176 bl CORINFO_HELP_PATCHPOINT G_M000_IG17: ldr x0, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG14 b G_M000_IG18 G_M000_IG18: ldr x0, [fp, #0xB8] bl G_M000_IG24 G_M000_IG19: nop G_M000_IG20: ldp fp, lr, [sp], #0xC0 ret lr G_M000_IG21: stp fp, lr, [sp, #-0x20]! add x3, fp, #192 str x3, [sp, #0x18] G_M000_IG22: ldr x0, [fp, #0x90] cbz x0, G_M000_IG23 ldr x0, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG23: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG24: stp fp, lr, [sp, #-0x20]! add x3, fp, #192 str x3, [sp, #0x18] G_M000_IG25: ldr x0, [fp, #0x90] cbz x0, G_M000_IG26 ldr x0, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG26: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 1196 341: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicHelper:FillAllCharacteristicsCore(System.Type,System.Collections.Generic.List`1[BenchmarkDotNet.Characteristics.Characteristic],System.Collections.Generic.HashSet`1[BenchmarkDotNet.Characteristics.Characteristic]) [Tier0, IL size=197, code size=1196] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicHelper:GetThisTypeCharacteristics(System.Type):System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Characteristics.Characteristic] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x20] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 208 342: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicHelper:GetThisTypeCharacteristics(System.Type) [Tier0, IL size=38, code size=208] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicHelper:GetThisTypeCharacteristicsCore(System.Type):System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Characteristics.Characteristic] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! mov fp, sp movi v16.16b, #0 add x9, fp, #88 add x10, fp, #0xD1FFAB1E stp q16, q16, [x9, #-0x40] stp q16, q16, [x9, #-0x20] bfm x9, xzr, #0, #5 dczva x9 add x9, x9, #64 cmp x9, x10 blo pc-16 (-4 instructions) stp q16, q16, [x10] stp q16, q16, [x10, #0x20] str x0, [fp, #0xD1FFAB1E] G_M000_IG02: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x60] ldr x0, [fp, #0x60] mov w1, #120 ldr x2, [fp, #0x60] ldr x2, [x2] ldr x2, [x2, #0x80] ldr x2, [x2, #0x28] blr x2 str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x68] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x58] ldr x1, [fp, #0x58] ldr x0, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x68] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x2, [fp, #0x68] str x2, [fp, #0xD1FFAB1E] G_M000_IG03: ldr x2, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x70] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x50] ldr x1, [fp, #0x50] ldr x0, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x70] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x2, [fp, #0x70] str x2, [fp, #0xD1FFAB1E] G_M000_IG04: ldr x2, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x48] ldr x0, [fp, #0x48] mov w1, #120 ldr x2, [fp, #0x48] ldr x2, [x2] ldr x2, [x2, #0x90] ldr x2, [x2, #0x38] blr x2 str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x78] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x40] ldr x1, [fp, #0x40] ldr x0, [fp, #0x78] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x78] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x2, [fp, #0x78] str x2, [fp, #0xD1FFAB1E] G_M000_IG05: ldr x2, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0xF0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xF8] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xE8] ldr x0, [fp, #0xF0] str x0, [fp, #0xE0] ldr x0, [fp, #0xF8] str x0, [fp, #0xD8] ldr x0, [fp, #0xF8] cbnz x0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x80] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x38] ldr x1, [fp, #0x38] ldr x0, [fp, #0x80] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x80] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x2, [fp, #0x80] str x2, [fp, #0xD8] G_M000_IG06: ldr x2, [fp, #0xD8] ldr x1, [fp, #0xE0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xE8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x30] ldr x1, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xC8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD0] ldr x0, [fp, #0xC8] str x0, [fp, #0xC0] ldr x0, [fp, #0xD0] str x0, [fp, #0xB8] ldr x0, [fp, #0xD0] cbnz x0, G_M000_IG07 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x88] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x28] ldr x1, [fp, #0x28] ldr x0, [fp, #0x88] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x88] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x2, [fp, #0x88] str x2, [fp, #0xB8] G_M000_IG07: ldr x2, [fp, #0xB8] ldr x1, [fp, #0xC0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0xA8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xB0] ldr x0, [fp, #0xA8] str x0, [fp, #0xA0] ldr x0, [fp, #0xB0] str x0, [fp, #0x98] ldr x0, [fp, #0xB0] cbnz x0, G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x90] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0x90] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x90] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x2, [fp, #0x90] str x2, [fp, #0x98] G_M000_IG08: ldr x2, [fp, #0x98] ldr x1, [fp, #0xA0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x18] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG09: ldp fp, lr, [sp], #0xD1FFAB1E ret lr ; Total bytes of code 1860 343: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicHelper:GetThisTypeCharacteristicsCore(System.Type) [Tier0, IL size=260, code size=1860] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicHelper+<>c:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 344: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicHelper+<>c:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicHelper+<>c:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 345: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicHelper+<>c:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Linq.Enumerable:Select[System.__Canon,System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,System.__Canon]):System.Collections.Generic.IEnumerable`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! mov fp, sp movi v16.16b, #0 add x9, fp, #48 mov x10, #144 stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40]! subs x10, x10, #64 bge pc-16 (-4 instructions) stp xzr, xzr, [x9, #0x20] str x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] str x1, [fp, #0xD1FFAB1E] str x2, [fp, #0xD1FFAB1E] G_M000_IG02: ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG04 mov w0, #15 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] cbz x0, G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] str x0, [fp, #0xE0] b G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0xE0] G_M000_IG07: ldr x0, [fp, #0xE0] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbz x0, G_M000_IG15 ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] cbz x0, G_M000_IG09 G_M000_IG08: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] str x0, [fp, #0x68] b G_M000_IG10 G_M000_IG09: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x68] G_M000_IG10: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] str x0, [fp, #0x48] ldr x0, [fp, #0x48] ldr x0, [x0, #0x10] cmp x0, #112 ble G_M000_IG13 G_M000_IG11: ldr x0, [fp, #0x48] ldr x0, [x0, #0x70] cbz x0, G_M000_IG13 G_M000_IG12: ldr x0, [fp, #0x48] ldr x0, [x0, #0x70] str x0, [fp, #0x60] b G_M000_IG14 G_M000_IG13: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x60] G_M000_IG14: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0x68] ldr x2, [fp, #0x60] bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x58] ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0x58] blr x2 str x0, [fp, #0x50] b G_M000_IG58 G_M000_IG15: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] cbz x0, G_M000_IG17 G_M000_IG16: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] str x0, [fp, #0xD8] b G_M000_IG18 G_M000_IG17: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0xD8] G_M000_IG18: ldr x0, [fp, #0xD8] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbz x0, G_M000_IG46 ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] str x0, [fp, #0x40] ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] cmp x0, #64 ble G_M000_IG21 G_M000_IG19: ldr x0, [fp, #0x40] ldr x0, [x0, #0x40] cbz x0, G_M000_IG21 G_M000_IG20: ldr x0, [fp, #0x40] ldr x0, [x0, #0x40] str x0, [fp, #0xB0] b G_M000_IG22 G_M000_IG21: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0xB0] G_M000_IG22: ldr x0, [fp, #0xB0] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbz x0, G_M000_IG32 ldr x0, [fp, #0xD1FFAB1E] ldr w0, [x0, #0x08] cbz w0, G_M000_IG27 ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] str x0, [fp, #0x38] ldr x0, [fp, #0x38] ldr x0, [x0, #0x10] cmp x0, #104 ble G_M000_IG25 G_M000_IG23: ldr x0, [fp, #0x38] ldr x0, [x0, #0x68] cbz x0, G_M000_IG25 G_M000_IG24: ldr x0, [fp, #0x38] ldr x0, [x0, #0x68] str x0, [fp, #0x70] b G_M000_IG26 G_M000_IG25: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x70] G_M000_IG26: ldr x0, [fp, #0x70] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x78] ldr x0, [fp, #0x78] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x78] str x0, [fp, #0xF0] ldr x0, [fp, #0xF0] str x0, [fp, #0x50] b G_M000_IG58 G_M000_IG27: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] str x0, [fp, #0x30] ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] cmp x0, #96 ble G_M000_IG30 G_M000_IG28: ldr x0, [fp, #0x30] ldr x0, [x0, #0x60] cbz x0, G_M000_IG30 G_M000_IG29: ldr x0, [fp, #0x30] ldr x0, [x0, #0x60] str x0, [fp, #0x80] b G_M000_IG31 G_M000_IG30: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x80] G_M000_IG31: ldr x0, [fp, #0x80] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x50] b G_M000_IG58 G_M000_IG32: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x0, [x0, #0x10] cmp x0, #72 ble G_M000_IG35 G_M000_IG33: ldr x0, [fp, #0x28] ldr x0, [x0, #0x48] cbz x0, G_M000_IG35 G_M000_IG34: ldr x0, [fp, #0x28] ldr x0, [x0, #0x48] str x0, [fp, #0xA8] b G_M000_IG36 G_M000_IG35: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0xA8] G_M000_IG36: ldr x0, [fp, #0xA8] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xF8] ldr x0, [fp, #0xF8] cbz x0, G_M000_IG41 ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] cmp x0, #88 ble G_M000_IG39 G_M000_IG37: ldr x0, [fp, #0x20] ldr x0, [x0, #0x58] cbz x0, G_M000_IG39 G_M000_IG38: ldr x0, [fp, #0x20] ldr x0, [x0, #0x58] str x0, [fp, #0x88] b G_M000_IG40 G_M000_IG39: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x88] G_M000_IG40: ldr x0, [fp, #0x88] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x90] ldr x0, [fp, #0x90] ldr x1, [fp, #0xF8] ldr x2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x90] str x0, [fp, #0x50] b G_M000_IG58 G_M000_IG41: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x10] cmp x0, #80 ble G_M000_IG44 G_M000_IG42: ldr x0, [fp, #0x18] ldr x0, [x0, #0x50] cbz x0, G_M000_IG44 G_M000_IG43: ldr x0, [fp, #0x18] ldr x0, [x0, #0x50] str x0, [fp, #0x98] b G_M000_IG45 G_M000_IG44: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x98] G_M000_IG45: ldr x0, [fp, #0x98] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xA0] ldr x0, [fp, #0xA0] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xA0] str x0, [fp, #0x50] b G_M000_IG58 G_M000_IG46: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x28] cbz x0, G_M000_IG48 G_M000_IG47: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x28] str x0, [fp, #0xD0] b G_M000_IG49 G_M000_IG48: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0xD0] G_M000_IG49: ldr x0, [fp, #0xD0] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbz x0, G_M000_IG54 str xzr, [fp, #0xE8] ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x10] cmp x0, #56 ble G_M000_IG52 G_M000_IG50: ldr x0, [fp, #0x10] ldr x0, [x0, #0x38] cbz x0, G_M000_IG52 G_M000_IG51: ldr x3, [fp, #0x10] ldr x3, [x3, #0x38] str x3, [fp, #0xB8] b G_M000_IG53 G_M000_IG52: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0xB8] G_M000_IG53: add x3, fp, #232 ldr x0, [fp, #0xB8] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0xE8] cbz x0, G_M000_IG54 ldr x0, [fp, #0xE8] str x0, [fp, #0x50] b G_M000_IG58 G_M000_IG54: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x30] cbz x0, G_M000_IG56 G_M000_IG55: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] ldr x0, [x0, #0x30] str x0, [fp, #0xC0] b G_M000_IG57 G_M000_IG56: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0xC0] G_M000_IG57: ldr x0, [fp, #0xC0] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xC8] ldr x0, [fp, #0xC8] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xC8] str x0, [fp, #0x50] b G_M000_IG58 G_M000_IG58: ldr x0, [fp, #0x50] G_M000_IG59: ldp fp, lr, [sp], #0xD1FFAB1E ret lr ; Total bytes of code 1652 346: JIT compiled System.Linq.Enumerable:Select[System.__Canon,System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,System.__Canon]) [Tier0, IL size=146, code size=1652] ; Assembly listing for method System.Linq.Enumerable+WhereArrayIterator`1[System.__Canon]:Select[System.__Canon](System.Func`2[System.__Canon,System.__Canon]):System.Collections.Generic.IEnumerable`1[System.__Canon]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x18] str x1, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] str x2, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x28] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: ldr x0, [fp, #0x10] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x2, [fp, #0x30] ldr x2, [x2, #0x20] ldr x1, [fp, #0x30] ldr x1, [x1, #0x18] ldr x0, [fp, #0x18] ldr x3, [fp, #0x20] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x18] G_M000_IG06: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 156 347: JIT compiled System.Linq.Enumerable+WhereArrayIterator`1[System.__Canon]:Select[System.__Canon](System.Func`2[System.__Canon,System.__Canon]) [Tier0, IL size=19, code size=156] ; Assembly listing for method System.Linq.Enumerable+WhereSelectArrayIterator`2[System.__Canon,System.__Canon]:.ctor(System.__Canon[],System.Func`2[System.__Canon,bool],System.Func`2[System.__Canon,System.__Canon]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] str x3, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] add x14, x14, #24 ldr x15, [fp, #0x20] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x28] add x14, x14, #32 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x28] add x14, x14, #40 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 104 348: JIT compiled System.Linq.Enumerable+WhereSelectArrayIterator`2[System.__Canon,System.__Canon]:.ctor(System.__Canon[],System.Func`2[System.__Canon,bool],System.Func`2[System.__Canon,System.__Canon]) [Tier0, IL size=28, code size=104] ; Assembly listing for method System.Linq.Enumerable:Empty[System.__Canon]():System.Collections.Generic.IEnumerable`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x0, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x18] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x18] G_M000_IG05: ldr x0, [fp, #0x18] bl CORINFO_HELP_GETGENERICS_GCSTATIC_BASE ldr x0, [x0] G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 349: JIT compiled System.Linq.Enumerable:Empty[System.__Canon]() [Tier0, IL size=6, code size=96] ; Assembly listing for method System.Linq.EmptyPartition`1[System.__Canon]:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x0, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x20] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x20] bl CORINFO_HELP_GETGENERICS_GCSTATIC_BASE ldr x15, [fp, #0x18] mov x14, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 350: JIT compiled System.Linq.EmptyPartition`1[System.__Canon]:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method System.Linq.EmptyPartition`1[System.__Canon]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 351: JIT compiled System.Linq.EmptyPartition`1[System.__Canon]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Linq.Enumerable:CreateSelectIPartitionIterator[System.__Canon,System.__Canon](System.Func`2[System.__Canon,System.__Canon],System.Linq.IPartition`1[System.__Canon],byref) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp add x9, fp, #32 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str xzr, [x9, #0x30] str x0, [fp, #0x78] str x0, [fp, #0x70] str x1, [fp, #0x68] str x2, [fp, #0x60] str x3, [fp, #0x58] G_M000_IG02: ldr x0, [fp, #0x70] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x70] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] str x0, [fp, #0x48] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x70] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x48] G_M000_IG05: ldr x0, [fp, #0x58] str x0, [fp, #0x40] ldr x0, [fp, #0x48] ldr x1, [fp, #0x60] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz x0, G_M000_IG09 ldr x0, [fp, #0x70] ldr x0, [x0, #0x10] ldr x0, [x0, #0x28] cbz x0, G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x70] ldr x0, [x0, #0x10] ldr x0, [x0, #0x28] str x0, [fp, #0x18] b G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x70] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x18] G_M000_IG08: ldr x0, [fp, #0x18] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x60] ldr x2, [fp, #0x68] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x14, [fp, #0x20] str x14, [fp, #0x50] ldr x14, [fp, #0x40] str x14, [fp, #0x30] ldr x14, [fp, #0x50] str x14, [fp, #0x28] b G_M000_IG13 G_M000_IG09: ldr x0, [fp, #0x70] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] cbz x0, G_M000_IG11 G_M000_IG10: ldr x0, [fp, #0x70] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] str x0, [fp, #0x38] b G_M000_IG12 G_M000_IG11: ldr x0, [fp, #0x70] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x38] G_M000_IG12: ldr x0, [fp, #0x40] str x0, [fp, #0x30] ldr x0, [fp, #0x38] bl CORINFO_HELP_GETGENERICS_GCSTATIC_BASE ldr x0, [x0] str x0, [fp, #0x28] G_M000_IG13: ldr x14, [fp, #0x30] ldr x15, [fp, #0x28] bl CORINFO_HELP_CHECKED_ASSIGN_REF G_M000_IG14: ldp fp, lr, [sp], #0x80 ret lr ; Total bytes of code 384 352: JIT compiled System.Linq.Enumerable:CreateSelectIPartitionIterator[System.__Canon,System.__Canon](System.Func`2[System.__Canon,System.__Canon],System.Linq.IPartition`1[System.__Canon],byref) [Tier0, IL size=27, code size=384] ; Assembly listing for method System.Linq.Enumerable:Concat[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Collections.Generic.IEnumerable`1[System.__Canon]):System.Collections.Generic.IEnumerable`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x0, [fp, #0x40] str x1, [fp, #0x38] str x2, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x38] cbnz x0, G_M000_IG03 mov w0, #4 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x30] cbnz x0, G_M000_IG04 mov w0, #14 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x20] b G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x40] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x20] G_M000_IG07: ldr x0, [fp, #0x20] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x28] ldr x0, [fp, #0x28] cbnz x0, G_M000_IG12 ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] cbz x0, G_M000_IG09 G_M000_IG08: ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] str x0, [fp, #0x10] b G_M000_IG10 G_M000_IG09: ldr x0, [fp, #0x40] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG10: ldr x0, [fp, #0x10] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x38] ldr x2, [fp, #0x30] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] G_M000_IG11: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG12: ldr x0, [fp, #0x28] ldr x1, [fp, #0x30] ldr x2, [fp, #0x28] ldr x2, [x2] ldr x2, [x2, #0x50] ldr x2, [x2, #0x10] blr x2 G_M000_IG13: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 348 353: JIT compiled System.Linq.Enumerable:Concat[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Collections.Generic.IEnumerable`1[System.__Canon]) [Tier0, IL size=45, code size=348] ; Assembly listing for method System.Linq.Enumerable+Concat2Iterator`1[System.__Canon]:.ctor(System.Collections.Generic.IEnumerable`1[System.__Canon],System.Collections.Generic.IEnumerable`1[System.__Canon]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] add x14, x14, #32 ldr x15, [fp, #0x20] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x28] add x14, x14, #40 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 354: JIT compiled System.Linq.Enumerable+Concat2Iterator`1[System.__Canon]:.ctor(System.Collections.Generic.IEnumerable`1[System.__Canon],System.Collections.Generic.IEnumerable`1[System.__Canon]) [Tier0, IL size=21, code size=84] ; Assembly listing for method System.Linq.Enumerable+ConcatIterator`1[System.__Canon]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 355: JIT compiled System.Linq.Enumerable+ConcatIterator`1[System.__Canon]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Linq.Enumerable:Distinct[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon]):System.Collections.Generic.IEnumerable`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x0, [fp, #0x20] str x1, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] mov x2, xzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 120 356: JIT compiled System.Linq.Enumerable:Distinct[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon]) [Tier0, IL size=8, code size=120] ; Assembly listing for method System.Linq.Enumerable:Distinct[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Collections.Generic.IEqualityComparer`1[System.__Canon]):System.Collections.Generic.IEnumerable`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] str x2, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG06: ldr x0, [fp, #0x10] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] G_M000_IG07: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 176 357: JIT compiled System.Linq.Enumerable:Distinct[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Collections.Generic.IEqualityComparer`1[System.__Canon]) [Tier0, IL size=18, code size=176] ; Assembly listing for method System.Linq.Enumerable+DistinctIterator`1[System.__Canon]:.ctor(System.Collections.Generic.IEnumerable`1[System.__Canon],System.Collections.Generic.IEqualityComparer`1[System.__Canon]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] add x14, x14, #24 ldr x15, [fp, #0x20] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x28] add x14, x14, #32 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 358: JIT compiled System.Linq.Enumerable+DistinctIterator`1[System.__Canon]:.ctor(System.Collections.Generic.IEnumerable`1[System.__Canon],System.Collections.Generic.IEqualityComparer`1[System.__Canon]) [Tier0, IL size=21, code size=84] ; Assembly listing for method System.Linq.Enumerable:OrderBy[System.__Canon,int](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,int]):System.Linq.IOrderedEnumerable`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] str x2, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] str x0, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: ldr x0, [fp, #0x10] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] mov x3, xzr mov w4, wzr mov x5, xzr movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x0, [fp, #0x18] G_M000_IG06: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 156 359: JIT compiled System.Linq.Enumerable:OrderBy[System.__Canon,int](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,int]) [Tier0, IL size=11, code size=156] ; Assembly listing for method System.Linq.OrderedEnumerable`2[System.__Canon,int]:.ctor(System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,int],System.Collections.Generic.IComparer`1[int],bool,System.Linq.OrderedEnumerable`1[System.__Canon]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] str x3, [fp, #0x30] str w4, [fp, #0x2C] str x5, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x40] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x38] cbnz x0, G_M000_IG04 mov w0, #9 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldr x14, [fp, #0x48] add x14, x14, #16 ldr x15, [fp, #0x20] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x48] add x14, x14, #24 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x48] str x0, [fp, #0x18] ldr x0, [fp, #0x30] str x0, [fp, #0x10] ldr x0, [fp, #0x30] cbnz x0, G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x10] G_M000_IG05: ldr x14, [fp, #0x18] add x14, x14, #32 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x48] ldr w1, [fp, #0x2C] strb w1, [x0, #0x28] G_M000_IG06: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 248 360: JIT compiled System.Linq.OrderedEnumerable`2[System.__Canon,int]:.ctor(System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,int],System.Collections.Generic.IComparer`1[int],bool,System.Linq.OrderedEnumerable`1[System.__Canon]) [Tier0, IL size=67, code size=248] ; Assembly listing for method System.Linq.OrderedEnumerable`1[System.__Canon]:.ctor(System.Collections.Generic.IEnumerable`1[System.__Canon]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x18] add x14, x14, #8 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 64 361: JIT compiled System.Linq.OrderedEnumerable`1[System.__Canon]:.ctor(System.Collections.Generic.IEnumerable`1[System.__Canon]) [Tier0, IL size=14, code size=64] ; Assembly listing for method System.Linq.Enumerable:ThenBy[System.__Canon,System.__Canon](System.Linq.IOrderedEnumerable`1[System.__Canon],System.Func`2[System.__Canon,System.__Canon]):System.Linq.IOrderedEnumerable`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str x0, [fp, #0x48] str x0, [fp, #0x40] str x1, [fp, #0x38] str x2, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x38] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] cbz x0, G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] str x0, [fp, #0x28] b G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x40] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x28] G_M000_IG06: ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] cbz x0, G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] str x0, [fp, #0x20] b G_M000_IG09 G_M000_IG08: ldr x0, [fp, #0x40] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x20] G_M000_IG09: ldr x0, [fp, #0x38] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x18] ldr x0, [fp, #0x38] ldr x1, [fp, #0x30] mov x2, xzr mov w3, wzr ldr x4, [fp, #0x18] blr x4 G_M000_IG10: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 228 362: JIT compiled System.Linq.Enumerable:ThenBy[System.__Canon,System.__Canon](System.Linq.IOrderedEnumerable`1[System.__Canon],System.Func`2[System.__Canon,System.__Canon]) [Tier0, IL size=20, code size=228] ; Assembly listing for method System.Linq.OrderedEnumerable`1[System.__Canon]:System.Linq.IOrderedEnumerable.CreateOrderedEnumerable[System.__Canon](System.Func`2[System.__Canon,System.__Canon],System.Collections.Generic.IComparer`1[System.__Canon],bool):System.Linq.IOrderedEnumerable`1[System.__Canon]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x18] str x1, [fp, #0x48] str x0, [fp, #0x40] str x1, [fp, #0x38] str x2, [fp, #0x30] str x3, [fp, #0x28] str w4, [fp, #0x24] G_M000_IG02: ldr x0, [fp, #0x38] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x38] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: ldr x0, [fp, #0x10] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x1, [fp, #0x40] ldr x1, [x1, #0x08] ldr w4, [fp, #0x24] uxtb w4, w4 ldr x0, [fp, #0x18] ldr x2, [fp, #0x30] ldr x3, [fp, #0x28] ldr x5, [fp, #0x40] movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x0, [fp, #0x18] G_M000_IG06: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 172 363: JIT compiled System.Linq.OrderedEnumerable`1[System.__Canon]:System.Linq.IOrderedEnumerable.CreateOrderedEnumerable[System.__Canon](System.Func`2[System.__Canon,System.__Canon],System.Collections.Generic.IComparer`1[System.__Canon],bool) [Tier0, IL size=16, code size=172] ; Assembly listing for method System.Linq.OrderedEnumerable`2[System.__Canon,System.__Canon]:.ctor(System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,System.__Canon],System.Collections.Generic.IComparer`1[System.__Canon],bool,System.Linq.OrderedEnumerable`1[System.__Canon]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str x0, [fp, #0x68] str x0, [fp, #0x60] str x1, [fp, #0x58] str x2, [fp, #0x50] str x3, [fp, #0x48] str w4, [fp, #0x44] str x5, [fp, #0x38] G_M000_IG02: ldr x0, [fp, #0x60] ldr x1, [fp, #0x58] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x58] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x50] cbnz x0, G_M000_IG04 mov w0, #9 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldr x14, [fp, #0x60] add x14, x14, #16 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x60] add x14, x14, #24 ldr x15, [fp, #0x50] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x60] str x14, [fp, #0x30] ldr x14, [fp, #0x48] str x14, [fp, #0x28] ldr x14, [fp, #0x48] cbnz x14, G_M000_IG08 ldr x14, [fp, #0x60] ldr x14, [x14] str x14, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x18] cbz x0, G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x18] str x0, [fp, #0x20] b G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x20] G_M000_IG07: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x28] G_M000_IG08: ldr x14, [fp, #0x30] add x14, x14, #32 ldr x15, [fp, #0x28] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x60] ldr w1, [fp, #0x44] strb w1, [x0, #0x28] G_M000_IG09: ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 336 364: JIT compiled System.Linq.OrderedEnumerable`2[System.__Canon,System.__Canon]:.ctor(System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,System.__Canon],System.Collections.Generic.IComparer`1[System.__Canon],bool,System.Linq.OrderedEnumerable`1[System.__Canon]) [Tier0, IL size=67, code size=336] ; Assembly listing for method System.Linq.Enumerable:ToArray[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon]):System.__Canon[] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str x0, [fp, #0x48] str x0, [fp, #0x40] str x1, [fp, #0x38] G_M000_IG02: ldr x0, [fp, #0x38] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x28] b G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x40] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x28] G_M000_IG06: ldr x0, [fp, #0x28] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x30] ldr x0, [fp, #0x30] cbnz x0, G_M000_IG11 ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] cbz x0, G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] str x0, [fp, #0x10] b G_M000_IG09 G_M000_IG08: ldr x0, [fp, #0x40] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG09: ldr x0, [fp, #0x10] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG10: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG11: ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] cbz x0, G_M000_IG13 G_M000_IG12: ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] str x0, [fp, #0x20] b G_M000_IG14 G_M000_IG13: ldr x0, [fp, #0x40] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x20] G_M000_IG14: ldr x0, [fp, #0x20] str x0, [fp, #0x18] ldr x0, [fp, #0x30] ldr x11, [fp, #0x18] ldr x1, [fp, #0x18] ldr x1, [x1] blr x1 G_M000_IG15: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 348 365: JIT compiled System.Linq.Enumerable:ToArray[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon]) [Tier0, IL size=34, code size=348] ; Assembly listing for method System.Linq.OrderedEnumerable`1[System.__Canon]:ToArray():System.__Canon[]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp str xzr, [fp, #0x60] str xzr, [fp, #0x50] str xzr, [fp, #0x48] str x0, [fp, #0x78] str x0, [fp, #0x70] G_M000_IG02: ldr x0, [fp, #0x70] ldr x0, [x0] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x2, [fp, #0x20] ldr x2, [x2, #0x30] ldr x2, [x2] ldr x2, [x2, #0x10] str x2, [fp, #0x38] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x38] G_M000_IG05: ldr x2, [fp, #0x70] ldr x2, [x2, #0x08] add x0, fp, #96 ldr x1, [fp, #0x38] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr w0, [fp, #0x68] str w0, [fp, #0x5C] mov w0, #0xD1FFAB1E str w0, [fp, #0x28] ldr w0, [fp, #0x5C] cbnz w0, G_M000_IG07 ldr x0, [fp, #0x60] G_M000_IG06: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG07: ldr x0, [fp, #0x70] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] cbz x0, G_M000_IG09 G_M000_IG08: ldr x1, [fp, #0x18] ldr x1, [x1, #0x30] ldr x1, [x1] ldr x1, [x1, #0x18] str x1, [fp, #0x30] b G_M000_IG10 G_M000_IG09: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x30] G_M000_IG10: ldr w1, [fp, #0x5C] sxtw x1, w1 ldr x0, [fp, #0x30] bl CORINFO_HELP_NEWARR_1_OBJ str x0, [fp, #0x50] ldr x1, [fp, #0x60] ldr x2, [fp, #0x68] ldr x0, [fp, #0x70] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x48] str wzr, [fp, #0x44] b G_M000_IG12 G_M000_IG11: ldr x2, [fp, #0x60] ldr x1, [fp, #0x48] ldr w0, [fp, #0x44] ldr w3, [x1, #0x08] cmp w0, w3 bhs G_M000_IG16 add x1, x1, x0, LSL #2 add x1, x1, #16 ldr w1, [x1] ldr w0, [x2, #0x08] cmp w1, w0 bhs G_M000_IG16 add x2, x2, x1, LSL #3 add x2, x2, #16 ldr x2, [x2] ldr w1, [fp, #0x44] sxtw x1, w1 ldr x0, [fp, #0x50] bl CORINFO_HELP_ARRADDR_ST ldr w0, [fp, #0x44] add w0, w0, #1 str w0, [fp, #0x44] G_M000_IG12: ldr w0, [fp, #0x28] sub w0, w0, #1 str w0, [fp, #0x28] ldr w0, [fp, #0x28] cmp w0, #0 bgt G_M000_IG14 G_M000_IG13: add x0, fp, #40 mov w1, #79 bl CORINFO_HELP_PATCHPOINT G_M000_IG14: ldr w2, [fp, #0x44] ldr x1, [fp, #0x50] ldr w1, [x1, #0x08] cmp w2, w1 blt G_M000_IG11 ldr x0, [fp, #0x50] G_M000_IG15: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG16: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 488 366: JIT compiled System.Linq.OrderedEnumerable`1[System.__Canon]:ToArray() [Tier0, IL size=88, code size=488] ; Assembly listing for method System.Linq.Buffer`1[System.__Canon]:.ctor(System.Collections.Generic.IEnumerable`1[System.__Canon]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp str xzr, [fp, #0x48] str xzr, [fp, #0x40] str x1, [fp, #0x68] str x0, [fp, #0x60] str x1, [fp, #0x58] str x2, [fp, #0x50] G_M000_IG02: ldr x0, [fp, #0x58] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x58] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x10] str x0, [fp, #0x38] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x38] G_M000_IG05: ldr x0, [fp, #0x38] ldr x1, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x48] ldr x0, [fp, #0x48] cbz x0, G_M000_IG11 ldr x0, [fp, #0x58] ldr x0, [x0, #0x30] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] cmp x0, #32 ble G_M000_IG08 G_M000_IG06: ldr x0, [fp, #0x18] ldr x0, [x0, #0x20] cbz x0, G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x18] ldr x0, [x0, #0x20] str x0, [fp, #0x28] b G_M000_IG09 G_M000_IG08: ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x28] G_M000_IG09: ldr x0, [fp, #0x28] str x0, [fp, #0x20] ldr x0, [fp, #0x48] ldr x11, [fp, #0x20] ldr x1, [fp, #0x20] ldr x1, [x1] blr x1 str x0, [fp, #0x40] ldr x14, [fp, #0x60] ldr x15, [fp, #0x40] bl CORINFO_HELP_CHECKED_ASSIGN_REF ldr x0, [fp, #0x40] ldr w0, [x0, #0x08] ldr x1, [fp, #0x60] str w0, [x1, #0x08] G_M000_IG10: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG11: ldr x0, [fp, #0x58] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] cbz x0, G_M000_IG13 G_M000_IG12: ldr x2, [fp, #0x58] ldr x2, [x2, #0x30] ldr x2, [x2] ldr x2, [x2, #0x18] str x2, [fp, #0x30] b G_M000_IG14 G_M000_IG13: ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x30] G_M000_IG14: ldr x2, [fp, #0x60] ldrsb wzr, [x2] ldr x2, [fp, #0x60] add x2, x2, #8 ldr x0, [fp, #0x30] ldr x1, [fp, #0x50] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x14, [fp, #0x60] mov x15, x0 bl CORINFO_HELP_CHECKED_ASSIGN_REF G_M000_IG15: ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 424 367: JIT compiled System.Linq.Buffer`1[System.__Canon]:.ctor(System.Collections.Generic.IEnumerable`1[System.__Canon]) [Tier0, IL size=53, code size=424] ; Assembly listing for method System.Linq.Enumerable+DistinctIterator`1[System.__Canon]:ToArray():System.__Canon[]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x38] str x0, [fp, #0x48] str x0, [fp, #0x40] G_M000_IG02: ldr x0, [fp, #0x40] ldr x0, [x0] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x10] str x0, [fp, #0x30] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x30] G_M000_IG05: ldr x0, [fp, #0x30] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] ldr x2, [fp, #0x40] ldr x2, [x2, #0x20] ldr x1, [fp, #0x40] ldr x1, [x1, #0x18] ldr x0, [fp, #0x38] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x40] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x18] cbz x0, G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x18] str x0, [fp, #0x28] b G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x28] G_M000_IG08: ldr x0, [fp, #0x28] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG09: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 268 368: JIT compiled System.Linq.Enumerable+DistinctIterator`1[System.__Canon]:ToArray() [Tier0, IL size=23, code size=268] ; Assembly listing for method System.Linq.Enumerable+ConcatIterator`1[System.__Canon]:MoveNext():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x90]! mov fp, sp str xzr, [fp, #0x78] str xzr, [fp, #0x30] str x0, [fp, #0x88] str x0, [fp, #0x80] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x38] ldr x0, [fp, #0x80] ldr w0, [x0, #0x14] cmp w0, #1 bne G_M000_IG06 ldr x0, [fp, #0x80] ldr x0, [x0] str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x28] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x10] str x0, [fp, #0x48] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x48] G_M000_IG05: ldr x0, [fp, #0x48] str x0, [fp, #0x40] ldr x0, [fp, #0x80] mov w1, wzr ldr x2, [fp, #0x80] ldr x2, [x2] ldr x2, [x2, #0x50] ldr x2, [x2, #0x08] blr x2 str x0, [fp, #0x30] ldr x0, [fp, #0x30] ldr x11, [fp, #0x40] ldr x1, [fp, #0x40] ldr x1, [x1] blr x1 ldr x14, [fp, #0x80] add x14, x14, #24 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x80] mov w1, #2 str w1, [x0, #0x14] G_M000_IG06: ldr x0, [fp, #0x80] ldr w0, [x0, #0x14] cmp w0, #1 ble G_M000_IG19 G_M000_IG07: ldr w0, [fp, #0x38] sub w0, w0, #1 str w0, [fp, #0x38] ldr w0, [fp, #0x38] cmp w0, #0 bgt G_M000_IG09 G_M000_IG08: add x0, fp, #56 mov w1, #43 bl CORINFO_HELP_PATCHPOINT G_M000_IG09: ldr x0, [fp, #0x80] ldr x0, [x0, #0x18] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbz w0, G_M000_IG14 ldr x1, [fp, #0x80] ldr x1, [x1] str x1, [fp, #0x20] ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x18] cbz x0, G_M000_IG11 G_M000_IG10: ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x18] str x0, [fp, #0x58] b G_M000_IG12 G_M000_IG11: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x58] G_M000_IG12: ldr x0, [fp, #0x58] str x0, [fp, #0x50] ldr x0, [fp, #0x80] ldr x0, [x0, #0x18] ldr x11, [fp, #0x50] ldr x1, [fp, #0x50] ldr x1, [x1] blr x1 ldr x14, [fp, #0x80] add x14, x14, #8 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF mov w0, #1 G_M000_IG13: ldp fp, lr, [sp], #0x90 ret lr G_M000_IG14: ldr x1, [fp, #0x80] ldr w1, [x1, #0x14] str w1, [fp, #0x74] ldr w1, [fp, #0x74] add w1, w1, #1 ldr x0, [fp, #0x80] str w1, [x0, #0x14] ldr w1, [fp, #0x74] sub w1, w1, #1 ldr x0, [fp, #0x80] ldr x2, [fp, #0x80] ldr x2, [x2] ldr x2, [x2, #0x50] ldr x2, [x2, #0x08] blr x2 str x0, [fp, #0x78] ldr x0, [fp, #0x78] cbz x0, G_M000_IG18 ldr x0, [fp, #0x80] ldr x0, [x0, #0x18] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 ldr x0, [fp, #0x80] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x10] cbz x0, G_M000_IG16 G_M000_IG15: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x10] str x0, [fp, #0x68] b G_M000_IG17 G_M000_IG16: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x68] G_M000_IG17: ldr x0, [fp, #0x68] str x0, [fp, #0x60] ldr x0, [fp, #0x78] ldr x11, [fp, #0x60] ldr x1, [fp, #0x60] ldr x1, [x1] blr x1 ldr x14, [fp, #0x80] add x14, x14, #24 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF b G_M000_IG07 G_M000_IG18: ldr x0, [fp, #0x80] ldr x1, [fp, #0x80] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x30] blr x1 G_M000_IG19: mov w0, wzr G_M000_IG20: ldp fp, lr, [sp], #0x90 ret lr ; Total bytes of code 704 369: JIT compiled System.Linq.Enumerable+ConcatIterator`1[System.__Canon]:MoveNext() [Tier0, IL size=137, code size=704] ; Assembly listing for method System.Linq.Enumerable+Concat2Iterator`1[System.__Canon]:GetEnumerable(int):System.Collections.Generic.IEnumerable`1[System.__Canon]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: ldr w0, [fp, #0x24] cbz w0, G_M000_IG03 ldr w0, [fp, #0x24] cmp w0, #1 beq G_M000_IG04 b G_M000_IG05 G_M000_IG03: ldr x0, [fp, #0x28] ldr x0, [x0, #0x20] str x0, [fp, #0x18] b G_M000_IG06 G_M000_IG04: ldr x0, [fp, #0x28] ldr x0, [x0, #0x28] str x0, [fp, #0x18] b G_M000_IG06 G_M000_IG05: str xzr, [fp, #0x18] G_M000_IG06: ldr x0, [fp, #0x18] G_M000_IG07: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 92 370: JIT compiled System.Linq.Enumerable+Concat2Iterator`1[System.__Canon]:GetEnumerable(int) [Tier0, IL size=31, code size=92] ; Assembly listing for method System.Linq.Enumerable+WhereSelectArrayIterator`2[System.__Canon,System.__Canon]:MoveNext():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str xzr, [fp, #0x40] str xzr, [fp, #0x38] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x58] str x0, [fp, #0x50] G_M000_IG02: ldr x0, [fp, #0x50] ldr w0, [x0, #0x14] sub w0, w0, #1 str w0, [fp, #0x4C] ldr x0, [fp, #0x50] ldr x0, [x0, #0x18] str x0, [fp, #0x40] mov w0, #0xD1FFAB1E str w0, [fp, #0x28] b G_M000_IG05 G_M000_IG03: ldr x0, [fp, #0x40] ldr w1, [fp, #0x4C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG09 add x0, x0, x1, LSL #3 add x0, x0, #16 ldr x0, [x0] str x0, [fp, #0x38] ldr x0, [fp, #0x50] ldr w0, [x0, #0x14] str w0, [fp, #0x34] ldr w0, [fp, #0x34] add w0, w0, #1 ldr x1, [fp, #0x50] str w0, [x1, #0x14] ldr w0, [fp, #0x34] str w0, [fp, #0x4C] ldr x0, [fp, #0x50] ldr x0, [x0, #0x20] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x0, [x0, #0x08] ldr x1, [fp, #0x38] ldr x2, [fp, #0x20] ldr x2, [x2, #0x18] blr x2 cbz w0, G_M000_IG05 ldr x0, [fp, #0x50] ldr x0, [x0, #0x28] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] ldr x1, [fp, #0x38] ldr x2, [fp, #0x18] ldr x2, [x2, #0x18] blr x2 ldr x14, [fp, #0x50] add x14, x14, #8 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF mov w0, #1 G_M000_IG04: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG05: ldr w0, [fp, #0x28] sub w0, w0, #1 str w0, [fp, #0x28] ldr w0, [fp, #0x28] cmp w0, #0 bgt G_M000_IG07 G_M000_IG06: add x0, fp, #40 mov w1, #78 bl CORINFO_HELP_PATCHPOINT G_M000_IG07: ldr w0, [fp, #0x4C] ldr x1, [fp, #0x40] ldr w1, [x1, #0x08] cmp w0, w1 blo G_M000_IG03 ldr x0, [fp, #0x50] ldr x1, [fp, #0x50] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x30] blr x1 mov w0, wzr G_M000_IG08: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG09: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 348 371: JIT compiled System.Linq.Enumerable+WhereSelectArrayIterator`2[System.__Canon,System.__Canon]:MoveNext() [Tier0, IL size=92, code size=348] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicHelper+<>c:b__8_0(System.Reflection.FieldInfo):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x10] ldr x1, [fp, #0x10] ldr x1, [x1] ldr x1, [x1, #0x50] ldr x1, [x1, #0x18] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 68 372: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicHelper+<>c:b__8_0(System.Reflection.FieldInfo) [Tier0, IL size=12, code size=68] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicHelper:IsCharacteristicSubclass(System.Type):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x2, [fp, #0x10] ldr x2, [x2] ldr x2, [x2, #0xB0] ldr x2, [x2, #0x18] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 88 373: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicHelper:IsCharacteristicSubclass(System.Type) [Tier0, IL size=22, code size=88] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicHelper+<>c:b__8_1(System.Reflection.FieldInfo):BenchmarkDotNet.Characteristics.Characteristic:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x20] mov x1, xzr ldr x2, [fp, #0x20] ldr x2, [x2] ldr x2, [x2, #0x58] ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 132 374: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicHelper+<>c:b__8_1(System.Reflection.FieldInfo) [Tier0, IL size=19, code size=132] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicHelper:AssertHasValue(System.Reflection.MemberInfo,BenchmarkDotNet.Characteristics.Characteristic):BenchmarkDotNet.Characteristics.Characteristic ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] str x0, [fp, #0x98] str x1, [fp, #0x90] G_M000_IG02: ldr x0, [fp, #0x98] cbnz x0, G_M000_IG03 str xzr, [fp, #0x60] b G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x98] ldr x1, [fp, #0x98] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x38] blr x1 str x0, [fp, #0x60] G_M000_IG04: ldr x0, [fp, #0x60] cbnz x0, G_M000_IG06 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x50] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x48] ldr x1, [fp, #0x48] ldr x0, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x50] bl CORINFO_HELP_THROW G_M000_IG06: ldr x0, [fp, #0x90] cbnz x0, G_M000_IG08 G_M000_IG07: add x0, fp, #104 mov w1, #22 mov w2, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x40] ldr x1, [fp, #0x40] add x0, fp, #104 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x98] ldr x1, [fp, #0x98] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x38] blr x1 str x0, [fp, #0x38] ldr x0, [fp, #0x38] ldr x1, [fp, #0x38] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x30] blr x1 str x0, [fp, #0x30] ldr x1, [fp, #0x30] add x0, fp, #104 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] ldr x1, [fp, #0x28] add x0, fp, #104 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x98] ldr x1, [fp, #0x98] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x30] blr x1 str x0, [fp, #0x20] ldr x1, [fp, #0x20] add x0, fp, #104 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x18] ldr x1, [fp, #0x18] add x0, fp, #104 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x58] add x0, fp, #104 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x58] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x58] bl CORINFO_HELP_THROW G_M000_IG08: ldr x0, [fp, #0x90] G_M000_IG09: ldp fp, lr, [sp], #0xA0 ret lr ; Total bytes of code 616 375: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicHelper:AssertHasValue(System.Reflection.MemberInfo,BenchmarkDotNet.Characteristics.Characteristic) [Tier0, IL size=126, code size=616] ; Assembly listing for method System.Linq.EmptyPartition`1[System.__Canon]:GetEnumerator():System.Collections.Generic.IEnumerator`1[System.__Canon]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 24 376: JIT compiled System.Linq.EmptyPartition`1[System.__Canon]:GetEnumerator() [Tier0, IL size=2, code size=24] ; Assembly listing for method System.Linq.EmptyPartition`1[System.__Canon]:MoveNext():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 24 377: JIT compiled System.Linq.EmptyPartition`1[System.__Canon]:MoveNext() [Tier0, IL size=2, code size=24] ; Assembly listing for method System.Linq.Enumerable+ConcatIterator`1[System.__Canon]:Dispose():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x18] cbz x0, G_M000_IG03 ldr x0, [fp, #0x18] ldr x0, [x0, #0x18] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 ldr x0, [fp, #0x18] str xzr, [x0, #0x18] G_M000_IG03: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 92 378: JIT compiled System.Linq.Enumerable+ConcatIterator`1[System.__Canon]:Dispose() [Tier0, IL size=33, code size=92] ; Assembly listing for method System.Linq.EmptyPartition`1[System.__Canon]:System.IDisposable.Dispose():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 20 379: JIT compiled System.Linq.EmptyPartition`1[System.__Canon]:System.IDisposable.Dispose() [Tier0, IL size=1, code size=20] ; Assembly listing for method System.Linq.Enumerable:HashSetToArray[System.__Canon](System.Collections.Generic.HashSet`1[System.__Canon]):System.__Canon[] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x20] str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x18] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x18] G_M000_IG05: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 sxtw x1, w0 str x1, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x18] bl CORINFO_HELP_NEWARR_1_OBJ str x0, [fp, #0x20] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x20] G_M000_IG06: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 180 380: JIT compiled System.Linq.Enumerable:HashSetToArray[System.__Canon](System.Collections.Generic.HashSet`1[System.__Canon]) [Tier0, IL size=21, code size=180] ; Assembly listing for method System.Linq.OrderedEnumerable`1[System.__Canon]:SortedMap(System.Linq.Buffer`1[System.__Canon]):int[]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x18] str x2, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] ldr w2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 381: JIT compiled System.Linq.OrderedEnumerable`1[System.__Canon]:SortedMap(System.Linq.Buffer`1[System.__Canon]) [Tier0, IL size=24, code size=96] ; Assembly listing for method System.Linq.OrderedEnumerable`1[System.__Canon]:GetEnumerableSorter():System.Linq.EnumerableSorter`1[System.__Canon]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] mov x1, xzr ldr x2, [fp, #0x18] ldr x2, [x2] ldr x2, [x2, #0x48] ldr x2, [x2, #0x28] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 48 382: JIT compiled System.Linq.OrderedEnumerable`1[System.__Canon]:GetEnumerableSorter() [Tier0, IL size=8, code size=48] ; Assembly listing for method System.Linq.OrderedEnumerable`2[System.__Canon,System.__Canon]:GetEnumerableSorter(System.Linq.EnumerableSorter`1[System.__Canon]):System.Linq.EnumerableSorter`1[System.__Canon]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp add x9, fp, #32 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str xzr, [x9, #0x30] str x0, [fp, #0x68] str x0, [fp, #0x60] str x1, [fp, #0x58] G_M000_IG02: ldr x0, [fp, #0x60] ldr x0, [x0, #0x20] str x0, [fp, #0x50] ldr x0, [fp, #0x60] ldr x0, [x0] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 cmp x0, x1 bne G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x50] cmp x0, x1 bne G_M000_IG06 ldr x0, [fp, #0x60] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x28] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x28] str x0, [fp, #0x30] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x30] G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x28] ldr x1, [fp, #0x28] ldr x0, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x50] G_M000_IG06: ldr x0, [fp, #0x60] ldr x0, [x0] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x20] cbz x0, G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x20] str x0, [fp, #0x38] b G_M000_IG09 G_M000_IG08: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x38] G_M000_IG09: ldr x0, [fp, #0x38] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x40] ldr x3, [fp, #0x60] ldrb w3, [x3, #0x28] ldr x1, [fp, #0x60] ldr x1, [x1, #0x18] ldr x0, [fp, #0x40] ldr x2, [fp, #0x50] ldr x4, [fp, #0x58] movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 ldr x0, [fp, #0x40] str x0, [fp, #0x48] ldr x0, [fp, #0x60] ldr x0, [x0, #0x10] cbz x0, G_M000_IG10 ldr x0, [fp, #0x60] ldr x0, [x0, #0x10] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x48] ldr x2, [fp, #0x20] ldr x2, [x2] ldr x2, [x2, #0x48] ldr x2, [x2, #0x28] blr x2 str x0, [fp, #0x48] G_M000_IG10: ldr x0, [fp, #0x48] G_M000_IG11: ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 488 383: JIT compiled System.Linq.OrderedEnumerable`2[System.__Canon,System.__Canon]:GetEnumerableSorter(System.Linq.EnumerableSorter`1[System.__Canon]) [Tier0, IL size=96, code size=488] ; Assembly listing for method System.Linq.EnumerableSorter`2[System.__Canon,System.__Canon]:.ctor(System.Func`2[System.__Canon,System.__Canon],System.Collections.Generic.IComparer`1[System.__Canon],bool,System.Linq.EnumerableSorter`1[System.__Canon]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x1, [fp, #0x30] str x2, [fp, #0x28] str w3, [fp, #0x24] str x4, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x38] add x14, x14, #8 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x38] add x14, x14, #16 ldr x15, [fp, #0x28] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x38] ldr w15, [fp, #0x24] strb w15, [x14, #0x28] ldr x14, [fp, #0x38] add x14, x14, #24 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 120 384: JIT compiled System.Linq.EnumerableSorter`2[System.__Canon,System.__Canon]:.ctor(System.Func`2[System.__Canon,System.__Canon],System.Collections.Generic.IComparer`1[System.__Canon],bool,System.Linq.EnumerableSorter`1[System.__Canon]) [Tier0, IL size=36, code size=120] ; Assembly listing for method System.Linq.EnumerableSorter`1[System.__Canon]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 385: JIT compiled System.Linq.EnumerableSorter`1[System.__Canon]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Linq.OrderedEnumerable`2[System.__Canon,int]:GetEnumerableSorter(System.Linq.EnumerableSorter`1[System.__Canon]):System.Linq.EnumerableSorter`1[System.__Canon]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str xzr, [fp, #0x40] str xzr, [fp, #0x38] str xzr, [fp, #0x30] str xzr, [fp, #0x20] str x0, [fp, #0x58] str x0, [fp, #0x50] str x1, [fp, #0x48] G_M000_IG02: ldr x0, [fp, #0x50] ldr x0, [x0, #0x20] str x0, [fp, #0x40] b G_M000_IG03 G_M000_IG03: ldr x0, [fp, #0x50] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x18] cbz x0, G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x18] str x0, [fp, #0x28] b G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x28] G_M000_IG06: ldr x0, [fp, #0x28] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] ldr x3, [fp, #0x50] ldrb w3, [x3, #0x28] ldr x1, [fp, #0x50] ldr x1, [x1, #0x18] ldr x0, [fp, #0x30] ldr x2, [fp, #0x40] ldr x4, [fp, #0x48] movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 ldr x0, [fp, #0x30] str x0, [fp, #0x38] ldr x0, [fp, #0x50] ldr x0, [x0, #0x10] cbz x0, G_M000_IG07 ldr x0, [fp, #0x50] ldr x0, [x0, #0x10] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x38] ldr x2, [fp, #0x20] ldr x2, [x2] ldr x2, [x2, #0x48] ldr x2, [x2, #0x28] blr x2 str x0, [fp, #0x38] G_M000_IG07: ldr x0, [fp, #0x38] G_M000_IG08: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 268 386: JIT compiled System.Linq.OrderedEnumerable`2[System.__Canon,int]:GetEnumerableSorter(System.Linq.EnumerableSorter`1[System.__Canon]) [Tier0, IL size=96, code size=268] ; Assembly listing for method System.Linq.EnumerableSorter`2[System.__Canon,int]:.ctor(System.Func`2[System.__Canon,int],System.Collections.Generic.IComparer`1[int],bool,System.Linq.EnumerableSorter`1[System.__Canon]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x1, [fp, #0x30] str x2, [fp, #0x28] str w3, [fp, #0x24] str x4, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x38] add x14, x14, #8 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x38] add x14, x14, #16 ldr x15, [fp, #0x28] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x38] ldr w15, [fp, #0x24] strb w15, [x14, #0x28] ldr x14, [fp, #0x38] add x14, x14, #24 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 120 387: JIT compiled System.Linq.EnumerableSorter`2[System.__Canon,int]:.ctor(System.Func`2[System.__Canon,int],System.Collections.Generic.IComparer`1[int],bool,System.Linq.EnumerableSorter`1[System.__Canon]) [Tier0, IL size=36, code size=120] ; Assembly listing for method System.Linq.EnumerableSorter`1[System.__Canon]:Sort(System.__Canon[],int):int[]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] G_M000_IG02: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] ldr w2, [fp, #0x1C] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x10] ldr w3, [fp, #0x1C] sub w3, w3, #1 ldr x0, [fp, #0x28] ldr x1, [fp, #0x10] mov w2, wzr ldr x4, [fp, #0x28] ldr x4, [x4] ldr x4, [x4, #0x40] ldr x4, [x4, #0x30] blr x4 ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 112 388: JIT compiled System.Linq.EnumerableSorter`1[System.__Canon]:Sort(System.__Canon[],int) [Tier0, IL size=22, code size=112] ; Assembly listing for method System.Linq.EnumerableSorter`1[System.__Canon]:ComputeMap(System.__Canon[],int):int[]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x28] str x0, [fp, #0x48] str x0, [fp, #0x40] str x1, [fp, #0x38] str w2, [fp, #0x34] G_M000_IG02: ldr x0, [fp, #0x40] ldr x1, [fp, #0x38] ldr w2, [fp, #0x34] ldr x3, [fp, #0x40] ldr x3, [x3] ldr x3, [x3, #0x40] ldr x3, [x3, #0x20] blr x3 ldr w1, [fp, #0x34] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x28] str wzr, [fp, #0x24] mov w0, #0xD1FFAB1E str w0, [fp, #0x18] b G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x28] ldr w1, [fp, #0x24] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG08 add x0, x0, x1, LSL #2 add x0, x0, #16 ldr w1, [fp, #0x24] str w1, [x0] ldr w0, [fp, #0x24] add w0, w0, #1 str w0, [fp, #0x24] G_M000_IG04: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG06 G_M000_IG05: add x0, fp, #24 mov w1, #27 bl CORINFO_HELP_PATCHPOINT G_M000_IG06: ldr w0, [fp, #0x24] ldr x1, [fp, #0x28] ldr w1, [x1, #0x08] cmp w0, w1 blt G_M000_IG03 ldr x0, [fp, #0x28] G_M000_IG07: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG08: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 228 389: JIT compiled System.Linq.EnumerableSorter`1[System.__Canon]:ComputeMap(System.__Canon[],int) [Tier0, IL size=35, code size=228] ; Assembly listing for method System.Linq.EnumerableSorter`2[System.__Canon,int]:ComputeKeys(System.__Canon[],int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp str xzr, [fp, #0x58] str xzr, [fp, #0x50] str xzr, [fp, #0x38] str xzr, [fp, #0x30] str x0, [fp, #0x78] str x0, [fp, #0x70] str x1, [fp, #0x68] str w2, [fp, #0x64] G_M000_IG02: ldr x0, [fp, #0x70] ldr x0, [x0, #0x08] str x0, [fp, #0x58] ldr x0, [fp, #0x70] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x18] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x18] str x0, [fp, #0x40] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x40] G_M000_IG05: mov w0, #0xD1FFAB1E str w0, [fp, #0x20] ldr x0, [fp, #0x40] bl CORINFO_HELP_GETGENERICS_GCSTATIC_BASE ldr x1, [x0] ldr x0, [fp, #0x58] cmp x1, x0 beq G_M000_IG10 ldr w1, [fp, #0x64] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x50] str wzr, [fp, #0x4C] b G_M000_IG07 G_M000_IG06: ldr x1, [fp, #0x68] ldr w0, [fp, #0x4C] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG15 add x1, x1, x0, LSL #3 add x1, x1, #16 ldr x1, [x1] ldr x0, [fp, #0x58] ldr x0, [x0, #0x08] ldr x2, [fp, #0x58] ldr x2, [x2, #0x18] blr x2 str w0, [fp, #0x2C] ldr x14, [fp, #0x50] ldr w15, [fp, #0x4C] ldr w12, [x14, #0x08] cmp w15, w12 bhs G_M000_IG15 add x14, x14, x15, LSL #2 add x14, x14, #16 ldr w15, [fp, #0x2C] str w15, [x14] ldr w14, [fp, #0x4C] add w14, w14, #1 str w14, [fp, #0x4C] G_M000_IG07: ldr w0, [fp, #0x20] sub w0, w0, #1 str w0, [fp, #0x20] ldr w0, [fp, #0x20] cmp w0, #0 bgt G_M000_IG09 G_M000_IG08: add x0, fp, #32 mov w1, #50 bl CORINFO_HELP_PATCHPOINT G_M000_IG09: ldr w1, [fp, #0x4C] ldr x0, [fp, #0x50] ldr w0, [x0, #0x08] cmp w1, w0 blt G_M000_IG06 ldr x14, [fp, #0x70] add x14, x14, #32 ldr x15, [fp, #0x50] bl CORINFO_HELP_ASSIGN_REF b G_M000_IG11 G_M000_IG10: ldr x1, [fp, #0x68] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x70] add x14, x14, #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG11: ldr x0, [fp, #0x70] ldr x0, [x0, #0x18] str x0, [fp, #0x38] ldr x0, [fp, #0x38] str x0, [fp, #0x30] ldr x0, [fp, #0x38] cbnz x0, G_M000_IG13 G_M000_IG12: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG13: ldr x0, [fp, #0x30] ldr x1, [fp, #0x68] ldr w2, [fp, #0x64] ldr x3, [fp, #0x30] ldr x3, [x3] ldr x3, [x3, #0x40] ldr x3, [x3, #0x20] blr x3 G_M000_IG14: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG15: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 516 390: JIT compiled System.Linq.EnumerableSorter`2[System.__Canon,int]:ComputeKeys(System.__Canon[],int) [Tier0, IL size=96, code size=516] ; Assembly listing for method System.Linq.EnumerableSorter`1[System.__Canon]:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x10] str x0, [fp, #0x38] str x0, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x30] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x10] str x0, [fp, #0x28] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x28] G_M000_IG05: ldr x0, [fp, #0x30] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] cbz x0, G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x30] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] str x0, [fp, #0x18] b G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x18] G_M000_IG08: ldr x0, [fp, #0x18] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x28] bl CORINFO_HELP_GETGENERICS_GCSTATIC_BASE ldr x1, [x0] str x1, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x30] bl CORINFO_HELP_GETGENERICS_GCSTATIC_BASE ldr x15, [fp, #0x20] mov x14, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG09: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 256 391: JIT compiled System.Linq.EnumerableSorter`1[System.__Canon]:.cctor() [Tier0, IL size=22, code size=256] ; Assembly listing for method System.Linq.EnumerableSorter`1+<>c[System.__Canon]:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x0, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x20] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x20] bl CORINFO_HELP_GETGENERICS_GCSTATIC_BASE ldr x15, [fp, #0x18] mov x14, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 392: JIT compiled System.Linq.EnumerableSorter`1+<>c[System.__Canon]:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method System.Linq.EnumerableSorter`1+<>c[System.__Canon]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 393: JIT compiled System.Linq.EnumerableSorter`1+<>c[System.__Canon]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicHelper+<>c:b__8_4(BenchmarkDotNet.Characteristics.Characteristic):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbnz w0, G_M000_IG04 mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: mov w0, #1 G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 72 394: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicHelper+<>c:b__8_4(BenchmarkDotNet.Characteristics.Characteristic) [Tier0, IL size=12, code size=72] ; Assembly listing for method System.Linq.EnumerableSorter`2[System.__Canon,System.__Canon]:ComputeKeys(System.__Canon[],int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! mov fp, sp add x9, fp, #48 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str x0, [fp, #0x98] str x0, [fp, #0x90] str x1, [fp, #0x88] str w2, [fp, #0x84] G_M000_IG02: ldr x0, [fp, #0x90] ldr x0, [x0, #0x08] str x0, [fp, #0x78] ldr x0, [fp, #0x90] ldr x0, [x0] str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x18] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x28] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x18] str x0, [fp, #0x60] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x28] movz x1, #40 movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x60] G_M000_IG05: mov w0, #0xD1FFAB1E str w0, [fp, #0x38] ldr x0, [fp, #0x60] bl CORINFO_HELP_GETGENERICS_GCSTATIC_BASE ldr x0, [x0] ldr x1, [fp, #0x78] cmp x0, x1 beq G_M000_IG13 ldr x0, [fp, #0x90] ldr x0, [x0] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x20] cbz x0, G_M000_IG07 G_M000_IG06: ldr x1, [fp, #0x20] ldr x1, [x1, #0x30] ldr x1, [x1, #0x08] ldr x1, [x1, #0x20] str x1, [fp, #0x40] b G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x20] movz x1, #56 movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x40] G_M000_IG08: ldr w1, [fp, #0x84] sxtw x1, w1 ldr x0, [fp, #0x40] bl CORINFO_HELP_NEWARR_1_OBJ str x0, [fp, #0x70] str wzr, [fp, #0x6C] b G_M000_IG10 G_M000_IG09: ldr x1, [fp, #0x88] ldr w0, [fp, #0x6C] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG21 add x1, x1, x0, LSL #3 add x1, x1, #16 ldr x1, [x1] ldr x0, [fp, #0x78] ldr x0, [x0, #0x08] ldr x2, [fp, #0x78] ldr x2, [x2, #0x18] blr x2 str x0, [fp, #0x30] ldr x2, [fp, #0x30] ldr w1, [fp, #0x6C] sxtw x1, w1 ldr x0, [fp, #0x70] bl CORINFO_HELP_ARRADDR_ST ldr w14, [fp, #0x6C] add w14, w14, #1 str w14, [fp, #0x6C] G_M000_IG10: ldr w0, [fp, #0x38] sub w0, w0, #1 str w0, [fp, #0x38] ldr w0, [fp, #0x38] cmp w0, #0 bgt G_M000_IG12 G_M000_IG11: add x0, fp, #56 mov w1, #50 bl CORINFO_HELP_PATCHPOINT G_M000_IG12: ldr w1, [fp, #0x6C] ldr x0, [fp, #0x70] ldr w0, [x0, #0x08] cmp w1, w0 blt G_M000_IG09 ldr x14, [fp, #0x90] add x14, x14, #32 ldr x15, [fp, #0x70] bl CORINFO_HELP_ASSIGN_REF b G_M000_IG17 G_M000_IG13: ldr x0, [fp, #0x90] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x20] cbz x0, G_M000_IG15 G_M000_IG14: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x20] str x0, [fp, #0x58] b G_M000_IG16 G_M000_IG15: ldr x0, [fp, #0x18] movz x1, #56 movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x58] G_M000_IG16: ldr x0, [fp, #0x58] ldr x1, [fp, #0x88] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x90] add x14, x14, #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG17: ldr x0, [fp, #0x90] ldr x0, [x0, #0x18] str x0, [fp, #0x50] ldr x0, [fp, #0x50] str x0, [fp, #0x48] ldr x0, [fp, #0x50] cbnz x0, G_M000_IG19 G_M000_IG18: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG19: ldr x0, [fp, #0x48] ldr x1, [fp, #0x88] ldr w2, [fp, #0x84] ldr x3, [fp, #0x48] ldr x3, [x3] ldr x3, [x3, #0x40] ldr x3, [x3, #0x20] blr x3 G_M000_IG20: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG21: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 648 395: JIT compiled System.Linq.EnumerableSorter`2[System.__Canon,System.__Canon]:ComputeKeys(System.__Canon[],int) [Tier0, IL size=96, code size=648] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicHelper+<>c:b__8_5(BenchmarkDotNet.Characteristics.Characteristic):System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 52 396: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicHelper+<>c:b__8_5(BenchmarkDotNet.Characteristics.Characteristic) [Tier0, IL size=7, code size=52] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:get_Id():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 397: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:get_Id() [Tier0, IL size=7, code size=28] ; Assembly listing for method System.Linq.EnumerableSorter`2[System.__Canon,int]:QuickSort(int[],int,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp add x9, fp, #32 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] str x0, [fp, #0x78] str x0, [fp, #0x70] str x1, [fp, #0x68] str w2, [fp, #0x64] str w3, [fp, #0x60] G_M000_IG02: ldr x0, [fp, #0x70] ldr x0, [x0, #0x18] cbnz x0, G_M000_IG04 ldr x0, [fp, #0x70] ldr x0, [x0, #0x10] str x0, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr x1, [fp, #0x30] cmp x0, x1 bne G_M000_IG04 ldr x0, [fp, #0x70] ldrb w0, [x0, #0x28] cbnz w0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x20] str x0, [fp, #0x58] b G_M000_IG08 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x1, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x3, [fp, #0x28] str x3, [fp, #0x58] b G_M000_IG08 G_M000_IG04: ldr x3, [fp, #0x70] ldr x3, [x3] str x3, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x18] cbz x0, G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x18] str x0, [fp, #0x50] b G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x50] G_M000_IG07: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] ldr x0, [fp, #0x70] ldr x1, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x18] ldr x2, [fp, #0x18] ldr x1, [fp, #0x70] ldr x0, [fp, #0x48] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x48] str x0, [fp, #0x58] G_M000_IG08: stp xzr, xzr, [fp, #0x38] ldr w3, [fp, #0x60] ldr w0, [fp, #0x64] sub w3, w3, w0 add w3, w3, #1 add x0, fp, #56 ldr x1, [fp, #0x68] ldr w2, [fp, #0x64] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x38] ldr x1, [fp, #0x40] ldr x2, [fp, #0x58] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG09: ldp fp, lr, [sp], #0x80 ret lr ; Total bytes of code 516 398: JIT compiled System.Linq.EnumerableSorter`2[System.__Canon,int]:QuickSort(int[],int,int) [Tier0, IL size=109, code size=516] ; Assembly listing for method System.Linq.EnumerableSorter`2[System.__Canon,int]:CompareAnyKeys(int,int):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str w1, [fp, #0x34] str w2, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x38] ldr x0, [x0, #0x20] str x0, [fp, #0x28] ldr x0, [fp, #0x38] ldr x0, [x0, #0x10] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x2, [fp, #0x28] ldr w1, [fp, #0x30] ldr w11, [x2, #0x08] cmp w1, w11 bhs G_M000_IG10 add x2, x2, x1, LSL #2 add x2, x2, #16 ldr w2, [x2] ldr x1, [fp, #0x28] ldr w11, [fp, #0x34] ldr w3, [x1, #0x08] cmp w11, w3 bhs G_M000_IG10 add x1, x1, x11, LSL #2 add x1, x1, #16 ldr w1, [x1] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x3, [x11] blr x3 str w0, [fp, #0x24] ldr w0, [fp, #0x24] cbnz w0, G_M000_IG06 ldr x0, [fp, #0x38] ldr x0, [x0, #0x18] cbnz x0, G_M000_IG04 ldr w0, [fp, #0x34] ldr w1, [fp, #0x30] sub w0, w0, w1 G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG04: ldr x0, [fp, #0x38] ldr x0, [x0, #0x18] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr w1, [fp, #0x34] ldr w2, [fp, #0x30] ldr x3, [fp, #0x10] ldr x3, [x3] ldr x3, [x3, #0x40] ldr x3, [x3, #0x28] blr x3 G_M000_IG05: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG06: ldr x0, [fp, #0x38] ldrb w0, [x0, #0x28] ldr w1, [fp, #0x24] cmp w1, #0 cset x1, gt cmp w0, w1 bne G_M000_IG08 movn w0, #0 G_M000_IG07: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG08: mov w0, #1 G_M000_IG09: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG10: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 300 399: JIT compiled System.Linq.EnumerableSorter`2[System.__Canon,int]:CompareAnyKeys(int,int) [Tier0, IL size=78, code size=300] ; Assembly listing for method System.Linq.EnumerableSorter`2[System.__Canon,System.__Canon]:CompareAnyKeys(int,int):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str xzr, [fp, #0x40] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x58] str x0, [fp, #0x50] str w1, [fp, #0x4C] str w2, [fp, #0x48] G_M000_IG02: ldr x0, [fp, #0x50] ldr x0, [x0, #0x20] str x0, [fp, #0x40] ldr x0, [fp, #0x50] ldr x0, [x0] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x28] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x28] str x0, [fp, #0x30] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x30] G_M000_IG05: ldr x0, [fp, #0x30] str x0, [fp, #0x28] ldr x0, [fp, #0x50] ldr x0, [x0, #0x10] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x2, [fp, #0x40] ldr w1, [fp, #0x48] ldr w11, [x2, #0x08] cmp w1, w11 bhs G_M000_IG13 add x2, x2, x1, LSL #3 add x2, x2, #16 ldr x2, [x2] ldr x1, [fp, #0x40] ldr w11, [fp, #0x4C] ldr w3, [x1, #0x08] cmp w11, w3 bhs G_M000_IG13 add x1, x1, x11, LSL #3 add x1, x1, #16 ldr x1, [x1] ldr x11, [fp, #0x28] ldr x3, [fp, #0x28] ldr x3, [x3] blr x3 str w0, [fp, #0x3C] ldr w0, [fp, #0x3C] cbnz w0, G_M000_IG09 ldr x0, [fp, #0x50] ldr x0, [x0, #0x18] cbnz x0, G_M000_IG07 ldr w0, [fp, #0x4C] ldr w1, [fp, #0x48] sub w0, w0, w1 G_M000_IG06: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG07: ldr x0, [fp, #0x50] ldr x0, [x0, #0x18] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr w1, [fp, #0x4C] ldr w2, [fp, #0x48] ldr x3, [fp, #0x18] ldr x3, [x3] ldr x3, [x3, #0x40] ldr x3, [x3, #0x28] blr x3 G_M000_IG08: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG09: ldr x0, [fp, #0x50] ldrb w0, [x0, #0x28] ldr w1, [fp, #0x3C] cmp w1, #0 cset x1, gt cmp w0, w1 bne G_M000_IG11 movn w0, #0 G_M000_IG10: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG11: mov w0, #1 G_M000_IG12: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG13: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 388 400: JIT compiled System.Linq.EnumerableSorter`2[System.__Canon,System.__Canon]:CompareAnyKeys(int,int) [Tier0, IL size=78, code size=388] ; Assembly listing for method System.Collections.Concurrent.ConcurrentDictionary`2[System.__Canon,System.__Canon]:TryAddInternal(System.Collections.Concurrent.ConcurrentDictionary`2+Tables[System.__Canon,System.__Canon],System.__Canon,System.Nullable`1[int],System.__Canon,bool,bool,byref):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! mov fp, sp add x9, fp, #56 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] stp q16, q16, [x9, #0x80] add x8, sp, #0xD1FFAB1E str x8, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] str x1, [fp, #0xD1FFAB1E] str x2, [fp, #0xF8] str x3, [fp, #0xF0] str x4, [fp, #0xE8] str w5, [fp, #0xE4] str w6, [fp, #0xE0] str x7, [fp, #0xD8] G_M000_IG02: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x08] str x0, [fp, #0xD0] ldr x0, [fp, #0xF0] str x0, [fp, #0xC0] mov w0, #0xD1FFAB1E str w0, [fp, #0x30] add x0, fp, #192 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG03 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD0] ldr x2, [fp, #0xF8] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str w0, [fp, #0x68] b G_M000_IG04 G_M000_IG03: add x0, fp, #192 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x68] G_M000_IG04: ldr w0, [fp, #0x68] str w0, [fp, #0xCC] G_M000_IG05: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG07 G_M000_IG06: add x0, fp, #48 mov w1, #36 bl CORINFO_HELP_PATCHPOINT G_M000_IG07: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x18] str x0, [fp, #0xB8] ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0] str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] cbz x0, G_M000_IG09 G_M000_IG08: ldr x3, [fp, #0x28] ldr x3, [x3, #0x30] ldr x3, [x3] ldr x3, [x3, #0x18] str x3, [fp, #0x60] b G_M000_IG10 G_M000_IG09: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x60] G_M000_IG10: add x3, fp, #168 ldr x0, [fp, #0x60] ldr x1, [fp, #0xD1FFAB1E] ldr w2, [fp, #0xCC] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 str x0, [fp, #0xB0] str wzr, [fp, #0xA4] str wzr, [fp, #0xA0] str wzr, [fp, #0x98] G_M000_IG11: ldr w0, [fp, #0xE0] uxtb w0, w0 cbz w0, G_M000_IG12 ldr x0, [fp, #0xB8] ldr w1, [fp, #0xA8] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG14 add x0, x0, x1, LSL #3 add x0, x0, #16 ldr x0, [x0] add x1, fp, #152 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG12: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x1, [x1, #0x08] dmb ishld cmp x0, x1 beq G_M000_IG16 ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x08] dmb ishld str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD0] ldr x1, [fp, #0xD1FFAB1E] ldr x1, [x1, #0x08] cmp x0, x1 beq G_M000_IG13 ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x08] str x0, [fp, #0xD0] ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD0] ldr x2, [fp, #0xF8] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str w0, [fp, #0xCC] G_M000_IG13: b G_M000_IG37 G_M000_IG14: bl CORINFO_HELP_RNGCHKFAIL G_M000_IG15: bl CORINFO_HELP_OVERFLOW G_M000_IG16: str wzr, [fp, #0x94] str xzr, [fp, #0x88] ldr x0, [fp, #0xB0] ldr x0, [x0] str x0, [fp, #0x78] b G_M000_IG26 G_M000_IG17: ldr w0, [fp, #0xCC] ldr x1, [fp, #0x78] ldr w1, [x1, #0x20] cmp w0, w1 bne G_M000_IG25 ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] cbz x0, G_M000_IG19 G_M000_IG18: ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] str x0, [fp, #0x58] b G_M000_IG20 G_M000_IG19: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x58] G_M000_IG20: ldr x0, [fp, #0x58] ldr x1, [fp, #0xD0] ldr x2, [fp, #0x78] ldr x3, [fp, #0xF8] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 cbz w0, G_M000_IG25 ldr w14, [fp, #0xE4] uxtb w14, w14 cbz w14, G_M000_IG23 b G_M000_IG21 G_M000_IG21: ldr x14, [fp, #0x78] add x14, x14, #16 ldr x15, [fp, #0xE8] bl CORINFO_HELP_ASSIGN_REF b G_M000_IG22 G_M000_IG22: ldr x14, [fp, #0xD8] ldr x15, [fp, #0xE8] bl CORINFO_HELP_CHECKED_ASSIGN_REF b G_M000_IG24 G_M000_IG23: ldr x14, [fp, #0x78] ldr x15, [x14, #0x10] ldr x14, [fp, #0xD8] bl CORINFO_HELP_CHECKED_ASSIGN_REF G_M000_IG24: str wzr, [fp, #0x6C] b G_M000_IG41 G_M000_IG25: ldr x0, [fp, #0x78] str x0, [fp, #0x88] ldr w0, [fp, #0x94] add w0, w0, #1 str w0, [fp, #0x94] ldr x0, [fp, #0x78] ldr x0, [x0, #0x18] dmb ishld str x0, [fp, #0x78] G_M000_IG26: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG28 G_M000_IG27: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG28: ldr x0, [fp, #0x78] cbnz x0, G_M000_IG17 ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x50] cbz x0, G_M000_IG30 G_M000_IG29: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x50] str x0, [fp, #0x48] b G_M000_IG31 G_M000_IG30: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x48] G_M000_IG31: ldr x0, [fp, #0x48] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x50] ldr x4, [fp, #0xB0] ldr x4, [x4] ldr x0, [fp, #0x50] ldr x1, [fp, #0xF8] ldr x2, [fp, #0xE8] ldr w3, [fp, #0xCC] movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 ldr x0, [fp, #0x50] str x0, [fp, #0x80] ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x58] cbz x0, G_M000_IG33 G_M000_IG32: ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x58] str x0, [fp, #0x40] b G_M000_IG34 G_M000_IG33: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x40] G_M000_IG34: ldr x0, [fp, #0x40] ldr x1, [fp, #0xB0] ldr x2, [fp, #0x80] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x1, [fp, #0xD1FFAB1E] ldr x1, [x1, #0x20] ldr w0, [fp, #0xA8] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG14 add x1, x1, x0, LSL #2 add x1, x1, #16 str x1, [fp, #0x38] ldr x1, [fp, #0x38] ldr w1, [x1] adds w1, w1, #1 bvs G_M000_IG15 ldr x0, [fp, #0x38] str w1, [x0] ldr x1, [fp, #0xD1FFAB1E] ldr x1, [x1, #0x20] ldr w0, [fp, #0xA8] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG14 add x1, x1, x0, LSL #2 add x1, x1, #16 ldr w1, [x1] ldr x0, [fp, #0xD1FFAB1E] ldr w0, [x0, #0x10] cmp w1, w0 ble G_M000_IG35 mov w1, #1 str w1, [fp, #0xA4] G_M000_IG35: ldr w1, [fp, #0x94] cmp w1, #100 bls G_M000_IG36 ldr x1, [fp, #0xD0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz x0, G_M000_IG36 mov w0, #1 str w0, [fp, #0xA0] G_M000_IG36: b G_M000_IG39 G_M000_IG37: ldr x0, [fp, #0xD1FFAB1E] bl G_M000_IG48 G_M000_IG38: b G_M000_IG05 G_M000_IG39: ldr x0, [fp, #0xD1FFAB1E] bl G_M000_IG48 G_M000_IG40: b G_M000_IG43 G_M000_IG41: ldr x0, [fp, #0xD1FFAB1E] bl G_M000_IG48 G_M000_IG42: b G_M000_IG46 G_M000_IG43: ldr w0, [fp, #0xA4] ldr w1, [fp, #0xA0] orr w0, w0, w1 cbz w0, G_M000_IG44 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr w2, [fp, #0xA4] ldr w3, [fp, #0xA0] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG44: ldr x14, [fp, #0xD8] ldr x15, [fp, #0xE8] bl CORINFO_HELP_CHECKED_ASSIGN_REF mov w0, #1 G_M000_IG45: ldp fp, lr, [sp], #0xD1FFAB1E ret lr G_M000_IG46: ldr w0, [fp, #0x6C] G_M000_IG47: ldp fp, lr, [sp], #0xD1FFAB1E ret lr G_M000_IG48: stp fp, lr, [sp, #-0x20]! add x3, fp, #0xD1FFAB1E str x3, [sp, #0x18] G_M000_IG49: ldr w0, [fp, #0x98] uxtb w0, w0 cbz w0, G_M000_IG50 ldr x0, [fp, #0xB8] ldr w1, [fp, #0xA8] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG51 add x0, x0, x1, LSL #3 add x0, x0, #16 ldr x0, [x0] bl System.Threading.Monitor:Exit(System.Object) G_M000_IG50: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG51: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 1540 401: JIT compiled System.Collections.Concurrent.ConcurrentDictionary`2[System.__Canon,System.__Canon]:TryAddInternal(System.Collections.Concurrent.ConcurrentDictionary`2+Tables[System.__Canon,System.__Canon],System.__Canon,System.Nullable`1[int],System.__Canon,bool,bool,byref) [Tier0, IL size=478, code size=1540] ; Assembly listing for method System.Collections.Concurrent.ConcurrentDictionary`2[System.__Canon,System.__Canon]:GetBucketAndLock(System.Collections.Concurrent.ConcurrentDictionary`2+Tables[System.__Canon,System.__Canon],int,byref):byref ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x28] str x0, [fp, #0x48] str x1, [fp, #0x40] str w2, [fp, #0x3C] str x3, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] str x0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cmp w0, #8 bne G_M000_IG03 ldr x2, [fp, #0x40] ldr x2, [x2, #0x28] ldr x1, [fp, #0x28] ldr w1, [x1, #0x08] ldr w0, [fp, #0x3C] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str w0, [fp, #0x24] b G_M000_IG04 G_M000_IG03: ldr w0, [fp, #0x3C] str w0, [fp, #0x20] ldr x0, [fp, #0x28] ldr w0, [x0, #0x08] str w0, [fp, #0x1C] ldr w0, [fp, #0x20] ldr w1, [fp, #0x1C] cmp w1, #0 beq G_M000_IG06 udiv w0, w0, w1 ldr w1, [fp, #0x1C] mul w0, w0, w1 ldr w1, [fp, #0x20] sub w0, w1, w0 str w0, [fp, #0x24] G_M000_IG04: ldr x0, [fp, #0x30] ldr w1, [fp, #0x24] str w1, [fp, #0x18] ldr x1, [fp, #0x40] ldr x1, [x1, #0x18] ldr w1, [x1, #0x08] str w1, [fp, #0x14] ldr w1, [fp, #0x18] ldr w2, [fp, #0x14] cmp w2, #0 beq G_M000_IG06 udiv w1, w1, w2 ldr w2, [fp, #0x14] mul w1, w1, w2 ldr w2, [fp, #0x18] sub w1, w2, w1 str w1, [x0] ldr x0, [fp, #0x28] ldr w1, [fp, #0x24] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG07 add x0, x0, x1, LSL #3 add x0, x0, #16 G_M000_IG05: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG06: bl CORINFO_HELP_THROWDIVZERO G_M000_IG07: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 292 402: JIT compiled System.Collections.Concurrent.ConcurrentDictionary`2[System.__Canon,System.__Canon]:GetBucketAndLock(System.Collections.Concurrent.ConcurrentDictionary`2+Tables[System.__Canon,System.__Canon],int,byref) [Tier0, IL size=64, code size=292] ; Assembly listing for method System.Collections.Concurrent.ConcurrentDictionary`2+Node[System.__Canon,System.__Canon]:.ctor(System.__Canon,System.__Canon,int,System.Collections.Concurrent.ConcurrentDictionary`2+Node[System.__Canon,System.__Canon]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x1, [fp, #0x30] str x2, [fp, #0x28] str w3, [fp, #0x24] str x4, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x38] add x14, x14, #8 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x38] add x14, x14, #16 ldr x15, [fp, #0x28] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x38] add x14, x14, #24 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x38] ldr w1, [fp, #0x24] str w1, [x0, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 120 403: JIT compiled System.Collections.Concurrent.ConcurrentDictionary`2+Node[System.__Canon,System.__Canon]:.ctor(System.__Canon,System.__Canon,int,System.Collections.Concurrent.ConcurrentDictionary`2+Node[System.__Canon,System.__Canon]) [Tier0, IL size=38, code size=120] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicHelper+<>c:b__13_0(BenchmarkDotNet.Characteristics.Characteristic):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cmp w0, #0 cset x0, eq G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 60 404: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicHelper+<>c:b__13_0(BenchmarkDotNet.Characteristics.Characteristic) [Tier0, IL size=10, code size=60] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicHelper+<>c:b__13_1(BenchmarkDotNet.Characteristics.Characteristic):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 52 405: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicHelper+<>c:b__13_1(BenchmarkDotNet.Characteristics.Characteristic) [Tier0, IL size=7, code size=52] ; Assembly listing for method BenchmarkDotNet.Jobs.GcMode:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 592 406: JIT compiled BenchmarkDotNet.Jobs.GcMode:.cctor() [Tier0, IL size=136, code size=592] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[int](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[int] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x0, [fp, #0x20] str x1, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 116 407: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[int](System.String) [Tier0, IL size=7, code size=116] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,int](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[int] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str wzr, [fp, #0x24] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0] bl CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE str x0, [fp, #0x18] str wzr, [fp, #0x24] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x1, [fp, #0x28] ldr x2, [fp, #0x18] ldr w4, [fp, #0x24] mov x3, xzr mov w5, wzr mov w6, wzr movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 136 408: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,int](System.String) [Tier0, IL size=29, code size=136] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[int]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,int,int],int,bool,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] str x3, [fp, #0x30] str w4, [fp, #0x2C] str w5, [fp, #0x28] str w6, [fp, #0x24] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 str x4, [fp, #0x10] ldr x4, [fp, #0x18] ldr w6, [fp, #0x2C] str w6, [x4, #0x08] ldr x4, [fp, #0x18] ldr w6, [fp, #0x24] uxtb w6, w6 ldr w5, [fp, #0x28] uxtb w5, w5 ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x10] ldr x3, [fp, #0x38] movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x14, [fp, #0x48] add x14, x14, #48 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x48] ldr w1, [fp, #0x2C] str w1, [x0, #0x38] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 184 409: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[int]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,int,int],int,bool,bool) [Tier0, IL size=45, code size=184] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject+<>c:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 410: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject+<>c:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject+<>c:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 411: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject+<>c:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Jobs.AccuracyMode:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 464 412: JIT compiled BenchmarkDotNet.Jobs.AccuracyMode:.cctor() [Tier0, IL size=106, code size=464] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[double](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[double] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x0, [fp, #0x20] str x1, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 116 413: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[double](System.String) [Tier0, IL size=7, code size=116] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,double](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[double] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0] bl CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE str x0, [fp, #0x18] str xzr, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x1, [fp, #0x28] ldr x2, [fp, #0x18] ldr d0, [fp, #0x20] mov x3, xzr mov w4, wzr mov w5, wzr movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 136 414: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,double](System.String) [Tier0, IL size=29, code size=136] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[double]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,double,double],double,bool,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] str x3, [fp, #0x30] str w4, [fp, #0x24] str w5, [fp, #0x20] str d0, [fp, #0x28] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 str x4, [fp, #0x10] ldr x4, [fp, #0x18] ldr d16, [fp, #0x28] str d16, [x4, #0x08] ldr x4, [fp, #0x18] ldr w6, [fp, #0x20] uxtb w6, w6 ldr w5, [fp, #0x24] uxtb w5, w5 ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x10] ldr x3, [fp, #0x38] movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x14, [fp, #0x48] add x14, x14, #48 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x48] ldr d16, [fp, #0x28] str d16, [x0, #0x38] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 184 415: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[double]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,double,double],double,bool,bool) [Tier0, IL size=45, code size=184] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[Perfolizer.Horology.TimeInterval](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x0, [fp, #0x20] str x1, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 116 416: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[Perfolizer.Horology.TimeInterval](System.String) [Tier0, IL size=7, code size=116] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,Perfolizer.Horology.TimeInterval](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0] bl CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE str x0, [fp, #0x18] str xzr, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x1, [fp, #0x28] ldr x2, [fp, #0x18] ldr d0, [fp, #0x20] mov x3, xzr mov w4, wzr mov w5, wzr movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 136 417: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,Perfolizer.Horology.TimeInterval](System.String) [Tier0, IL size=29, code size=136] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,Perfolizer.Horology.TimeInterval,Perfolizer.Horology.TimeInterval],Perfolizer.Horology.TimeInterval,bool,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] str x3, [fp, #0x30] str w4, [fp, #0x24] str w5, [fp, #0x20] str d0, [fp, #0x28] G_M000_IG02: add x1, fp, #40 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_BOX str x0, [fp, #0x18] ldr x4, [fp, #0x18] ldr w5, [fp, #0x24] uxtb w5, w5 ldr w6, [fp, #0x20] uxtb w6, w6 ldr x1, [fp, #0x40] ldr x3, [fp, #0x38] ldr x0, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x14, [fp, #0x48] add x14, x14, #48 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x48] ldr x1, [fp, #0x28] str x1, [x0, #0x38] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 164 418: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,Perfolizer.Horology.TimeInterval,Perfolizer.Horology.TimeInterval],Perfolizer.Horology.TimeInterval,bool,bool) [Tier0, IL size=45, code size=164] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[int](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[int] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x0, [fp, #0x20] str x1, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 116 419: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[int](System.String) [Tier0, IL size=7, code size=116] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,int](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[int] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str wzr, [fp, #0x24] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0] bl CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE str x0, [fp, #0x18] str wzr, [fp, #0x24] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x1, [fp, #0x28] ldr x2, [fp, #0x18] ldr w4, [fp, #0x24] mov x3, xzr mov w5, wzr mov w6, wzr movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 136 420: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,int](System.String) [Tier0, IL size=29, code size=136] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[int]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,int,int],int,bool,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] str x3, [fp, #0x30] str w4, [fp, #0x2C] str w5, [fp, #0x28] str w6, [fp, #0x24] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 str x4, [fp, #0x10] ldr x4, [fp, #0x18] ldr w6, [fp, #0x2C] str w6, [x4, #0x08] ldr x4, [fp, #0x18] ldr w6, [fp, #0x24] uxtb w6, w6 ldr w5, [fp, #0x28] uxtb w5, w5 ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x10] ldr x3, [fp, #0x38] movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x14, [fp, #0x48] add x14, x14, #48 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x48] ldr w1, [fp, #0x2C] str w1, [x0, #0x38] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 184 421: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[int]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,int,int],int,bool,bool) [Tier0, IL size=45, code size=184] ; Assembly listing for method BenchmarkDotNet.Jobs.InfrastructureMode:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #164 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x15, [fp, #0x28] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #164 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x15, [fp, #0x20] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 632 422: JIT compiled BenchmarkDotNet.Jobs.InfrastructureMode:.cctor() [Tier0, IL size=121, code size=632] ; Assembly listing for method BenchmarkDotNet.Toolchains.InProcess.Emit.InProcessEmitToolchain:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] mov w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] mov w1, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x15, [fp, #0x10] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 160 423: JIT compiled BenchmarkDotNet.Toolchains.InProcess.Emit.InProcessEmitToolchain:.cctor() [Tier0, IL size=23, code size=160] ; Assembly listing for method BenchmarkDotNet.Toolchains.InProcess.Emit.InProcessEmitToolchain:.ctor(bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x18] ldr x1, [fp, #0x18] ldr w2, [fp, #0x24] uxtb w2, w2 ldr x0, [fp, #0x28] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 100 424: JIT compiled BenchmarkDotNet.Toolchains.InProcess.Emit.InProcessEmitToolchain:.ctor(bool) [Tier0, IL size=13, code size=100] ; Assembly listing for method BenchmarkDotNet.Toolchains.InProcess.Emit.InProcessEmitToolchain:.ctor(System.TimeSpan,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str x1, [fp, #0x30] str w2, [fp, #0x2C] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr w2, [fp, #0x2C] uxtb w2, w2 ldr x0, [fp, #0x10] ldr x1, [fp, #0x30] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x38] ldr x4, [fp, #0x10] ldr x2, [fp, #0x20] ldr x3, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 232 425: JIT compiled BenchmarkDotNet.Toolchains.InProcess.Emit.InProcessEmitToolchain:.ctor(System.TimeSpan,bool) [Tier0, IL size=29, code size=232] ; Assembly listing for method BenchmarkDotNet.Toolchains.InProcess.Emit.InProcessEmitGenerator:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 426: JIT compiled BenchmarkDotNet.Toolchains.InProcess.Emit.InProcessEmitGenerator:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Toolchains.InProcess.Emit.InProcessEmitBuilder:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 427: JIT compiled BenchmarkDotNet.Toolchains.InProcess.Emit.InProcessEmitBuilder:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Toolchains.InProcess.Emit.InProcessEmitExecutor:.ctor(System.TimeSpan,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr x0, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #162 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x1, [x0] str x1, [fp, #0x20] G_M000_IG03: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] str x1, [x0, #0x10] ldr x0, [fp, #0x28] ldr w1, [fp, #0x1C] strb w1, [x0, #0x08] G_M000_IG04: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 160 428: JIT compiled BenchmarkDotNet.Toolchains.InProcess.Emit.InProcessEmitExecutor:.ctor(System.TimeSpan,bool) [Tier0, IL size=41, code size=160] ; Assembly listing for method BenchmarkDotNet.Toolchains.InProcess.Emit.InProcessEmitExecutor:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: fmov d0, #1.0000 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x0, [x1] fmov d0, #5.0000 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str x0, [x1] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 96 429: JIT compiled BenchmarkDotNet.Toolchains.InProcess.Emit.InProcessEmitExecutor:.cctor() [Tier0, IL size=39, code size=96] ; Assembly listing for method BenchmarkDotNet.Toolchains.Toolchain:.ctor(System.String,BenchmarkDotNet.Toolchains.IGenerator,BenchmarkDotNet.Toolchains.IBuilder,BenchmarkDotNet.Toolchains.IExecutor):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x1, [fp, #0x30] str x2, [fp, #0x28] str x3, [fp, #0x20] str x4, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x38] add x14, x14, #8 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x38] add x14, x14, #16 ldr x15, [fp, #0x28] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x38] add x14, x14, #24 ldr x15, [fp, #0x20] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x38] add x14, x14, #32 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 124 430: JIT compiled BenchmarkDotNet.Toolchains.Toolchain:.ctor(System.String,BenchmarkDotNet.Toolchains.IGenerator,BenchmarkDotNet.Toolchains.IBuilder,BenchmarkDotNet.Toolchains.IExecutor) [Tier0, IL size=36, code size=124] ; Assembly listing for method BenchmarkDotNet.Jobs.InfrastructureMode:.ctor(BenchmarkDotNet.Toolchains.IToolchain):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 76 431: JIT compiled BenchmarkDotNet.Jobs.InfrastructureMode:.ctor(BenchmarkDotNet.Toolchains.IToolchain) [Tier0, IL size=14, code size=76] ; Assembly listing for method BenchmarkDotNet.Jobs.InfrastructureMode:set_Toolchain(BenchmarkDotNet.Toolchains.IToolchain):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 104 432: JIT compiled BenchmarkDotNet.Jobs.InfrastructureMode:set_Toolchain(BenchmarkDotNet.Toolchains.IToolchain) [Tier0, IL size=13, code size=104] ; Assembly listing for method BenchmarkDotNet.Jobs.MetaMode:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 208 433: JIT compiled BenchmarkDotNet.Jobs.MetaMode:.cctor() [Tier0, IL size=46, code size=208] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateHiddenCharacteristic[bool](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[bool] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x0, [fp, #0x20] str x1, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 116 434: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateHiddenCharacteristic[bool](System.String) [Tier0, IL size=7, code size=116] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:CreateHidden[System.__Canon,bool](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[bool] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str wzr, [fp, #0x24] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0] bl CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE str x0, [fp, #0x18] str wzr, [fp, #0x24] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x1, [fp, #0x28] ldr x2, [fp, #0x18] ldr w4, [fp, #0x24] mov x3, xzr mov w5, wzr mov w6, #1 movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 136 435: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:CreateHidden[System.__Canon,bool](System.String) [Tier0, IL size=29, code size=136] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateIgnoreOnApplyCharacteristic[bool](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[bool] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x0, [fp, #0x20] str x1, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 116 436: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateIgnoreOnApplyCharacteristic[bool](System.String) [Tier0, IL size=7, code size=116] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:CreateIgnoreOnApply[System.__Canon,bool](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[bool] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str wzr, [fp, #0x24] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0] bl CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE str x0, [fp, #0x18] str wzr, [fp, #0x24] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x1, [fp, #0x28] ldr x2, [fp, #0x18] ldr w4, [fp, #0x24] mov x3, xzr mov w5, #1 mov w6, wzr movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 136 437: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:CreateIgnoreOnApply[System.__Canon,bool](System.String) [Tier0, IL size=29, code size=136] ; Assembly listing for method BenchmarkDotNet.Jobs.RunMode:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 mov w2, wzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E G_M000_IG03: movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x38] mov w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x38] mov w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x38] mov w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x38] mov w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x38] mov w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x30] mov w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x30] mov w1, #3 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x30] mov w1, #3 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x28] mov w1, #2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x28] mov w1, #10 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x28] mov w1, #15 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E G_M000_IG04: movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x20] mov w1, #3 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x20] mov w1, #15 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x20] mov w1, #100 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x18] mov w1, #4 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x18] mov w1, #30 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x18] mov w1, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG05: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 1868 438: JIT compiled BenchmarkDotNet.Jobs.RunMode:.cctor() [Tier0, IL size=410, code size=1868] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,int](System.String,int):BenchmarkDotNet.Characteristics.Characteristic`1[int] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] str w2, [fp, #0x24] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0] bl CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE str x0, [fp, #0x10] ldr x2, [fp, #0x10] ldr x1, [fp, #0x28] ldr x0, [fp, #0x18] ldr w4, [fp, #0x24] mov x3, xzr mov w5, wzr mov w6, wzr movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 132 439: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,int](System.String,int) [Tier0, IL size=21, code size=132] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[int]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,int,int],int,bool,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] str x3, [fp, #0x30] str w4, [fp, #0x2C] str w5, [fp, #0x28] str w6, [fp, #0x24] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 str x4, [fp, #0x10] ldr x4, [fp, #0x18] ldr w6, [fp, #0x2C] str w6, [x4, #0x08] ldr x4, [fp, #0x18] ldr w6, [fp, #0x24] uxtb w6, w6 ldr w5, [fp, #0x28] uxtb w5, w5 ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x10] ldr x3, [fp, #0x38] movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x14, [fp, #0x48] add x14, x14, #48 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x48] ldr w1, [fp, #0x2C] str w1, [x0, #0x38] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 184 440: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[int]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,int,int],int,bool,bool) [Tier0, IL size=45, code size=184] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[long](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[long] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x0, [fp, #0x20] str x1, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x20] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 116 441: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject`1[System.__Canon]:CreateCharacteristic[long](System.String) [Tier0, IL size=7, code size=116] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,long](System.String):BenchmarkDotNet.Characteristics.Characteristic`1[long] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0] bl CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE str x0, [fp, #0x18] str xzr, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x1, [fp, #0x28] ldr x2, [fp, #0x18] ldr x4, [fp, #0x20] mov x3, xzr mov w5, wzr mov w6, wzr movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 136 442: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:Create[System.__Canon,long](System.String) [Tier0, IL size=29, code size=136] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[long]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,long,long],long,bool,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] str x3, [fp, #0x30] str x4, [fp, #0x28] str w5, [fp, #0x24] str w6, [fp, #0x20] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 str x4, [fp, #0x10] ldr x4, [fp, #0x18] ldr x6, [fp, #0x28] str x6, [x4, #0x08] ldr x4, [fp, #0x18] ldr w6, [fp, #0x20] uxtb w6, w6 ldr w5, [fp, #0x24] uxtb w5, w5 ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x10] ldr x3, [fp, #0x38] movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr x14, [fp, #0x48] add x14, x14, #48 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x48] ldr x1, [fp, #0x28] str x1, [x0, #0x38] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 184 443: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[long]:.ctor(System.String,System.Type,System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,long,long],long,bool,bool) [Tier0, IL size=45, code size=184] ; Assembly listing for method BenchmarkDotNet.Jobs.RunMode:set_LaunchCount(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr w2, [fp, #0x24] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 104 444: JIT compiled BenchmarkDotNet.Jobs.RunMode:set_LaunchCount(int) [Tier0, IL size=13, code size=104] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[int]:set_Item(BenchmarkDotNet.Characteristics.CharacteristicObject,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] G_M000_IG02: ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] ldr w2, [fp, #0x1C] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 64 445: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[int]:set_Item(BenchmarkDotNet.Characteristics.CharacteristicObject,int) [Tier0, IL size=9, code size=64] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x2, [fp, #0x10] ldr w0, [fp, #0x1C] str w0, [x2, #0x08] ldr x2, [fp, #0x10] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 446: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],int) [Tier0, IL size=14, code size=96] ; Assembly listing for method BenchmarkDotNet.Jobs.RunMode:set_WarmupCount(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr w2, [fp, #0x24] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 104 447: JIT compiled BenchmarkDotNet.Jobs.RunMode:set_WarmupCount(int) [Tier0, IL size=13, code size=104] ; Assembly listing for method BenchmarkDotNet.Jobs.RunMode:set_IterationCount(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr w2, [fp, #0x24] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 104 448: JIT compiled BenchmarkDotNet.Jobs.RunMode:set_IterationCount(int) [Tier0, IL size=13, code size=104] ; Assembly listing for method BenchmarkDotNet.Jobs.RunMode:set_RunStrategy(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr w2, [fp, #0x24] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 104 449: JIT compiled BenchmarkDotNet.Jobs.RunMode:set_RunStrategy(int) [Tier0, IL size=13, code size=104] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[int]:set_Item(BenchmarkDotNet.Characteristics.CharacteristicObject,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] G_M000_IG02: ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] ldr w2, [fp, #0x1C] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 64 450: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[int]:set_Item(BenchmarkDotNet.Characteristics.CharacteristicObject,int) [Tier0, IL size=9, code size=64] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x2, [fp, #0x10] ldr w0, [fp, #0x1C] str w0, [x2, #0x08] ldr x2, [fp, #0x10] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 451: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],int) [Tier0, IL size=14, code size=96] ; Assembly listing for method BenchmarkDotNet.Jobs.RunMode:set_UnrollFactor(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr w2, [fp, #0x24] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 104 452: JIT compiled BenchmarkDotNet.Jobs.RunMode:set_UnrollFactor(int) [Tier0, IL size=13, code size=104] ; Assembly listing for method System.Linq.Enumerable:Intersect[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Collections.Generic.IEnumerable`1[System.__Canon]):System.Collections.Generic.IEnumerable`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] str x2, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x18] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x18] G_M000_IG05: ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] mov x3, xzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG06: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 128 453: JIT compiled System.Linq.Enumerable:Intersect[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Collections.Generic.IEnumerable`1[System.__Canon]) [Tier0, IL size=9, code size=128] ; Assembly listing for method System.Linq.Enumerable:Intersect[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Collections.Generic.IEnumerable`1[System.__Canon],System.Collections.Generic.IEqualityComparer`1[System.__Canon]):System.Collections.Generic.IEnumerable`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] str x2, [fp, #0x20] str x3, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x28] cbnz x0, G_M000_IG03 mov w0, #4 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x20] cbnz x0, G_M000_IG04 mov w0, #14 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x10] b G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG07: ldr x0, [fp, #0x10] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] ldr x3, [fp, #0x18] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG08: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 196 454: JIT compiled System.Linq.Enumerable:Intersect[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Collections.Generic.IEnumerable`1[System.__Canon],System.Collections.Generic.IEqualityComparer`1[System.__Canon]) [Tier0, IL size=28, code size=196] ; Assembly listing for method System.Linq.Enumerable:IntersectIterator[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Collections.Generic.IEnumerable`1[System.__Canon],System.Collections.Generic.IEqualityComparer`1[System.__Canon]):System.Collections.Generic.IEnumerable`1[System.__Canon] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x20] str x0, [fp, #0x48] str x0, [fp, #0x40] str x1, [fp, #0x38] str x2, [fp, #0x30] str x3, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x40] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x18] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x40] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x18] G_M000_IG05: ldr x0, [fp, #0x18] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] movn w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x20] add x14, x14, #56 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x20] add x14, x14, #24 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x20] add x14, x14, #40 ldr x15, [fp, #0x28] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x20] G_M000_IG06: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 192 455: JIT compiled System.Linq.Enumerable:IntersectIterator[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Collections.Generic.IEnumerable`1[System.__Canon],System.Collections.Generic.IEqualityComparer`1[System.__Canon]) [Tier0, IL size=29, code size=192] ; Assembly listing for method System.Linq.Enumerable+d__122`1[System.__Canon]:.ctor(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x18] ldr w1, [fp, #0x14] str w1, [x0, #0x50] bl System.Environment:get_CurrentManagedThreadId():int ldr x1, [fp, #0x18] str w0, [x1, #0x54] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 72 456: JIT compiled System.Linq.Enumerable+d__122`1[System.__Canon]:.ctor(int) [Tier0, IL size=25, code size=72] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:ApplyCore(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Collections.Generic.IEnumerable`1[BenchmarkDotNet.Characteristics.Characteristic]):BenchmarkDotNet.Characteristics.CharacteristicObject:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] add x3, sp, #96 str x3, [fp, #0x58] str x0, [fp, #0x50] str x1, [fp, #0x48] str x2, [fp, #0x40] G_M000_IG02: ldr x0, [fp, #0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov w0, #0xD1FFAB1E str w0, [fp, #0x18] ldr x0, [fp, #0x48] cbnz x0, G_M000_IG04 ldr x0, [fp, #0x50] G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG04: ldr x0, [fp, #0x40] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x38] G_M000_IG05: b G_M000_IG09 G_M000_IG06: ldr x0, [fp, #0x38] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x30] ldr x0, [fp, #0x48] ldr x0, [x0, #0x08] add x2, fp, #40 ldr x1, [fp, #0x30] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 cbz w0, G_M000_IG09 ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbz w0, G_M000_IG08 ldr x0, [fp, #0x50] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG09 ldr x0, [fp, #0x50] ldr x1, [fp, #0x30] ldr x2, [fp, #0x28] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x10] ldr x1, [fp, #0x10] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x20] ldr x0, [fp, #0x20] cbz x0, G_M000_IG07 ldr x0, [fp, #0x20] ldr wzr, [x0] bl System.Object:GetType():System.Type:this movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x28] G_M000_IG07: ldr x0, [fp, #0x50] ldr x1, [fp, #0x30] ldr x2, [fp, #0x28] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG09 G_M000_IG08: ldr x0, [fp, #0x50] ldr x1, [fp, #0x30] ldr x2, [fp, #0x28] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG09: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG11 G_M000_IG10: add x0, fp, #24 mov w1, #107 bl CORINFO_HELP_PATCHPOINT G_M000_IG11: ldr x0, [fp, #0x38] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG06 b G_M000_IG12 G_M000_IG12: ldr x0, [fp, #0x58] bl G_M000_IG16 G_M000_IG13: nop G_M000_IG14: ldr x0, [fp, #0x50] G_M000_IG15: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG16: stp fp, lr, [sp, #-0x20]! add x3, fp, #96 str x3, [sp, #0x18] G_M000_IG17: ldr x0, [fp, #0x38] cbz x0, G_M000_IG18 ldr x0, [fp, #0x38] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG18: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 596 457: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:ApplyCore(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Collections.Generic.IEnumerable`1[BenchmarkDotNet.Characteristics.Characteristic]) [Tier0, IL size=129, code size=596] ; Assembly listing for method System.Linq.Enumerable+d__122`1[System.__Canon]:System.Collections.Generic.IEnumerable.GetEnumerator():System.Collections.Generic.IEnumerator`1[System.__Canon]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str x0, [fp, #0x38] str x0, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x30] ldr w0, [x0, #0x50] cmn w0, #2 bne G_M000_IG03 ldr x0, [fp, #0x30] ldr w0, [x0, #0x54] str w0, [fp, #0x1C] bl System.Environment:get_CurrentManagedThreadId():int ldr w1, [fp, #0x1C] cmp w0, w1 bne G_M000_IG03 ldr x0, [fp, #0x30] str wzr, [x0, #0x50] ldr x0, [fp, #0x30] str x0, [fp, #0x28] b G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x30] ldr x0, [x0] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] mov w1, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x20] str x14, [fp, #0x28] G_M000_IG04: ldr x14, [fp, #0x30] ldr x15, [x14, #0x38] ldr x14, [fp, #0x28] add x14, x14, #48 bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x30] ldr x15, [x14, #0x18] ldr x14, [fp, #0x28] add x14, x14, #16 bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x30] ldr x15, [x14, #0x28] ldr x14, [fp, #0x28] add x14, x14, #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x28] G_M000_IG05: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 212 458: JIT compiled System.Linq.Enumerable+d__122`1[System.__Canon]:System.Collections.Generic.IEnumerable.GetEnumerator() [Tier0, IL size=79, code size=212] ; Assembly listing for method System.Linq.Enumerable+d__122`1[System.__Canon]:MoveNext():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x90]! mov fp, sp str xzr, [fp, #0x68] str xzr, [fp, #0x60] add x1, sp, #144 str x1, [fp, #0x88] str x0, [fp, #0x80] str x0, [fp, #0x78] G_M000_IG02: ldr x0, [fp, #0x78] ldr w0, [x0, #0x50] str w0, [fp, #0x70] mov w0, #0xD1FFAB1E str w0, [fp, #0x30] ldr w0, [fp, #0x70] cbz w0, G_M000_IG03 ldr w0, [fp, #0x70] cmp w0, #1 beq G_M000_IG14 str wzr, [fp, #0x74] b G_M000_IG18 G_M000_IG03: ldr x0, [fp, #0x78] movn w1, #0 str w1, [x0, #0x50] ldr x0, [fp, #0x78] ldr x0, [x0] str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x10] cbz x0, G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x28] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x10] str x0, [fp, #0x58] b G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x58] G_M000_IG06: ldr x0, [fp, #0x58] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x60] ldr x2, [fp, #0x78] ldr x2, [x2, #0x20] ldr x1, [fp, #0x78] ldr x1, [x1, #0x10] ldr x0, [fp, #0x60] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x14, [fp, #0x78] add x14, x14, #64 ldr x15, [fp, #0x60] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x78] ldr x0, [x0] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] cbz x0, G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] str x0, [fp, #0x50] b G_M000_IG09 G_M000_IG08: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x50] G_M000_IG09: ldr x0, [fp, #0x50] str x0, [fp, #0x48] ldr x0, [fp, #0x78] ldr x0, [x0, #0x30] ldr x11, [fp, #0x48] ldr x1, [fp, #0x48] ldr x1, [x1] blr x1 ldr x14, [fp, #0x78] add x14, x14, #72 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x78] movn w1, #2 str w1, [x0, #0x50] b G_M000_IG15 G_M000_IG10: ldr x0, [fp, #0x78] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x20] cbz x0, G_M000_IG12 G_M000_IG11: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x20] str x0, [fp, #0x40] b G_M000_IG13 G_M000_IG12: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x40] G_M000_IG13: ldr x0, [fp, #0x40] str x0, [fp, #0x38] ldr x0, [fp, #0x78] ldr x0, [x0, #0x48] ldr x11, [fp, #0x38] ldr x1, [fp, #0x38] ldr x1, [x1] blr x1 str x0, [fp, #0x68] ldr x0, [fp, #0x78] ldr x0, [x0, #0x40] ldr x1, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG15 ldr x14, [fp, #0x78] add x14, x14, #8 ldr x15, [fp, #0x68] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x78] mov w1, #1 str w1, [x0, #0x50] mov w1, #1 str w1, [fp, #0x74] b G_M000_IG18 G_M000_IG14: ldr x0, [fp, #0x78] movn w1, #2 str w1, [x0, #0x50] G_M000_IG15: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG17 G_M000_IG16: add x0, fp, #48 mov w1, #130 bl CORINFO_HELP_PATCHPOINT G_M000_IG17: ldr x0, [fp, #0x78] ldr x0, [x0, #0x48] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG10 ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x78] str xzr, [x0, #0x48] str wzr, [fp, #0x74] b G_M000_IG18 G_M000_IG18: ldr w0, [fp, #0x74] G_M000_IG19: ldp fp, lr, [sp], #0x90 ret lr G_M000_IG20: stp fp, lr, [sp, #-0x20]! add x3, fp, #144 str x3, [sp, #0x18] G_M000_IG21: ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG22: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 756 459: JIT compiled System.Linq.Enumerable+d__122`1[System.__Canon]:MoveNext() [Tier0, IL size=169, code size=756] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject+<>c:b__24_2(BenchmarkDotNet.Characteristics.Characteristic):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cmp w0, #0 cset x0, eq G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 60 460: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject+<>c:b__24_2(BenchmarkDotNet.Characteristics.Characteristic) [Tier0, IL size=10, code size=60] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:get_IgnoreOnApply():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldrb w0, [x0, #0x28] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 461: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:get_IgnoreOnApply() [Tier0, IL size=7, code size=28] ; Assembly listing for method System.Linq.Enumerable+d__122`1[System.__Canon]:System.Collections.Generic.IEnumerator.get_Current():System.__Canon:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 462: JIT compiled System.Linq.Enumerable+d__122`1[System.__Canon]:System.Collections.Generic.IEnumerator.get_Current() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:HasValue(BenchmarkDotNet.Characteristics.Characteristic):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] add x2, fp, #24 ldr x1, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 cbz w0, G_M000_IG04 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] cmp x0, x1 cset x0, ne G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: mov w0, wzr G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 112 463: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:HasValue(BenchmarkDotNet.Characteristics.Characteristic) [Tier0, IL size=30, code size=112] ; Assembly listing for method System.Linq.Enumerable+d__122`1[System.__Canon]:<>m__Finally1():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movn w11, #0 str w11, [x0, #0x50] ldr x0, [fp, #0x18] ldr x0, [x0, #0x48] cbz x0, G_M000_IG03 ldr x0, [fp, #0x18] ldr x0, [x0, #0x48] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 72 464: JIT compiled System.Linq.Enumerable+d__122`1[System.__Canon]:<>m__Finally1() [Tier0, IL size=27, code size=72] ; Assembly listing for method System.Linq.Enumerable+d__122`1[System.__Canon]:System.IDisposable.Dispose():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp add x1, sp, #48 str x1, [fp, #0x28] str x0, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x20] ldr w0, [x0, #0x50] str w0, [fp, #0x1C] ldr w0, [fp, #0x1C] cmn w0, #3 beq G_M000_IG03 ldr w0, [fp, #0x1C] cmp w0, #1 bne G_M000_IG06 G_M000_IG03: b G_M000_IG04 G_M000_IG04: ldr x0, [fp, #0x28] bl G_M000_IG07 G_M000_IG05: nop G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG07: stp fp, lr, [sp, #-0x20]! add x3, fp, #48 str x3, [sp, #0x18] G_M000_IG08: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG09: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 124 465: JIT compiled System.Linq.Enumerable+d__122`1[System.__Canon]:System.IDisposable.Dispose() [Tier0, IL size=27, code size=124] ; Assembly listing for method System.Nullable`1[System.Guid]:.ctor(System.Guid):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x18] str x2, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] ldr w1, [fp, #0x18] str w1, [x0, #0x04] ldr x1, [fp, #0x1C] str x1, [x0, #0x08] ldr w1, [fp, #0x24] str w1, [x0, #0x10] ldr x0, [fp, #0x28] mov w1, #1 strb w1, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 68 466: JIT compiled System.Nullable`1[System.Guid]:.ctor(System.Guid) [Tier0, IL size=15, code size=68] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[System.Nullable`1[System.Guid]]:set_Item(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Nullable`1[System.Guid]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] G_M000_IG02: ldr x0, [fp, #0x40] str x0, [fp, #0x18] ldr x0, [fp, #0x48] str x0, [fp, #0x10] ldr x0, [fp, #0x38] ldp x1, x2, [x0] stp x1, x2, [fp, #0x20] ldr w1, [x0, #0x10] str w1, [fp, #0x30] ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] add x2, fp, #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 108 467: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[System.Nullable`1[System.Guid]]:set_Item(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Nullable`1[System.Guid]) [Tier0, IL size=9, code size=108] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue[System.Nullable`1[System.Guid]](BenchmarkDotNet.Characteristics.Characteristic`1[System.Nullable`1[System.Guid]],System.Nullable`1[System.Guid]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_BOX_NULLABLE str x0, [fp, #0x10] ldr x2, [fp, #0x10] ldr x1, [fp, #0x20] ldr x0, [fp, #0x28] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 88 468: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue[System.Nullable`1[System.Guid]](BenchmarkDotNet.Characteristics.Characteristic`1[System.Nullable`1[System.Guid]],System.Nullable`1[System.Guid]) [Tier0, IL size=14, code size=88] ; Assembly listing for method Perfolizer.Horology.TimeInterval:.ctor(double):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str d0, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr d16, [fp, #0x10] str d16, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 36 469: JIT compiled Perfolizer.Horology.TimeInterval:.ctor(double) [Tier0, IL size=8, code size=36] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval]:set_Item(BenchmarkDotNet.Characteristics.CharacteristicObject,Perfolizer.Horology.TimeInterval):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str d0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] ldr d0, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 64 470: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval]:set_Item(BenchmarkDotNet.Characteristics.CharacteristicObject,Perfolizer.Horology.TimeInterval) [Tier0, IL size=9, code size=64] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue[Perfolizer.Horology.TimeInterval](BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval],Perfolizer.Horology.TimeInterval):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] str d0, [fp, #0x18] G_M000_IG02: add x1, fp, #24 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_BOX str x0, [fp, #0x10] ldr x2, [fp, #0x10] ldr x1, [fp, #0x20] ldr x0, [fp, #0x28] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 88 471: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue[Perfolizer.Horology.TimeInterval](BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval],Perfolizer.Horology.TimeInterval) [Tier0, IL size=14, code size=88] ; Assembly listing for method BenchmarkDotNet.Jobs.Job:get_DisplayInfo():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG04 ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x2, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 252 472: JIT compiled BenchmarkDotNet.Jobs.Job:get_DisplayInfo() [Tier0, IL size=56, code size=252] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveId(BenchmarkDotNet.Characteristics.CharacteristicObject,System.String):System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x38] str x1, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG04 ldr x0, [fp, #0x30] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x38] ldr x2, [fp, #0x18] ldr x2, [x2] ldr x2, [x2, #0x40] ldr x2, [x2, #0x20] blr x2 str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr w0, [x0, #0x08] cbnz w0, G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x28] G_M000_IG05: ldr x0, [fp, #0x28] G_M000_IG06: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 284 473: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveId(BenchmarkDotNet.Characteristics.CharacteristicObject,System.String) [Tier0, IL size=61, code size=284] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicSetPresenter:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x28] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x20] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x10] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 288 474: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicSetPresenter:.cctor() [Tier0, IL size=41, code size=288] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+DefaultPresenter:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 475: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+DefaultPresenter:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicSetPresenter:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 476: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicSetPresenter:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+DisplayPresenter:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 477: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+DisplayPresenter:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+FolderPresenter:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 478: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+FolderPresenter:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+SourceCodePresenter:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 479: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+SourceCodePresenter:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+DisplayPresenter:ToPresentation(BenchmarkDotNet.Characteristics.CharacteristicObject):System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] str x0, [fp, #0x48] str x1, [fp, #0x40] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] str x14, [fp, #0x38] ldr x14, [fp, #0x38] add x14, x14, #8 ldr x15, [fp, #0x40] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x1, [fp, #0x38] ldr x1, [x1, #0x08] ldr x0, [fp, #0x48] mov w2, wzr ldr x3, [fp, #0x48] ldr x3, [x3] ldr x3, [x3, #0x40] ldr x3, [x3, #0x28] blr x3 str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x2, [fp, #0x20] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x30] ldr x1, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 288 480: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+DisplayPresenter:ToPresentation(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=56, code size=288] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+DisplayPresenter+<>c__DisplayClass2_0:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 481: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+DisplayPresenter+<>c__DisplayClass2_0:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicSetPresenter:GetPresentableCharacteristics(BenchmarkDotNet.Characteristics.CharacteristicObject,bool):System.Collections.Generic.IEnumerable`1[BenchmarkDotNet.Characteristics.Characteristic]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str w2, [fp, #0x3C] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x28] str x0, [fp, #0x30] ldr x0, [fp, #0x30] ldr w1, [fp, #0x3C] strb w1, [x0, #0x08] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x40] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x2, [fp, #0x20] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 240 482: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicSetPresenter:GetPresentableCharacteristics(BenchmarkDotNet.Characteristics.CharacteristicObject,bool) [Tier0, IL size=37, code size=240] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+<>c__DisplayClass5_0:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 483: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+<>c__DisplayClass5_0:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:GetCharacteristicsWithValues():System.Collections.Generic.IEnumerable`1[BenchmarkDotNet.Characteristics.Characteristic]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] str x0, [fp, #0x58] G_M000_IG02: ldr x0, [fp, #0x58] ldr x1, [fp, #0x58] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x20] blr x1 cbnz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x1, [fp, #0x58] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x2, [fp, #0x20] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG04: ldr x0, [fp, #0x58] ldr x0, [x0, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x48] ldr x0, [fp, #0x40] str x0, [fp, #0x38] ldr x0, [fp, #0x48] str x0, [fp, #0x30] ldr x0, [fp, #0x48] cbnz x0, G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr x0, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x15, [fp, #0x28] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x2, [fp, #0x28] str x2, [fp, #0x30] G_M000_IG05: ldr x2, [fp, #0x30] ldr x1, [fp, #0x38] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x50] ldr x0, [fp, #0x50] G_M000_IG06: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 428 484: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:GetCharacteristicsWithValues() [Tier0, IL size=82, code size=428] ; Assembly listing for method System.Linq.Enumerable+WhereArrayIterator`1[System.__Canon]:Where(System.Func`2[System.__Canon,bool]):System.Collections.Generic.IEnumerable`1[System.__Canon]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x0, [fp, #0x40] str x1, [fp, #0x38] G_M000_IG02: ldr x0, [fp, #0x40] ldr x0, [x0] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x10] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x10] str x0, [fp, #0x30] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x30] G_M000_IG05: ldr x0, [fp, #0x40] ldr x0, [x0, #0x18] str x0, [fp, #0x28] ldr x0, [fp, #0x40] ldr x0, [x0] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x1, [fp, #0x40] ldr x1, [x1, #0x20] ldr x0, [fp, #0x30] ldr x2, [fp, #0x38] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x18] ldr x2, [fp, #0x18] ldr x1, [fp, #0x28] ldr x0, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x20] G_M000_IG06: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 224 485: JIT compiled System.Linq.Enumerable+WhereArrayIterator`1[System.__Canon]:Where(System.Func`2[System.__Canon,bool]) [Tier0, IL size=24, code size=224] ; Assembly listing for method System.Linq.Utilities:CombinePredicates[System.__Canon](System.Func`2[System.__Canon,bool],System.Func`2[System.__Canon,bool]):System.Func`2[System.__Canon,bool] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str xzr, [fp, #0x38] str xzr, [fp, #0x30] str xzr, [fp, #0x20] str x0, [fp, #0x58] str x0, [fp, #0x50] str x1, [fp, #0x48] str x2, [fp, #0x40] G_M000_IG02: ldr x0, [fp, #0x50] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x50] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x28] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x28] G_M000_IG05: ldr x0, [fp, #0x28] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x30] str x14, [fp, #0x38] ldr x14, [fp, #0x38] add x14, x14, #8 ldr x15, [fp, #0x48] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x38] add x14, x14, #16 ldr x15, [fp, #0x40] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x50] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] cbz x0, G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x50] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] str x0, [fp, #0x18] b G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x18] G_M000_IG08: ldr x0, [fp, #0x18] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x20] G_M000_IG09: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 296 486: JIT compiled System.Linq.Utilities:CombinePredicates[System.__Canon](System.Func`2[System.__Canon,bool],System.Func`2[System.__Canon,bool]) [Tier0, IL size=33, code size=296] ; Assembly listing for method System.Linq.Utilities+<>c__DisplayClass1_0`1[System.__Canon]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 487: JIT compiled System.Linq.Utilities+<>c__DisplayClass1_0`1[System.__Canon]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Linq.Utilities+<>c__DisplayClass1_0`1[System.__Canon]:b__0(System.__Canon):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] ldr x1, [fp, #0x20] ldr x2, [fp, #0x18] ldr x2, [x2, #0x18] blr x2 cbz w0, G_M000_IG04 ldr x0, [fp, #0x28] ldr x0, [x0, #0x10] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x08] ldr x1, [fp, #0x20] ldr x2, [fp, #0x10] ldr x2, [x2, #0x18] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: mov w0, wzr G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 120 488: JIT compiled System.Linq.Utilities+<>c__DisplayClass1_0`1[System.__Canon]:b__0(System.__Canon) [Tier0, IL size=29, code size=120] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+<>c__DisplayClass5_0:b__0(BenchmarkDotNet.Characteristics.Characteristic):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x1, [fp, #0x18] ldrb w1, [x1, #0x08] ldr x0, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 489: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+<>c__DisplayClass5_0:b__0(BenchmarkDotNet.Characteristics.Characteristic) [Tier0, IL size=13, code size=56] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicHelper:IsPresentableCharacteristic(BenchmarkDotNet.Characteristics.Characteristic,bool):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbnz w0, G_M000_IG06 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbnz w0, G_M000_IG06 ldr w0, [fp, #0x14] uxtb w0, w0 cbnz w0, G_M000_IG04 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cmp w0, #0 cset x0, eq G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: mov w0, #1 G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG06: mov w0, wzr G_M000_IG07: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 160 490: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicHelper:IsPresentableCharacteristic(BenchmarkDotNet.Characteristics.Characteristic,bool) [Tier0, IL size=33, code size=160] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:get_DontShowInSummary():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldrb w0, [x0, #0x29] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 491: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:get_DontShowInSummary() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+DisplayPresenter+<>c__DisplayClass2_0:b__0(BenchmarkDotNet.Characteristics.Characteristic):System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x38] str x1, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x38] ldr x1, [x1, #0x08] ldr x2, [fp, #0x30] ldr x3, [fp, #0x20] ldr x3, [x3] ldr x3, [x3, #0x40] ldr x3, [x3, #0x20] blr x3 str x0, [fp, #0x18] ldr x2, [fp, #0x18] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 188 492: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+DisplayPresenter+<>c__DisplayClass2_0:b__0(BenchmarkDotNet.Characteristics.Characteristic) [Tier0, IL size=34, code size=188] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+DisplayPresenter:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 ldr x15, [x14] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 68 493: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicSetPresenter+DisplayPresenter:.cctor() [Tier0, IL size=11, code size=68] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicPresenter:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x28] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x20] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x10] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 288 494: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicPresenter:.cctor() [Tier0, IL size=41, code size=288] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicPresenter+DefaultCharacteristicPresenter:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 495: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicPresenter+DefaultCharacteristicPresenter:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicPresenter:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 496: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicPresenter:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicPresenter+FolderCharacteristicPresenter:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 497: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicPresenter+FolderCharacteristicPresenter:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicPresenter+SourceCodeCharacteristicPresenter:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 498: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicPresenter+SourceCodeCharacteristicPresenter:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicPresenter+DefaultCharacteristicPresenter:ToPresentation(BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic):System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x38] str x1, [fp, #0x30] str x2, [fp, #0x28] G_M000_IG02: ldr x1, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] cmp x1, x0 bne G_M000_IG04 ldr x1, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x20] ldr x0, [fp, #0x20] cbz x0, G_M000_IG04 ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG04: ldr x0, [fp, #0x30] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbnz w0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG05: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG06: ldr x0, [fp, #0x28] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x38] ldr x2, [fp, #0x28] ldr x3, [fp, #0x38] ldr x3, [x3] ldr x3, [x3, #0x40] ldr x3, [x3, #0x28] blr x3 G_M000_IG07: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 272 499: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicPresenter+DefaultCharacteristicPresenter:ToPresentation(BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic) [Tier0, IL size=55, code size=272] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic:get_Item(BenchmarkDotNet.Characteristics.CharacteristicObject):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 500: JIT compiled BenchmarkDotNet.Characteristics.Characteristic:get_Item(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=8, code size=56] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[System.Nullable`1[System.Guid]]:ResolveValueCore(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Object):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xB0]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] str xzr, [x9, #0x80] str x0, [fp, #0xA8] str x1, [fp, #0xA0] str x2, [fp, #0x98] G_M000_IG02: ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz x0, G_M000_IG04 ldr x0, [fp, #0xA8] ldr x1, [fp, #0xA0] ldr x2, [fp, #0x98] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x40] ldr x2, [fp, #0x40] add x0, fp, #72 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_UNBOX_NULLABLE add x1, fp, #72 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_BOX_NULLABLE G_M000_IG03: ldp fp, lr, [sp], #0xB0 ret lr G_M000_IG04: ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x90] ldr x0, [fp, #0xA8] ldr x1, [fp, #0xA0] ldr x2, [fp, #0x98] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x38] ldr x2, [fp, #0x38] add x0, fp, #120 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_UNBOX_NULLABLE ldr x0, [fp, #0x90] str x0, [fp, #0x18] ldr x0, [fp, #0xA0] str x0, [fp, #0x10] ldp x0, x1, [fp, #0x78] stp x0, x1, [fp, #0x20] ldr w0, [fp, #0x88] str w0, [fp, #0x30] ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] ldr x1, [fp, #0x10] add x2, fp, #32 add x8, fp, #96 ldr x3, [fp, #0x18] ldr x3, [x3, #0x18] blr x3 add x1, fp, #96 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_BOX_NULLABLE G_M000_IG05: ldp fp, lr, [sp], #0xB0 ret lr ; Total bytes of code 344 501: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[System.Nullable`1[System.Guid]]:ResolveValueCore(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Object) [Tier0, IL size=58, code size=344] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[System.Nullable`1[System.Guid]]:get_Resolver():System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,System.Nullable`1[System.Guid],System.Nullable`1[System.Guid]]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 502: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[System.Nullable`1[System.Guid]]:get_Resolver() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicPresenter+DefaultCharacteristicPresenter:ToPresentation(System.Object,BenchmarkDotNet.Characteristics.Characteristic):System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x38] str x1, [fp, #0x30] str x2, [fp, #0x28] G_M000_IG02: ldr x1, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz x0, G_M000_IG04 ldr x1, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x20] ldr x0, [fp, #0x20] cbz x0, G_M000_IG04 ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG04: ldr x1, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] cmp x1, x0 bne G_M000_IG06 ldr x1, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz x0, G_M000_IG06 ldr x1, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [x0] str x0, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0x14] ldr w1, [fp, #0x14] ldr x0, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG05: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG06: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG07: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 352 503: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicPresenter+DefaultCharacteristicPresenter:ToPresentation(System.Object,BenchmarkDotNet.Characteristics.Characteristic) [Tier0, IL size=67, code size=352] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicPresenter+DefaultCharacteristicPresenter:ToPresentation(System.Object):System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x0, [fp, #0x48] G_M000_IG02: ldr x1, [fp, #0x48] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x40] ldr x0, [fp, #0x40] str x0, [fp, #0x38] ldr x0, [fp, #0x40] cbnz x0, G_M000_IG03 str xzr, [fp, #0x30] b G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] str x2, [fp, #0x18] ldr x2, [fp, #0x18] ldr x0, [fp, #0x38] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 mov x1, xzr ldr x3, [x11] blr x3 str x0, [fp, #0x30] G_M000_IG04: ldr x0, [fp, #0x30] str x0, [fp, #0x28] ldr x0, [fp, #0x30] cbnz x0, G_M000_IG07 ldr x0, [fp, #0x48] cbnz x0, G_M000_IG05 str xzr, [fp, #0x20] b G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x48] ldr x1, [fp, #0x48] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x08] blr x1 str x0, [fp, #0x20] G_M000_IG06: ldr x0, [fp, #0x20] str x0, [fp, #0x28] ldr x0, [fp, #0x20] cbnz x0, G_M000_IG07 movz x0, #8 movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x28] G_M000_IG07: ldr x0, [fp, #0x28] G_M000_IG08: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 272 504: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicPresenter+DefaultCharacteristicPresenter:ToPresentation(System.Object) [Tier0, IL size=50, code size=272] ; Assembly listing for method BenchmarkDotNet.Helpers.DefaultCultureInfo:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x1, [fp, #0x28] ldr x1, [x1] ldr x1, [x1, #0x58] ldr x1, [x1] blr x1 str x0, [fp, #0x20] ldr x1, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x1, [x1] ldr x1, [x1, #0x50] ldr x1, [x1, #0x10] blr x1 str x0, [fp, #0x10] ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 228 505: JIT compiled BenchmarkDotNet.Helpers.DefaultCultureInfo:.cctor() [Tier0, IL size=41, code size=228] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval]:ResolveValueCore(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Object):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #32 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] str x0, [fp, #0x58] str x1, [fp, #0x50] str x2, [fp, #0x48] G_M000_IG02: ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz x0, G_M000_IG04 ldr x0, [fp, #0x58] ldr x1, [fp, #0x50] ldr x2, [fp, #0x48] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x30] ldr x1, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x28] ldr x1, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_BOX G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG04: ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] ldr x0, [fp, #0x58] ldr x1, [fp, #0x50] ldr x2, [fp, #0x48] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x20] ldr x1, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr d0, [x0] str d0, [fp, #0x18] ldr d0, [fp, #0x18] ldr x1, [fp, #0x50] ldr x0, [fp, #0x40] ldr x0, [x0, #0x08] ldr x2, [fp, #0x40] ldr x2, [x2, #0x18] blr x2 ldr x0, [fp, #0x38] str d0, [x0, #0x08] ldr x0, [fp, #0x38] G_M000_IG05: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 344 506: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval]:ResolveValueCore(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Object) [Tier0, IL size=58, code size=344] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval]:get_Resolver():System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,Perfolizer.Horology.TimeInterval,Perfolizer.Horology.TimeInterval]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 507: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval]:get_Resolver() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Horology.TimeInterval:ToString():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #85 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 mov x3, xzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 108 508: JIT compiled Perfolizer.Horology.TimeInterval:ToString() [Tier0, IL size=18, code size=108] ; Assembly listing for method Perfolizer.Common.DefaultCultureInfo:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x1, [fp, #0x28] ldr x1, [x1] ldr x1, [x1, #0x58] ldr x1, [x1] blr x1 str x0, [fp, #0x20] ldr x1, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x1, [x1] ldr x1, [x1, #0x50] ldr x1, [x1, #0x10] blr x1 str x0, [fp, #0x10] ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 228 509: JIT compiled Perfolizer.Common.DefaultCultureInfo:.cctor() [Tier0, IL size=41, code size=228] ; Assembly listing for method Perfolizer.Horology.TimeInterval:ToString(System.Globalization.CultureInfo,System.String,Perfolizer.Common.UnitPresentation):System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] str x3, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x28] ldr x4, [fp, #0x10] ldr x2, [fp, #0x20] ldr x3, [fp, #0x18] mov x1, xzr movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 72 510: JIT compiled Perfolizer.Horology.TimeInterval:ToString(System.Globalization.CultureInfo,System.String,Perfolizer.Common.UnitPresentation) [Tier0, IL size=11, code size=72] ; Assembly listing for method Perfolizer.Horology.TimeInterval:ToString(Perfolizer.Horology.TimeUnit,System.Globalization.CultureInfo,System.String,Perfolizer.Common.UnitPresentation):System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] str xzr, [x9, #0x60] str x0, [fp, #0x98] str x1, [fp, #0x90] str x2, [fp, #0x88] str x3, [fp, #0x80] str x4, [fp, #0x78] G_M000_IG02: ldr x0, [fp, #0x90] str x0, [fp, #0x60] ldr x0, [fp, #0x90] cbnz x0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, #1 bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x38] ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x30] ldr x0, [fp, #0x38] mov w1, wzr ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG10 add x0, x0, x1, LSL #3 add x0, x0, #16 ldr d16, [fp, #0x30] str d16, [x0] ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x60] G_M000_IG03: ldr x0, [fp, #0x60] str x0, [fp, #0x90] ldr x0, [fp, #0x88] str x0, [fp, #0x58] ldr x0, [fp, #0x88] cbnz x0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x58] G_M000_IG04: ldr x0, [fp, #0x58] str x0, [fp, #0x88] ldr x0, [fp, #0x80] str x0, [fp, #0x50] ldr x0, [fp, #0x80] cbnz x0, G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x50] G_M000_IG05: ldr x0, [fp, #0x50] str x0, [fp, #0x80] ldr x0, [fp, #0x78] str x0, [fp, #0x48] ldr x0, [fp, #0x78] cbnz x0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #87 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x48] G_M000_IG06: ldr x0, [fp, #0x48] str x0, [fp, #0x78] ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #82 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x20] ldr d0, [fp, #0x28] ldr x0, [fp, #0x20] ldr x1, [fp, #0x90] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str d0, [fp, #0x70] ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbz w0, G_M000_IG08 ldr x0, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x40] ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str w0, [fp, #0x1C] ldr w1, [fp, #0x1C] ldr x0, [fp, #0x40] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 str x0, [fp, #0x68] add x0, fp, #112 ldr x1, [fp, #0x80] ldr x2, [fp, #0x88] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x2, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG07: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG08: add x0, fp, #112 ldr x1, [fp, #0x80] ldr x2, [fp, #0x88] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG09: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG10: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 708 511: JIT compiled Perfolizer.Horology.TimeInterval:ToString(Perfolizer.Horology.TimeUnit,System.Globalization.CultureInfo,System.String,Perfolizer.Common.UnitPresentation) [Tier0, IL size=141, code size=708] ; Assembly listing for method Perfolizer.Horology.TimeInterval:get_Nanoseconds():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 512: JIT compiled Perfolizer.Horology.TimeInterval:get_Nanoseconds() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Horology.TimeUnit:GetBestTimeUnit(double[]):Perfolizer.Horology.TimeUnit ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x0, [fp, #0x48] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x20] ldr x0, [fp, #0x48] ldr w0, [x0, #0x08] cbnz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #82 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG04: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #82 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x38] str wzr, [fp, #0x34] b G_M000_IG08 G_M000_IG05: ldr x0, [fp, #0x38] ldr w1, [fp, #0x34] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG12 add x0, x0, x1, LSL #3 add x0, x0, #16 ldr x0, [x0] str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 mov x1, #0xD1FFAB1E mul x0, x0, x1 scvtf d16, x0 ldr d17, [fp, #0x40] fcmp d16, d17 ble G_M000_IG07 ldr x0, [fp, #0x28] G_M000_IG06: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG07: ldr w0, [fp, #0x34] add w0, w0, #1 str w0, [fp, #0x34] G_M000_IG08: ldr w0, [fp, #0x20] sub w0, w0, #1 str w0, [fp, #0x20] ldr w0, [fp, #0x20] cmp w0, #0 bgt G_M000_IG10 G_M000_IG09: add x0, fp, #32 mov w1, #54 bl CORINFO_HELP_PATCHPOINT G_M000_IG10: ldr w0, [fp, #0x34] ldr x1, [fp, #0x38] ldr w1, [x1, #0x08] cmp w0, w1 blt G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #82 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x18] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG11: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG12: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 428 513: JIT compiled Perfolizer.Horology.TimeUnit:GetBestTimeUnit(double[]) [Tier0, IL size=71, code size=428] ; Assembly listing for method System.Linq.Enumerable:Min(System.Collections.Generic.IEnumerable`1[double]):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 514: JIT compiled System.Linq.Enumerable:Min(System.Collections.Generic.IEnumerable`1[double]) [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Linq.Enumerable:MinFloat[double](System.Collections.Generic.IEnumerable`1[double]):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp str xzr, [fp, #0x48] str xzr, [fp, #0x30] add x1, sp, #112 str x1, [fp, #0x68] str x0, [fp, #0x60] G_M000_IG02: mov w1, #0xD1FFAB1E str w1, [fp, #0x18] add x1, fp, #72 ldr x0, [fp, #0x60] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG12 add x0, fp, #72 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG03: ldr w0, [fp, #0x50] cmp w0, #0 bls G_M000_IG30 ldr x0, [fp, #0x48] ldr d16, [x0] str d16, [fp, #0x58] mov w0, #1 str w0, [fp, #0x44] b G_M000_IG08 G_M000_IG04: ldr w0, [fp, #0x44] ldr w1, [fp, #0x50] cmp w0, w1 bhs G_M000_IG30 ldr x0, [fp, #0x48] ldr w1, [fp, #0x44] mov w1, w1 lsl x1, x1, #3 ldr d0, [x0, x1] str d0, [fp, #0x38] ldr d0, [fp, #0x38] ldr d1, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG05 ldr d0, [fp, #0x38] str d0, [fp, #0x58] b G_M000_IG07 G_M000_IG05: ldr d0, [fp, #0x38] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG07 ldr d0, [fp, #0x38] G_M000_IG06: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG07: ldr w0, [fp, #0x44] add w0, w0, #1 str w0, [fp, #0x44] G_M000_IG08: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG10 G_M000_IG09: add x0, fp, #24 mov w1, #95 bl CORINFO_HELP_PATCHPOINT G_M000_IG10: ldr w0, [fp, #0x44] ldr w1, [fp, #0x50] cmp w0, w1 blo G_M000_IG04 ldr d0, [fp, #0x58] G_M000_IG11: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG12: ldr x0, [fp, #0x60] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x30] G_M000_IG13: ldr x0, [fp, #0x30] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG14 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG14: ldr x0, [fp, #0x30] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str d0, [fp, #0x58] ldr d0, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG17 ldr d16, [fp, #0x58] str d16, [fp, #0x28] b G_M000_IG20 G_M000_IG15: ldr x0, [fp, #0x30] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str d0, [fp, #0x20] ldr d0, [fp, #0x20] ldr d1, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG16 ldr d0, [fp, #0x20] str d0, [fp, #0x58] b G_M000_IG17 G_M000_IG16: ldr d0, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG17 ldr d16, [fp, #0x20] str d16, [fp, #0x28] b G_M000_IG24 G_M000_IG17: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG19 G_M000_IG18: add x0, fp, #24 mov w1, #207 bl CORINFO_HELP_PATCHPOINT G_M000_IG19: ldr x0, [fp, #0x30] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG15 b G_M000_IG22 G_M000_IG20: ldr x0, [fp, #0x68] bl G_M000_IG31 G_M000_IG21: b G_M000_IG28 G_M000_IG22: ldr x0, [fp, #0x68] bl G_M000_IG31 G_M000_IG23: b G_M000_IG26 G_M000_IG24: ldr x0, [fp, #0x68] bl G_M000_IG31 G_M000_IG25: b G_M000_IG28 G_M000_IG26: ldr d0, [fp, #0x58] G_M000_IG27: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG28: ldr d0, [fp, #0x28] G_M000_IG29: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG30: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 G_M000_IG31: stp fp, lr, [sp, #-0x20]! add x3, fp, #112 str x3, [sp, #0x18] G_M000_IG32: ldr x0, [fp, #0x30] cbz x0, G_M000_IG33 ldr x0, [fp, #0x30] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG33: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 796 515: JIT compiled System.Linq.Enumerable:MinFloat[double](System.Collections.Generic.IEnumerable`1[double]) [Tier0, IL size=235, code size=796] ; Assembly listing for method System.Linq.Enumerable:TryGetSpan[double](System.Collections.Generic.IEnumerable`1[double],byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x0, [fp, #0x58] str x1, [fp, #0x50] G_M000_IG02: ldr x0, [fp, #0x58] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: mov w0, #1 str w0, [fp, #0x4C] ldr x0, [fp, #0x58] ldr wzr, [x0] bl System.Object:GetType():System.Type:this movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 cmp x0, x1 bne G_M000_IG04 ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] str x1, [fp, #0x20] ldr x14, [fp, #0x50] add x13, fp, #24 bl CORINFO_HELP_ASSIGN_BYREF ldr x12, [x13], #0x08 str x12, [x14], #0x08 b G_M000_IG06 G_M000_IG04: ldr x0, [fp, #0x58] ldr wzr, [x0] bl System.Object:GetType():System.Type:this movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 cmp x0, x1 bne G_M000_IG05 ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x38] str x1, [fp, #0x40] ldr x0, [fp, #0x38] ldr x1, [fp, #0x40] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x28] str x1, [fp, #0x30] ldr x14, [fp, #0x50] add x13, fp, #40 bl CORINFO_HELP_ASSIGN_BYREF ldr x12, [x13], #0x08 str x12, [x14], #0x08 b G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x50] stp xzr, xzr, [x0] str wzr, [fp, #0x4C] G_M000_IG06: ldr w0, [fp, #0x4C] G_M000_IG07: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 308 516: JIT compiled System.Linq.Enumerable:TryGetSpan[double](System.Collections.Generic.IEnumerable`1[double],byref) [Tier0, IL size=112, code size=308] ; Assembly listing for method Perfolizer.Horology.TimeUnit:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp add x9, fp, #48 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x68] ldr x0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 mov x3, #1 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x15, [fp, #0x68] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x60] ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 mov x3, #0xD1FFAB1E movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x15, [fp, #0x60] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x58] ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #15 LSL #16 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x15, [fp, #0x58] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x50] ldr x0, [fp, #0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x15, [fp, #0x50] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 mov x3, #60 mul x3, x0, x3 str x3, [fp, #0x28] ldr x3, [fp, #0x28] ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x15, [fp, #0x48] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 mov x3, #60 mul x3, x0, x3 str x3, [fp, #0x20] ldr x3, [fp, #0x20] ldr x0, [fp, #0x40] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x15, [fp, #0x40] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 G_M000_IG03: movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 mov x3, #24 mul x3, x0, x3 str x3, [fp, #0x18] ldr x3, [fp, #0x18] ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x15, [fp, #0x38] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, #7 bl CORINFO_HELP_NEWARR_1_OBJ str x0, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr x0, [fp, #0x30] mov x1, xzr bl CORINFO_HELP_ARRADDR_ST movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr x0, [fp, #0x30] mov x1, #1 bl CORINFO_HELP_ARRADDR_ST movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr x0, [fp, #0x30] mov x1, #2 bl CORINFO_HELP_ARRADDR_ST movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr x0, [fp, #0x30] mov x1, #3 bl CORINFO_HELP_ARRADDR_ST movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr x0, [fp, #0x30] mov x1, #4 bl CORINFO_HELP_ARRADDR_ST movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr x0, [fp, #0x30] mov x1, #5 bl CORINFO_HELP_ARRADDR_ST movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr x0, [fp, #0x30] mov x1, #6 bl CORINFO_HELP_ARRADDR_ST ldr x15, [fp, #0x30] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG04: ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 1080 517: JIT compiled Perfolizer.Horology.TimeUnit:.cctor() [Tier0, IL size=270, code size=1080] ; Assembly listing for method Perfolizer.Horology.TimeUnit:.ctor(System.String,System.String,long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] str x3, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] add x14, x14, #8 ldr x15, [fp, #0x20] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x28] add x14, x14, #16 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x28] ldr x1, [fp, #0x10] str x1, [x0, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 100 518: JIT compiled Perfolizer.Horology.TimeUnit:.ctor(System.String,System.String,long) [Tier0, IL size=28, code size=100] ; Assembly listing for method Perfolizer.Horology.TimeUnit:get_NanosecondAmount():long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 519: JIT compiled Perfolizer.Horology.TimeUnit:get_NanosecondAmount() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Common.UnitPresentation:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] mov w1, #1 mov w2, wzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] mov w1, wzr mov w2, wzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x15, [fp, #0x10] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 168 520: JIT compiled Perfolizer.Common.UnitPresentation:.cctor() [Tier0, IL size=25, code size=168] ; Assembly listing for method Perfolizer.Common.UnitPresentation:.ctor(bool,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] str w2, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w1, [fp, #0x14] uxtb w1, w1 ldr x0, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x18] ldr w1, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 112 521: JIT compiled Perfolizer.Common.UnitPresentation:.ctor(bool,int) [Tier0, IL size=21, code size=112] ; Assembly listing for method Perfolizer.Common.UnitPresentation:set_IsVisible(bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr x0, [fp, #0x18] ldr w1, [fp, #0x14] strb w1, [x0, #0x0C] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 36 522: JIT compiled Perfolizer.Common.UnitPresentation:set_IsVisible(bool) [Tier0, IL size=8, code size=36] ; Assembly listing for method Perfolizer.Common.UnitPresentation:set_MinUnitWidth(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr x0, [fp, #0x18] ldr w1, [fp, #0x14] str w1, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 36 523: JIT compiled Perfolizer.Common.UnitPresentation:set_MinUnitWidth(int) [Tier0, IL size=8, code size=36] ; Assembly listing for method Perfolizer.Horology.TimeUnit:Convert(double,Perfolizer.Horology.TimeUnit,Perfolizer.Horology.TimeUnit):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x30] str x1, [fp, #0x28] str d0, [fp, #0x38] G_M000_IG02: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 scvtf d16, x0 ldr d17, [fp, #0x38] fmul d16, d16, d17 str d16, [fp, #0x20] ldr x0, [fp, #0x28] str x0, [fp, #0x18] ldr x0, [fp, #0x28] cbnz x0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, #1 bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x10] ldr x0, [fp, #0x10] mov w1, wzr ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG05 add x0, x0, x1, LSL #3 add x0, x0, #16 ldr d16, [fp, #0x38] str d16, [x0] ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] G_M000_IG03: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 scvtf d0, x0 ldr d16, [fp, #0x20] fdiv d0, d16, d0 G_M000_IG04: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG05: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 232 524: JIT compiled Perfolizer.Horology.TimeUnit:Convert(double,Perfolizer.Horology.TimeUnit,Perfolizer.Horology.TimeUnit) [Tier0, IL size=37, code size=232] ; Assembly listing for method Perfolizer.Common.UnitPresentation:get_IsVisible():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldrb w0, [x0, #0x0C] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 525: JIT compiled Perfolizer.Common.UnitPresentation:get_IsVisible() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Horology.TimeUnit:get_Name():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 526: JIT compiled Perfolizer.Horology.TimeUnit:get_Name() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Common.UnitPresentation:get_MinUnitWidth():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 527: JIT compiled Perfolizer.Common.UnitPresentation:get_MinUnitWidth() [Tier0, IL size=7, code size=28] ; Assembly listing for method System.Number:FormatNumber[ushort](byref,byref,int,System.Globalization.NumberFormatInfo) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! mov fp, sp add x9, fp, #32 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] str x0, [fp, #0x98] str x1, [fp, #0x90] str w2, [fp, #0x8C] str x3, [fp, #0x80] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x18] ldr x0, [fp, #0x90] ldrb w0, [x0, #0x08] cbnz w0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x58] b G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x60] ldr x0, [fp, #0x80] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 ldr x1, [fp, #0x60] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG14 add x0, x1, x0, LSL #3 add x0, x0, #16 ldr x0, [x0] str x0, [fp, #0x58] G_M000_IG04: ldr x0, [fp, #0x58] str x0, [fp, #0x78] ldr x0, [fp, #0x78] str x0, [fp, #0x70] str wzr, [fp, #0x6C] b G_M000_IG10 G_M000_IG05: ldr x0, [fp, #0x70] ldr w1, [fp, #0x6C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG14 add x0, x0, x1, LSL #1 add x0, x0, #12 ldrh w0, [x0] str w0, [fp, #0x68] ldr w0, [fp, #0x68] cmp w0, #35 beq G_M000_IG06 ldr w0, [fp, #0x68] cmp w0, #45 beq G_M000_IG07 b G_M000_IG08 G_M000_IG06: ldr x0, [fp, #0x80] ldr x0, [x0, #0x08] str x0, [fp, #0x40] ldr x0, [fp, #0x80] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x48] str x1, [fp, #0x50] ldr x0, [fp, #0x80] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x30] str x1, [fp, #0x38] ldr x4, [fp, #0x48] ldr x5, [fp, #0x50] ldr x6, [fp, #0x30] ldr x7, [fp, #0x38] ldr x0, [fp, #0x98] ldr x1, [fp, #0x90] ldr w2, [fp, #0x8C] ldr x3, [fp, #0x40] movz x8, #0xD1FFAB1E movk x8, #0xD1FFAB1E LSL #16 movk x8, #0xD1FFAB1E LSL #32 ldr x8, [x8] blr x8 b G_M000_IG09 G_M000_IG07: ldr x0, [fp, #0x80] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] str x1, [fp, #0x28] ldr x1, [fp, #0x20] ldr x2, [fp, #0x28] ldr x0, [fp, #0x98] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG09 G_M000_IG08: ldr w0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x14] ldr w1, [fp, #0x14] ldr x0, [fp, #0x98] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG09: ldr w0, [fp, #0x6C] add w0, w0, #1 str w0, [fp, #0x6C] G_M000_IG10: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG12 G_M000_IG11: add x0, fp, #24 mov w1, #118 bl CORINFO_HELP_PATCHPOINT G_M000_IG12: ldr x0, [fp, #0x70] ldr w0, [x0, #0x08] ldr w1, [fp, #0x6C] cmp w0, w1 bgt G_M000_IG05 G_M000_IG13: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG14: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 604 528: JIT compiled System.Number:FormatNumber[ushort](byref,byref,int,System.Globalization.NumberFormatInfo) [Tier0, IL size=128, code size=604] ; Assembly listing for method System.Globalization.NumberFormatInfo:NumberDecimalSeparatorTChar[ushort]():System.ReadOnlySpan`1[ushort]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] str x0, [fp, #0x38] G_M000_IG02: b G_M000_IG03 G_M000_IG03: ldr x0, [fp, #0x38] ldr x0, [x0, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x20] str x1, [fp, #0x28] ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x10] str x1, [fp, #0x18] ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] G_M000_IG04: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 120 529: JIT compiled System.Globalization.NumberFormatInfo:NumberDecimalSeparatorTChar[ushort]() [Tier0, IL size=95, code size=120] ; Assembly listing for method System.Runtime.InteropServices.MemoryMarshal:Cast[ushort,ushort](System.ReadOnlySpan`1[ushort]):System.ReadOnlySpan`1[ushort] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x40] str x1, [fp, #0x48] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: mov w0, #2 str w0, [fp, #0x3C] mov w0, #2 str w0, [fp, #0x38] ldr w0, [fp, #0x48] str w0, [fp, #0x34] ldr w0, [fp, #0x3C] ldr w1, [fp, #0x38] cmp w0, w1 bne G_M000_IG05 ldr w0, [fp, #0x34] str w0, [fp, #0x30] b G_M000_IG07 G_M000_IG05: ldr w0, [fp, #0x3C] cmp w0, #1 bne G_M000_IG06 ldr w0, [fp, #0x34] ldr w1, [fp, #0x38] cmp w1, #0 beq G_M000_IG09 udiv w0, w0, w1 str w0, [fp, #0x30] b G_M000_IG07 G_M000_IG06: ldr w0, [fp, #0x34] mov w0, w0 ldr w1, [fp, #0x3C] mov w1, w1 mul x0, x0, x1 ldr w1, [fp, #0x38] mov w1, w1 cmp x1, #0 beq G_M000_IG09 udiv x0, x0, x1 str x0, [fp, #0x28] ldr x0, [fp, #0x28] tst x0, #0xD1FFAB1E bne G_M000_IG10 str w0, [fp, #0x30] G_M000_IG07: stp xzr, xzr, [fp, #0x18] ldr x0, [fp, #0x40] ldr x1, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x10] ldr x1, [fp, #0x10] add x0, fp, #24 ldr w2, [fp, #0x30] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] ldr x1, [fp, #0x20] G_M000_IG08: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG09: bl CORINFO_HELP_THROWDIVZERO G_M000_IG10: bl CORINFO_HELP_OVERFLOW brk_windows #0 ; Total bytes of code 384 530: JIT compiled System.Runtime.InteropServices.MemoryMarshal:Cast[ushort,ushort](System.ReadOnlySpan`1[ushort]) [Tier0, IL size=114, code size=384] ; Assembly listing for method System.Globalization.NumberFormatInfo:NumberGroupSeparatorTChar[ushort]():System.ReadOnlySpan`1[ushort]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] str x0, [fp, #0x38] G_M000_IG02: b G_M000_IG03 G_M000_IG03: ldr x0, [fp, #0x38] ldr x0, [x0, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x20] str x1, [fp, #0x28] ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x10] str x1, [fp, #0x18] ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] G_M000_IG04: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 120 531: JIT compiled System.Globalization.NumberFormatInfo:NumberGroupSeparatorTChar[ushort]() [Tier0, IL size=95, code size=120] ; Assembly listing for method System.Number:FormatFixed[ushort](byref,byref,int,int[],System.ReadOnlySpan`1[ushort],System.ReadOnlySpan`1[ushort]) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! mov fp, sp add x9, fp, #80 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] str xzr, [x9, #0x80] str x0, [fp, #0xD1FFAB1E] str x1, [fp, #0xD1FFAB1E] str w2, [fp, #0xD1FFAB1E] str x3, [fp, #0xD1FFAB1E] str x4, [fp, #0xD1FFAB1E] str x5, [fp, #0xD1FFAB1E] str x6, [fp, #0xD1FFAB1E] str x7, [fp, #0xD1FFAB1E] G_M000_IG02: ldr x0, [fp, #0xD1FFAB1E] ldr w0, [x0, #0x04] str w0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD1FFAB1E] mov w0, #0xD1FFAB1E str w0, [fp, #0x30] ldr w0, [fp, #0xD1FFAB1E] cmp w0, #0 ble G_M000_IG31 ldr x0, [fp, #0xD1FFAB1E] cbz x0, G_M000_IG26 str wzr, [fp, #0xFC] ldr w0, [fp, #0xD1FFAB1E] str w0, [fp, #0xF8] str wzr, [fp, #0xF4] ldr x0, [fp, #0xD1FFAB1E] ldr w0, [x0, #0x08] cbz w0, G_M000_IG11 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xFC] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG44 add x0, x0, x1, LSL #2 add x0, x0, #16 ldr w0, [x0] str w0, [fp, #0xE4] b G_M000_IG05 G_M000_IG03: ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xFC] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG44 add x0, x0, x1, LSL #2 add x0, x0, #16 ldr w0, [x0] str w0, [fp, #0xF4] ldr w0, [fp, #0xF4] cbz w0, G_M000_IG08 ldr w0, [fp, #0xF8] ldr w1, [fp, #0xD1FFAB1E] add w0, w0, w1 str w0, [fp, #0xF8] ldr w0, [fp, #0xFC] ldr x1, [fp, #0xD1FFAB1E] ldr w1, [x1, #0x08] sub w1, w1, #1 cmp w0, w1 bge G_M000_IG04 ldr w0, [fp, #0xFC] add w0, w0, #1 str w0, [fp, #0xFC] G_M000_IG04: ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xFC] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG44 add x0, x0, x1, LSL #2 add x0, x0, #16 ldr w0, [x0] ldr w1, [fp, #0xE4] add w0, w0, w1 str w0, [fp, #0xE4] ldr w0, [fp, #0xE4] ldr w1, [fp, #0xF8] orr w0, w0, w1 tbz w0, #31, G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG05: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG07 G_M000_IG06: add x0, fp, #48 mov w1, #96 bl CORINFO_HELP_PATCHPOINT G_M000_IG07: ldr w0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xE4] cmp w0, w1 bgt G_M000_IG03 G_M000_IG08: ldr w0, [fp, #0xE4] cbz w0, G_M000_IG09 ldr x0, [fp, #0xD1FFAB1E] mov w1, wzr ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG44 add x0, x0, x1, LSL #2 add x0, x0, #16 ldr w0, [x0] str w0, [fp, #0x38] b G_M000_IG10 G_M000_IG09: str wzr, [fp, #0x38] G_M000_IG10: ldr w0, [fp, #0x38] str w0, [fp, #0xF4] G_M000_IG11: str wzr, [fp, #0xFC] str wzr, [fp, #0xF0] ldr x0, [fp, #0xD1FFAB1E] ldr w0, [x0] str w0, [fp, #0xEC] ldr w0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xEC] cmp w0, w1 blt G_M000_IG12 ldr w0, [fp, #0xEC] str w0, [fp, #0x64] b G_M000_IG13 G_M000_IG12: ldr w0, [fp, #0xD1FFAB1E] str w0, [fp, #0x64] G_M000_IG13: ldr w0, [fp, #0x64] str w0, [fp, #0xE8] ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x50] str x1, [fp, #0x58] ldr x0, [fp, #0x50] ldr x1, [fp, #0x58] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xD0] ldr x0, [fp, #0xD0] str x0, [fp, #0x28] ldr x0, [fp, #0x28] str x0, [fp, #0xD8] ldr x0, [fp, #0xD8] ldr w1, [fp, #0xF8] sxtw x1, w1 mov w2, #2 sxtw x2, w2 mul x1, x1, x2 add x0, x0, x1 mov w1, #2 sxtw x1, w1 sub x0, x0, x1 str x0, [fp, #0xC8] ldr w0, [fp, #0xD1FFAB1E] sub w0, w0, #1 str w0, [fp, #0xC4] b G_M000_IG23 G_M000_IG14: ldr x0, [fp, #0xC8] str x0, [fp, #0xB8] ldr x0, [fp, #0xB8] mov w1, #2 sxtw x1, w1 sub x0, x0, x1 str x0, [fp, #0xC8] ldr x0, [fp, #0xB8] str x0, [fp, #0x48] ldr w0, [fp, #0xC4] ldr w1, [fp, #0xE8] cmp w0, w1 blt G_M000_IG15 ldr x0, [fp, #0x48] str x0, [fp, #0x40] mov w0, #48 str w0, [fp, #0x3C] b G_M000_IG16 G_M000_IG15: ldr x0, [fp, #0x48] str x0, [fp, #0x40] ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xC4] ldrb w0, [x0, w1, SXTW #2] str w0, [fp, #0x3C] G_M000_IG16: ldr w0, [fp, #0x3C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x40] strh w0, [x1] ldr w0, [fp, #0xF4] cmp w0, #0 ble G_M000_IG22 ldr w0, [fp, #0xF0] add w0, w0, #1 str w0, [fp, #0xF0] ldr w0, [fp, #0xF0] ldr w1, [fp, #0xF4] cmp w0, w1 bne G_M000_IG22 ldr w0, [fp, #0xC4] cbz w0, G_M000_IG22 ldr w0, [fp, #0xD1FFAB1E] sub w0, w0, #1 str w0, [fp, #0xB4] b G_M000_IG18 G_M000_IG17: ldr x0, [fp, #0xC8] str x0, [fp, #0xB8] ldr x0, [fp, #0xB8] mov w1, #2 sxtw x1, w1 sub x0, x0, x1 str x0, [fp, #0xC8] ldr w0, [fp, #0xB4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG44 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xB4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] ldr x1, [fp, #0xB8] strh w0, [x1] ldr w0, [fp, #0xB4] sub w0, w0, #1 str w0, [fp, #0xB4] G_M000_IG18: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG20 G_M000_IG19: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG20: ldr w0, [fp, #0xB4] tbz w0, #31, G_M000_IG17 ldr w0, [fp, #0xFC] ldr x1, [fp, #0xD1FFAB1E] ldr w1, [x1, #0x08] sub w1, w1, #1 cmp w0, w1 bge G_M000_IG21 ldr w0, [fp, #0xFC] add w0, w0, #1 str w0, [fp, #0xFC] ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xFC] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG44 add x0, x0, x1, LSL #2 add x0, x0, #16 ldr w0, [x0] str w0, [fp, #0xF4] G_M000_IG21: str wzr, [fp, #0xF0] G_M000_IG22: ldr w0, [fp, #0xC4] sub w0, w0, #1 str w0, [fp, #0xC4] G_M000_IG23: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG25 G_M000_IG24: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG25: ldr w0, [fp, #0xC4] tbz w0, #31, G_M000_IG14 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xE8] sxtw x1, w1 add x0, x0, x1 str x0, [fp, #0xD1FFAB1E] str xzr, [fp, #0xD0] b G_M000_IG32 G_M000_IG26: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG28 G_M000_IG27: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG28: ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x80] ldr x0, [fp, #0xD1FFAB1E] ldrb w0, [x0] cbnz w0, G_M000_IG29 ldr x0, [fp, #0x80] str x0, [fp, #0x70] mov w0, #48 str w0, [fp, #0x6C] b G_M000_IG30 G_M000_IG29: ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x78] ldr x0, [fp, #0xD1FFAB1E] mov w1, #1 mov w1, w1 add x0, x0, x1 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0x80] str x0, [fp, #0x70] ldr x0, [fp, #0x78] ldrb w0, [x0] str w0, [fp, #0x6C] G_M000_IG30: ldr w0, [fp, #0x6C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x24] ldr w1, [fp, #0x24] ldr x0, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [fp, #0xD1FFAB1E] sub w0, w0, #1 str w0, [fp, #0x68] ldr w0, [fp, #0xD1FFAB1E] sub w0, w0, #1 str w0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0x68] cmp w0, #0 bgt G_M000_IG26 b G_M000_IG32 G_M000_IG31: mov w0, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x20] ldr w1, [fp, #0x20] ldr x0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG32: ldr w1, [fp, #0xD1FFAB1E] cmp w1, #0 ble G_M000_IG43 ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr w0, [fp, #0xD1FFAB1E] tbz w0, #31, G_M000_IG40 ldr w0, [fp, #0xD1FFAB1E] cmp w0, #0 ble G_M000_IG40 ldr w0, [fp, #0xD1FFAB1E] neg w0, w0 ldr w1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0xB0] str wzr, [fp, #0xAC] b G_M000_IG34 G_M000_IG33: mov w0, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x1C] ldr w1, [fp, #0x1C] ldr x0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [fp, #0xAC] add w0, w0, #1 str w0, [fp, #0xAC] G_M000_IG34: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG36 G_M000_IG35: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG36: ldr w0, [fp, #0xAC] ldr w1, [fp, #0xB0] cmp w0, w1 blt G_M000_IG33 ldr w0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xB0] add w0, w0, w1 str w0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xB0] sub w0, w0, w1 str w0, [fp, #0xD1FFAB1E] b G_M000_IG40 G_M000_IG37: ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xA0] ldr x0, [fp, #0xD1FFAB1E] ldrb w0, [x0] cbnz w0, G_M000_IG38 ldr x0, [fp, #0xA0] str x0, [fp, #0x90] mov w0, #48 str w0, [fp, #0x8C] b G_M000_IG39 G_M000_IG38: ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x98] ldr x0, [fp, #0xD1FFAB1E] mov w1, #1 mov w1, w1 add x0, x0, x1 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xA0] str x0, [fp, #0x90] ldr x0, [fp, #0x98] ldrb w0, [x0] str w0, [fp, #0x8C] G_M000_IG39: ldr w0, [fp, #0x8C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x18] ldr w1, [fp, #0x18] ldr x0, [fp, #0x90] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [fp, #0xD1FFAB1E] sub w0, w0, #1 str w0, [fp, #0xD1FFAB1E] G_M000_IG40: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG42 G_M000_IG41: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG42: ldr w0, [fp, #0xD1FFAB1E] cmp w0, #0 bgt G_M000_IG37 G_M000_IG43: ldp fp, lr, [sp], #0xD1FFAB1E ret lr G_M000_IG44: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 1940 532: JIT compiled System.Number:FormatFixed[ushort](byref,byref,int,int[],System.ReadOnlySpan`1[ushort],System.ReadOnlySpan`1[ushort]) [Tier0, IL size=542, code size=1940] ; Assembly listing for method System.Collections.Generic.ValueListBuilder`1[ushort]:AppendSpan(int):System.Span`1[ushort]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x0, [fp, #0x48] str w1, [fp, #0x44] G_M000_IG02: ldr x0, [fp, #0x48] ldr w0, [x0, #0x08] str w0, [fp, #0x40] ldr x0, [fp, #0x48] G_M000_IG03: ldp x1, x2, [x0, #0x10] stp x1, x2, [fp, #0x30] G_M000_IG04: ldr w0, [fp, #0x40] mov w0, w0 ldr w1, [fp, #0x44] mov w1, w1 add x0, x0, x1 ldr w1, [fp, #0x38] mov w1, w1 cmp x0, x1 bhi G_M000_IG06 ldr w0, [fp, #0x40] ldr w1, [fp, #0x44] add w0, w0, w1 ldr x1, [fp, #0x48] str w0, [x1, #0x08] add x0, fp, #48 ldr w1, [fp, #0x40] ldr w2, [fp, #0x44] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x10] str x1, [fp, #0x18] ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] G_M000_IG05: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG06: ldr x0, [fp, #0x48] ldr w1, [fp, #0x44] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x20] str x1, [fp, #0x28] ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] G_M000_IG07: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 220 533: JIT compiled System.Collections.Generic.ValueListBuilder`1[ushort]:AppendSpan(int) [Tier0, IL size=56, code size=220] ; Assembly listing for method System.Collections.Generic.ValueListBuilder`1[ushort]:Append(System.ReadOnlySpan`1[ushort]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x38] str x1, [fp, #0x28] str x2, [fp, #0x30] G_M000_IG02: ldr x1, [fp, #0x38] ldr w1, [x1, #0x08] str w1, [fp, #0x24] ldr x1, [fp, #0x38] G_M000_IG03: ldp x0, x2, [x1, #0x10] stp x0, x2, [fp, #0x10] G_M000_IG04: ldr w1, [fp, #0x30] cmp w1, #1 bne G_M000_IG06 ldr w1, [fp, #0x24] ldr w2, [fp, #0x18] cmp w1, w2 bhs G_M000_IG06 ldr w1, [fp, #0x24] ldr w2, [fp, #0x18] cmp w1, w2 bhs G_M000_IG08 ldr x1, [fp, #0x10] ldr w2, [fp, #0x24] mov w2, w2 lsl x2, x2, #1 add x1, x1, x2 ldr w2, [fp, #0x30] cmp w2, #0 bls G_M000_IG08 ldr x2, [fp, #0x28] ldrh w2, [x2] strh w2, [x1] ldr w1, [fp, #0x24] add w1, w1, #1 ldr x2, [fp, #0x38] str w1, [x2, #0x08] G_M000_IG05: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG06: ldr x1, [fp, #0x28] ldr x2, [fp, #0x30] ldr x0, [fp, #0x38] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG07: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG08: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 208 534: JIT compiled System.Collections.Generic.ValueListBuilder`1[ushort]:Append(System.ReadOnlySpan`1[ushort]) [Tier0, IL size=78, code size=208] ; Assembly listing for method System.Collections.Generic.ValueListBuilder`1[ushort]:Append(ushort):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: ldr x1, [fp, #0x28] ldr w1, [x1, #0x08] str w1, [fp, #0x20] ldr x1, [fp, #0x28] G_M000_IG03: ldp x0, x2, [x1, #0x10] stp x0, x2, [fp, #0x10] G_M000_IG04: ldr w1, [fp, #0x20] ldr w0, [fp, #0x18] cmp w1, w0 bhs G_M000_IG06 ldr w1, [fp, #0x20] ldr w0, [fp, #0x18] cmp w1, w0 bhs G_M000_IG08 ldr x1, [fp, #0x10] ldr w0, [fp, #0x20] mov w0, w0 lsl x0, x0, #1 ldr w2, [fp, #0x24] strh w2, [x1, x0] ldr w1, [fp, #0x20] add w1, w1, #1 ldr x0, [fp, #0x28] str w1, [x0, #0x08] G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG06: ldr w1, [fp, #0x24] uxth w1, w1 ldr x0, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG07: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG08: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 172 535: JIT compiled System.Collections.Generic.ValueListBuilder`1[ushort]:Append(ushort) [Tier0, IL size=56, code size=172] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[int]:ResolveValueCore(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Object):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] G_M000_IG02: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz x0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x38] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x20] ldr x1, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [x0] ldr x1, [fp, #0x28] str w0, [x1, #0x08] ldr x0, [fp, #0x28] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG04: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x38] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x18] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w2, [x0] str w2, [fp, #0x14] ldr w2, [fp, #0x14] ldr x1, [fp, #0x40] ldr x0, [fp, #0x30] ldr x0, [x0, #0x08] ldr x3, [fp, #0x30] ldr x3, [x3, #0x18] blr x3 ldr x1, [fp, #0x28] str w0, [x1, #0x08] ldr x0, [fp, #0x28] G_M000_IG05: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 356 536: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[int]:ResolveValueCore(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Object) [Tier0, IL size=58, code size=356] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[int]:get_Resolver():System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,int,int]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 537: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[int]:get_Resolver() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon]:get_FallbackValue():System.__Canon:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x38] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 538: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon]:get_FallbackValue() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Jobs.Job:get_ResolvedId():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr x0, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG04 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 120 539: JIT compiled BenchmarkDotNet.Jobs.Job:get_ResolvedId() [Tier0, IL size=27, code size=120] ; Assembly listing for method BenchmarkDotNet.Jobs.JobIdGenerator:GenerateRandomId(BenchmarkDotNet.Jobs.Job):System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str x0, [fp, #0x68] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x1, [fp, #0x68] ldr x2, [fp, #0x28] ldr x2, [x2] ldr x2, [x2, #0x40] ldr x2, [x2, #0x20] blr x2 str x0, [fp, #0x60] mov w0, #0xD1FFAB1E str w0, [fp, #0x30] ldr x0, [fp, #0x60] movz x1, #8 movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG03: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] ldr x0, [fp, #0x60] ldr x1, [fp, #0x60] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x18] blr x1 str w0, [fp, #0x24] ldr w1, [fp, #0x24] ldr x0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x38] str x0, [fp, #0x58] movz x0, #8 movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x50] str wzr, [fp, #0x4C] b G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x58] mov w1, #26 ldr x2, [fp, #0x58] ldr x2, [x2] ldr x2, [x2, #0x40] ldr x2, [x2, #0x28] blr x2 add w0, w0, #65 uxth w0, w0 str w0, [fp, #0x40] add x0, fp, #64 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x50] ldr w1, [fp, #0x4C] add w1, w1, #1 str w1, [fp, #0x4C] G_M000_IG06: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG08 G_M000_IG07: add x0, fp, #48 mov w1, #85 bl CORINFO_HELP_PATCHPOINT G_M000_IG08: ldr w0, [fp, #0x4C] cmp w0, #6 blt G_M000_IG05 ldr x1, [fp, #0x50] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG09: ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 464 540: JIT compiled BenchmarkDotNet.Jobs.JobIdGenerator:GenerateRandomId(BenchmarkDotNet.Jobs.Job) [Tier0, IL size=101, code size=464] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:Validate(BenchmarkDotNet.Jobs.Job):System.Collections.Generic.IEnumerable`1[BenchmarkDotNet.Validators.ValidationError] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] movn w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x10] add x14, x14, #24 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 92 541: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo:Validate(BenchmarkDotNet.Jobs.Job) [Tier0, IL size=15, code size=92] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+d__55:.ctor(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x18] ldr w1, [fp, #0x14] str w1, [x0, #0x20] bl System.Environment:get_CurrentManagedThreadId():int ldr x1, [fp, #0x18] str w0, [x1, #0x24] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 72 542: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+d__55:.ctor(int) [Tier0, IL size=25, code size=72] ; Assembly listing for method BenchmarkDotNet.Validators.ValidationErrorReporter:ReportIfAny(System.Collections.Generic.IEnumerable`1[BenchmarkDotNet.Validators.ValidationError],BenchmarkDotNet.Engines.IHost):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str wzr, [fp, #0x34] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x10] add x2, sp, #80 str x2, [fp, #0x48] str x0, [fp, #0x40] str x1, [fp, #0x38] G_M000_IG02: str wzr, [fp, #0x34] ldr x0, [fp, #0x40] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x28] mov w0, #0xD1FFAB1E str w0, [fp, #0x18] G_M000_IG03: b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x28] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x38] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 mov w0, #1 str w0, [fp, #0x34] G_M000_IG05: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG07 G_M000_IG06: add x0, fp, #24 mov w1, #32 bl CORINFO_HELP_PATCHPOINT G_M000_IG07: ldr x0, [fp, #0x28] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG04 b G_M000_IG08 G_M000_IG08: ldr x0, [fp, #0x48] bl G_M000_IG12 G_M000_IG09: nop G_M000_IG10: ldr w0, [fp, #0x34] G_M000_IG11: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG12: stp fp, lr, [sp, #-0x20]! add x3, fp, #80 str x3, [sp, #0x18] G_M000_IG13: ldr x0, [fp, #0x28] cbz x0, G_M000_IG14 ldr x0, [fp, #0x28] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG14: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 324 543: JIT compiled BenchmarkDotNet.Validators.ValidationErrorReporter:ReportIfAny(System.Collections.Generic.IEnumerable`1[BenchmarkDotNet.Validators.ValidationError],BenchmarkDotNet.Engines.IHost) [Tier0, IL size=54, code size=324] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+d__55:System.Collections.Generic.IEnumerable.GetEnumerator():System.Collections.Generic.IEnumerator`1[BenchmarkDotNet.Validators.ValidationError]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] ldr w0, [x0, #0x20] cmn w0, #2 bne G_M000_IG03 ldr x0, [fp, #0x28] ldr w0, [x0, #0x24] str w0, [fp, #0x14] bl System.Environment:get_CurrentManagedThreadId():int ldr w1, [fp, #0x14] cmp w0, w1 bne G_M000_IG03 ldr x0, [fp, #0x28] str wzr, [x0, #0x20] ldr x0, [fp, #0x28] str x0, [fp, #0x20] b G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] mov w1, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x18] str x14, [fp, #0x20] G_M000_IG04: ldr x14, [fp, #0x28] ldr x15, [x14, #0x18] ldr x14, [fp, #0x20] add x14, x14, #16 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x20] G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 172 544: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+d__55:System.Collections.Generic.IEnumerable.GetEnumerator() [Tier0, IL size=55, code size=172] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+d__55:MoveNext():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str x0, [fp, #0x68] G_M000_IG02: ldr x0, [fp, #0x68] ldr w0, [x0, #0x20] str w0, [fp, #0x64] ldr w0, [fp, #0x64] cmp w0, #2 bhi G_M000_IG03 ldr w0, [fp, #0x64] mov w0, w0 adr x1, [@RWD00] ldr w1, [x1, x0, LSL #2] adr x2, [G_M000_IG02] add x1, x1, x2 br x1 G_M000_IG03: mov w0, wzr G_M000_IG04: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG05: ldr x0, [fp, #0x68] movn w1, #0 str w1, [x0, #0x20] ldr x0, [fp, #0x68] ldr x0, [x0, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cmp w0, #2 bne G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbnz w0, G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] mov w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 mov x3, xzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x14, [fp, #0x68] add x14, x14, #8 ldr x15, [fp, #0x20] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x68] mov w1, #1 str w1, [x0, #0x20] mov w0, #1 G_M000_IG06: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG07: ldr x0, [fp, #0x68] movn w1, #0 str w1, [x0, #0x20] G_M000_IG08: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x58] ldr x0, [fp, #0x68] ldr x0, [x0, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cmp w0, #1 bne G_M000_IG11 ldr x1, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz x0, G_M000_IG11 add x0, fp, #48 mov w1, #51 mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #48 ldr x2, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x2, [fp, #0x18] ldr x0, [fp, #0x28] mov w1, #1 mov x3, xzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x14, [fp, #0x68] add x14, x14, #8 ldr x15, [fp, #0x28] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x68] mov w1, #2 str w1, [x0, #0x20] mov w0, #1 G_M000_IG09: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG10: ldr x0, [fp, #0x68] movn w1, #0 str w1, [x0, #0x20] G_M000_IG11: mov w0, wzr G_M000_IG12: ldp fp, lr, [sp], #0x70 ret lr RWD00 dd G_M000_IG05 - G_M000_IG02 dd G_M000_IG07 - G_M000_IG02 dd G_M000_IG10 - G_M000_IG02 ; Total bytes of code 696 545: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+d__55:MoveNext() [Tier0, IL size=195, code size=696] ; Assembly listing for method BenchmarkDotNet.Jobs.Job:get_Environment():BenchmarkDotNet.Jobs.EnvironmentMode:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 64 546: JIT compiled BenchmarkDotNet.Jobs.Job:get_Environment() [Tier0, IL size=12, code size=64] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon]:get_Item(BenchmarkDotNet.Characteristics.CharacteristicObject):System.__Canon:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] ldr x0, [x0] ldr x0, [x0, #0x18] str x0, [fp, #0x20] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x20] G_M000_IG05: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] ldr x2, [fp, #0x30] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG06: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 144 547: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon]:get_Item(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=8, code size=144] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:GetValue[System.__Canon](BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon]):System.__Canon:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x18] str x1, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] str x2, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x30] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x28] ldr x0, [x0, #0x10] ldr x0, [x0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 104 548: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:GetValue[System.__Canon](BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon]) [Tier0, IL size=13, code size=104] ; Assembly listing for method BenchmarkDotNet.Jobs.EnvironmentMode:get_Jit():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 64 549: JIT compiled BenchmarkDotNet.Jobs.EnvironmentMode:get_Jit() [Tier0, IL size=12, code size=64] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[int]:get_Item(BenchmarkDotNet.Characteristics.CharacteristicObject):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 550: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[int]:get_Item(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=8, code size=56] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:GetValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int]):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 100 551: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:GetValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int]) [Tier0, IL size=13, code size=100] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[int]:ResolveValueCore(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Object):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] G_M000_IG02: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz x0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x38] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x20] ldr x1, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [x0] ldr x1, [fp, #0x28] str w0, [x1, #0x08] ldr x0, [fp, #0x28] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG04: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x38] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x18] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w2, [x0] str w2, [fp, #0x14] ldr w2, [fp, #0x14] ldr x1, [fp, #0x40] ldr x0, [fp, #0x30] ldr x0, [x0, #0x08] ldr x3, [fp, #0x30] ldr x3, [x3, #0x18] blr x3 ldr x1, [fp, #0x28] str w0, [x1, #0x08] ldr x0, [fp, #0x28] G_M000_IG05: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 356 552: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[int]:ResolveValueCore(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Object) [Tier0, IL size=58, code size=356] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[int]:get_Resolver():System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,int,int]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 553: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[int]:get_Resolver() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Portability.RuntimeInformation:GetCurrentRuntime():BenchmarkDotNet.Environments.Runtime ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x20] b G_M000_IG10 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x20] b G_M000_IG10 G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x20] b G_M000_IG10 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x20] b G_M000_IG10 G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG07 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x20] b G_M000_IG10 G_M000_IG07: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x20] b G_M000_IG10 G_M000_IG08: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG09 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x20] b G_M000_IG10 G_M000_IG09: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x28] bl CORINFO_HELP_THROW G_M000_IG10: ldr x0, [fp, #0x20] G_M000_IG11: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 548 554: JIT compiled BenchmarkDotNet.Portability.RuntimeInformation:GetCurrentRuntime() [Tier0, IL size=109, code size=548] ; Assembly listing for method BenchmarkDotNet.Environments.CoreRuntime:GetCurrentVersion():BenchmarkDotNet.Environments.CoreRuntime ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbnz w0, G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x28] bl CORINFO_HELP_THROW G_M000_IG04: add x0, fp, #56 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG06 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x30] bl CORINFO_HELP_THROW G_M000_IG06: ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG07: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 268 555: JIT compiled BenchmarkDotNet.Environments.CoreRuntime:GetCurrentVersion() [Tier0, IL size=45, code size=268] ; Assembly listing for method BenchmarkDotNet.Environments.CoreRuntime:FromVersion(System.Version):BenchmarkDotNet.Environments.CoreRuntime ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xB0]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] stp xzr, xzr, [x9, #0x80] str x0, [fp, #0xA8] G_M000_IG02: ldr x0, [fp, #0xA8] str x0, [fp, #0xA0] ldr x0, [fp, #0xA0] cbz x0, G_M000_IG10 ldr x0, [fp, #0xA0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cmp w0, #2 bne G_M000_IG03 ldr x0, [fp, #0xA0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbnz w0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x30] b G_M000_IG11 G_M000_IG03: ldr x0, [fp, #0xA0] str x0, [fp, #0x98] ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cmp w0, #2 bne G_M000_IG04 ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cmp w0, #1 bne G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x30] b G_M000_IG11 G_M000_IG04: ldr x0, [fp, #0xA0] str x0, [fp, #0x90] ldr x0, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cmp w0, #2 bne G_M000_IG05 ldr x0, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cmp w0, #2 bne G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x30] b G_M000_IG11 G_M000_IG05: ldr x0, [fp, #0xA0] str x0, [fp, #0x88] ldr x0, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cmp w0, #3 bne G_M000_IG06 ldr x0, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbnz w0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x30] b G_M000_IG11 G_M000_IG06: ldr x0, [fp, #0xA0] str x0, [fp, #0x80] ldr x0, [fp, #0x80] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cmp w0, #3 bne G_M000_IG07 ldr x0, [fp, #0x80] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cmp w0, #1 bne G_M000_IG07 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x30] b G_M000_IG11 G_M000_IG07: ldr x0, [fp, #0xA0] str x0, [fp, #0x78] ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cmp w0, #5 bne G_M000_IG08 ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbnz w0, G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x30] b G_M000_IG11 G_M000_IG08: ldr x0, [fp, #0xA0] str x0, [fp, #0x70] ldr x0, [fp, #0x70] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cmp w0, #6 bne G_M000_IG09 ldr x0, [fp, #0x70] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbnz w0, G_M000_IG09 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x30] b G_M000_IG11 G_M000_IG09: ldr x0, [fp, #0xA0] str x0, [fp, #0x68] ldr x0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cmp w0, #7 bne G_M000_IG10 ldr x0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbnz w0, G_M000_IG10 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x30] b G_M000_IG11 G_M000_IG10: add x0, fp, #64 mov w1, #4 mov w2, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x0, fp, #64 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str w0, [fp, #0x2C] ldr w1, [fp, #0x2C] add x0, fp, #64 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #64 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str w0, [fp, #0x28] ldr w1, [fp, #0x28] add x0, fp, #64 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #64 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x38] add x0, fp, #64 mov w1, #6 mov w2, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x0, fp, #64 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str w0, [fp, #0x24] ldr w1, [fp, #0x24] add x0, fp, #64 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #64 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str w0, [fp, #0x20] ldr w1, [fp, #0x20] add x0, fp, #64 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #64 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x30] b G_M000_IG11 G_M000_IG11: ldr x0, [fp, #0x30] G_M000_IG12: ldp fp, lr, [sp], #0xB0 ret lr ; Total bytes of code 1632 556: JIT compiled BenchmarkDotNet.Environments.CoreRuntime:FromVersion(System.Version) [Tier0, IL size=374, code size=1632] ; Assembly listing for method BenchmarkDotNet.Environments.CoreRuntime:CreateForNewVersion(System.String,System.String):BenchmarkDotNet.Environments.CoreRuntime ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] str x0, [fp, #0x48] str x1, [fp, #0x40] G_M000_IG02: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x28] bl CORINFO_HELP_THROW G_M000_IG04: ldr x0, [fp, #0x40] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG06 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x30] bl CORINFO_HELP_THROW G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] ldr x0, [fp, #0x38] ldr x3, [fp, #0x40] ldr x2, [fp, #0x48] mov w1, #1 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x38] G_M000_IG07: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 316 557: JIT compiled BenchmarkDotNet.Environments.CoreRuntime:CreateForNewVersion(System.String,System.String) [Tier0, IL size=47, code size=316] ; Assembly listing for method BenchmarkDotNet.Environments.CoreRuntime:.ctor(int,System.String,System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str w1, [fp, #0x24] str x2, [fp, #0x18] str x3, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x28] ldr w1, [fp, #0x24] ldr x2, [fp, #0x18] ldr x3, [fp, #0x10] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 68 558: JIT compiled BenchmarkDotNet.Environments.CoreRuntime:.ctor(int,System.String,System.String) [Tier0, IL size=10, code size=68] ; Assembly listing for method BenchmarkDotNet.Environments.Runtime:.ctor(int,System.String,System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x48] str w1, [fp, #0x44] str x2, [fp, #0x38] str x3, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x20] bl CORINFO_HELP_THROW G_M000_IG04: ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG06 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x28] bl CORINFO_HELP_THROW G_M000_IG06: ldr x14, [fp, #0x48] ldr w15, [fp, #0x44] str w15, [x14, #0x18] ldr x14, [fp, #0x48] add x14, x14, #16 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x48] add x14, x14, #8 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF G_M000_IG07: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 332 559: JIT compiled BenchmarkDotNet.Environments.Runtime:.ctor(int,System.String,System.String) [Tier0, IL size=66, code size=332] ; Assembly listing for method BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+d__55:System.IDisposable.Dispose():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 20 560: JIT compiled BenchmarkDotNet.Environments.BenchmarkEnvironmentInfo+d__55:System.IDisposable.Dispose() [Tier0, IL size=1, code size=20] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, wzr bl CORINFO_HELP_CLASSINIT_SHARED_DYNAMICCLASS movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 ldr x15, [x14] ldr x14, [fp, #0x18] add x14, x14, #72 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x18] mov x1, #1 str x1, [x0, #0x78] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 104 561: JIT compiled BenchmarkDotNet.Engines.EngineParameters:.ctor() [Tier0, IL size=26, code size=104] ; Assembly listing for method BenchmarkDotNet.Jobs.JobMode`1[System.__Canon]:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str x0, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x20] ldr x0, [x0, #0x30] ldr x0, [x0, #0x08] ldr x0, [x0, #0x10] str x0, [fp, #0x18] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS str x0, [fp, #0x18] G_M000_IG05: ldr x0, [fp, #0x20] bl CORINFO_HELP_GETGENERICS_GCSTATIC_BASE str x0, [fp, #0x10] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 ldr x14, [fp, #0x10] mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 168 562: JIT compiled BenchmarkDotNet.Jobs.JobMode`1[System.__Canon]:.cctor() [Tier0, IL size=21, code size=168] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:set_Host(BenchmarkDotNet.Engines.IHost):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #8 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 563: JIT compiled BenchmarkDotNet.Engines.EngineParameters:set_Host(BenchmarkDotNet.Engines.IHost) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:set_WorkloadActionUnroll(System.Action`1[long]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #24 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 564: JIT compiled BenchmarkDotNet.Engines.EngineParameters:set_WorkloadActionUnroll(System.Action`1[long]) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:set_WorkloadActionNoUnroll(System.Action`1[long]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #16 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 565: JIT compiled BenchmarkDotNet.Engines.EngineParameters:set_WorkloadActionNoUnroll(System.Action`1[long]) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:set_Dummy1Action(System.Action):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #32 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 566: JIT compiled BenchmarkDotNet.Engines.EngineParameters:set_Dummy1Action(System.Action) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:set_Dummy2Action(System.Action):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #40 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 567: JIT compiled BenchmarkDotNet.Engines.EngineParameters:set_Dummy2Action(System.Action) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:set_Dummy3Action(System.Action):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #48 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 568: JIT compiled BenchmarkDotNet.Engines.EngineParameters:set_Dummy3Action(System.Action) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:set_OverheadActionNoUnroll(System.Action`1[long]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #56 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 569: JIT compiled BenchmarkDotNet.Engines.EngineParameters:set_OverheadActionNoUnroll(System.Action`1[long]) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:set_OverheadActionUnroll(System.Action`1[long]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #64 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 570: JIT compiled BenchmarkDotNet.Engines.EngineParameters:set_OverheadActionUnroll(System.Action`1[long]) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:set_GlobalSetupAction(System.Action):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #80 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 571: JIT compiled BenchmarkDotNet.Engines.EngineParameters:set_GlobalSetupAction(System.Action) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:set_GlobalCleanupAction(System.Action):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #88 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 572: JIT compiled BenchmarkDotNet.Engines.EngineParameters:set_GlobalCleanupAction(System.Action) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:set_IterationSetupAction(System.Action):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #96 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 573: JIT compiled BenchmarkDotNet.Engines.EngineParameters:set_IterationSetupAction(System.Action) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:set_IterationCleanupAction(System.Action):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #104 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 574: JIT compiled BenchmarkDotNet.Engines.EngineParameters:set_IterationCleanupAction(System.Action) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:set_TargetJob(BenchmarkDotNet.Jobs.Job):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #72 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 575: JIT compiled BenchmarkDotNet.Engines.EngineParameters:set_TargetJob(BenchmarkDotNet.Jobs.Job) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:set_OperationsPerInvoke(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] str x1, [x0, #0x78] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 36 576: JIT compiled BenchmarkDotNet.Engines.EngineParameters:set_OperationsPerInvoke(long) [Tier0, IL size=8, code size=36] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:set_MeasureExtraStats(bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr x0, [fp, #0x18] ldr w1, [fp, #0x14] strb w1, [x0, #0x80] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 36 577: JIT compiled BenchmarkDotNet.Engines.EngineParameters:set_MeasureExtraStats(bool) [Tier0, IL size=8, code size=36] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:set_BenchmarkName(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #112 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 578: JIT compiled BenchmarkDotNet.Engines.EngineParameters:set_BenchmarkName(System.String) [Tier0, IL size=8, code size=40] ; Assembly listing for method BenchmarkDotNet.Engines.EngineFactory:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 579: JIT compiled BenchmarkDotNet.Engines.EngineFactory:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Engines.EngineFactory:CreateReadyToRun(BenchmarkDotNet.Engines.EngineParameters):BenchmarkDotNet.Engines.IEngine:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! mov fp, sp movi v16.16b, #0 add x9, fp, #88 add x10, fp, #0xD1FFAB1E stp q16, q16, [x9, #-0x40] stp q16, q16, [x9, #-0x20] bfm x9, xzr, #0, #5 dczva x9 add x9, x9, #64 cmp x9, x10 blo pc-16 (-4 instructions) stp q16, q16, [x10] stp q16, q16, [x10, #0x20] str x0, [fp, #0xD1FFAB1E] str x1, [fp, #0xD1FFAB1E] G_M000_IG02: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbnz x0, G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xA0] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x90] ldr x1, [fp, #0x90] ldr x0, [fp, #0xA0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xA0] bl CORINFO_HELP_THROW G_M000_IG04: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbnz x0, G_M000_IG06 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xA8] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x88] ldr x1, [fp, #0x88] ldr x0, [fp, #0xA8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xA8] bl CORINFO_HELP_THROW G_M000_IG06: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbnz x0, G_M000_IG08 G_M000_IG07: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xB0] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x80] ldr x1, [fp, #0x80] ldr x0, [fp, #0xB0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xB0] bl CORINFO_HELP_THROW G_M000_IG08: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbnz x0, G_M000_IG10 G_M000_IG09: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xB8] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x78] ldr x1, [fp, #0x78] ldr x0, [fp, #0xB8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xB8] bl CORINFO_HELP_THROW G_M000_IG10: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbnz x0, G_M000_IG12 G_M000_IG11: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xC0] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x70] ldr x1, [fp, #0x70] ldr x0, [fp, #0xC0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xC0] bl CORINFO_HELP_THROW G_M000_IG12: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbnz x0, G_M000_IG14 G_M000_IG13: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xC8] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x68] ldr x1, [fp, #0x68] ldr x0, [fp, #0xC8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xC8] bl CORINFO_HELP_THROW G_M000_IG14: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbnz x0, G_M000_IG16 G_M000_IG15: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xD0] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x60] ldr x1, [fp, #0x60] ldr x0, [fp, #0xD0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xD0] bl CORINFO_HELP_THROW G_M000_IG16: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbnz x0, G_M000_IG18 G_M000_IG17: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xD8] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x58] ldr x1, [fp, #0x58] ldr x0, [fp, #0xD8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xD8] bl CORINFO_HELP_THROW G_M000_IG18: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG19 b G_M000_IG20 G_M000_IG19: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x08] ldr x1, [fp, #0xD1FFAB1E] ldr x1, [x1, #0x18] blr x1 G_M000_IG20: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbnz w0, G_M000_IG21 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x98] b G_M000_IG27 G_M000_IG21: str wzr, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbnz w0, G_M000_IG22 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbz w0, G_M000_IG23 G_M000_IG22: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] add w0, w0, #1 str w0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] add w0, w0, #1 str w0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str w0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str w0, [fp, #0x54] ldr w3, [fp, #0x54] ldr w1, [fp, #0xD1FFAB1E] ldr w2, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 str d0, [fp, #0xD1FFAB1E] ldr d0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x98] b G_M000_IG27 G_M000_IG23: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] add w0, w0, #1 str w0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] add w0, w0, #1 str w0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xD1FFAB1E] mov w2, #1 mov w3, #1 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 str d0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str d0, [fp, #0xD1FFAB1E] ldr d0, [fp, #0xD1FFAB1E] ldr d1, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0xD1FFAB1E] ldr d0, [fp, #0xD1FFAB1E] fmov d16, #1.5000 fcmp d0, d16 bhs G_M000_IG24 fmov d0, #10.0000 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0xF0] ldr d0, [fp, #0xD1FFAB1E] ldr d1, [fp, #0xF0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG24 ldr w0, [fp, #0xD1FFAB1E] add w0, w0, #1 str w0, [fp, #0xEC] ldr w0, [fp, #0xD1FFAB1E] add w0, w0, #1 str w0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xEC] mov w2, #1 mov w3, #1 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 str d0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str d0, [fp, #0xE0] ldr d0, [fp, #0xE0] ldr d1, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0xD1FFAB1E] G_M000_IG24: ldr d16, [fp, #0xD1FFAB1E] fmov d17, #1.5000 fcmp d16, d17 bhs G_M000_IG25 ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x98] b G_M000_IG27 G_M000_IG25: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x38] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] str x2, [fp, #0x48] ldr x2, [fp, #0x48] ldr x1, [fp, #0x40] ldr x0, [fp, #0x38] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 str w0, [fp, #0xD1FFAB1E] ldr d0, [fp, #0xD1FFAB1E] bl System.Math:Ceiling(double):double fcvtzs w0, d0 ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bge G_M000_IG26 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x30] ldr x0, [fp, #0x30] mov w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x28] ldr x0, [fp, #0x28] mov w1, #2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x20] ldr x0, [fp, #0x20] mov w1, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0xF8] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x18] ldr x3, [fp, #0x18] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xF8] ldr x0, [fp, #0xD1FFAB1E] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 str x0, [fp, #0x98] b G_M000_IG27 G_M000_IG26: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] add w0, w0, #1 str w0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] add w0, w0, #1 str w0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xD1FFAB1E] ldr w2, [fp, #0xD1FFAB1E] ldr w3, [fp, #0xD1FFAB1E] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 str d0, [fp, #0xD1FFAB1E] ldr d0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x98] b G_M000_IG27 G_M000_IG27: ldr x0, [fp, #0x98] G_M000_IG28: ldp fp, lr, [sp], #0xD1FFAB1E ret lr ; Total bytes of code 2264 580: JIT compiled BenchmarkDotNet.Engines.EngineFactory:CreateReadyToRun(BenchmarkDotNet.Engines.EngineParameters) [Tier0, IL size=453, code size=2264] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_WorkloadActionNoUnroll():System.Action`1[long]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 581: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_WorkloadActionNoUnroll() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_WorkloadActionUnroll():System.Action`1[long]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 582: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_WorkloadActionUnroll() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_Dummy1Action():System.Action:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 583: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_Dummy1Action() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_Dummy2Action():System.Action:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x28] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 584: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_Dummy2Action() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_Dummy3Action():System.Action:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 585: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_Dummy3Action() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_OverheadActionNoUnroll():System.Action`1[long]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x38] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 586: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_OverheadActionNoUnroll() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_OverheadActionUnroll():System.Action`1[long]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x40] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 587: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_OverheadActionUnroll() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_TargetJob():BenchmarkDotNet.Jobs.Job:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x48] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 588: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_TargetJob() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_GlobalSetupAction():System.Action:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x50] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 589: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_GlobalSetupAction() [Tier0, IL size=7, code size=28] ; Assembly listing for method System.Reflection.Invoke:Setup():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] str x0, [fp, #0x98] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 mov w2, #20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x90] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x90] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 mov w2, #24 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x88] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x88] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 mov w2, #24 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x80] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x80] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 mov w2, #24 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x78] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x78] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 mov w2, #24 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x70] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x70] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 mov w2, #24 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x68] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x68] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, #4 bl CORINFO_HELP_NEWARR_1_OBJ str x0, [fp, #0x60] ldr x0, [fp, #0x60] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ARRADDR_ST ldr x0, [fp, #0x60] mov x1, #1 movz x2, #32 movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ARRADDR_ST ldr x0, [fp, #0x60] mov x1, #2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ARRADDR_ST ldr x0, [fp, #0x60] mov x1, #3 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ARRADDR_ST G_M000_IG03: ldr x0, [fp, #0x58] ldr x1, [fp, #0x60] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x50] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x50] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x48] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x40] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x38] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x38] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x30] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x28] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x20] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG04: ldp fp, lr, [sp], #0xA0 ret lr ; Total bytes of code 1280 590: JIT compiled System.Reflection.Invoke:Setup() [Tier0, IL size=366, code size=1280] ; Assembly listing for method System.Reflection.Invoke:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x40] ldr x0, [fp, #0x40] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x40] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, #4 bl CORINFO_HELP_NEWARR_1_OBJ str x0, [fp, #0x38] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] ldr x2, [fp, #0x30] mov w0, #42 str w0, [x2, #0x08] ldr x2, [fp, #0x30] ldr x0, [fp, #0x38] mov x1, xzr bl CORINFO_HELP_ARRADDR_ST ldr x0, [fp, #0x38] mov x1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ARRADDR_ST str xzr, [fp, #0x48] add x1, fp, #72 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_BOX str x0, [fp, #0x18] ldr x2, [fp, #0x18] ldr x0, [fp, #0x38] mov x1, #2 bl CORINFO_HELP_ARRADDR_ST movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr x0, [fp, #0x38] mov x1, #3 bl CORINFO_HELP_ARRADDR_ST ldr x15, [fp, #0x38] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, #5 bl CORINFO_HELP_NEWARR_1_OBJ str x0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] ldr x2, [fp, #0x30] mov w0, #42 str w0, [x2, #0x08] ldr x2, [fp, #0x30] ldr x0, [fp, #0x28] mov x1, xzr bl CORINFO_HELP_ARRADDR_ST ldr x0, [fp, #0x28] mov x1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ARRADDR_ST str xzr, [fp, #0x48] add x1, fp, #72 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_BOX str x0, [fp, #0x10] ldr x2, [fp, #0x10] ldr x0, [fp, #0x28] mov x1, #2 bl CORINFO_HELP_ARRADDR_ST movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr x0, [fp, #0x28] mov x1, #3 bl CORINFO_HELP_ARRADDR_ST movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x2, [fp, #0x20] mov w0, #1 strb w0, [x2, #0x08] ldr x2, [fp, #0x20] ldr x0, [fp, #0x28] mov x1, #4 bl CORINFO_HELP_ARRADDR_ST ldr x15, [fp, #0x28] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 520 591: JIT compiled System.Reflection.Invoke:.cctor() [Tier0, IL size=128, code size=520] ; Assembly listing for method System.Reflection.Invoke+MyClass:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 592: JIT compiled System.Reflection.Invoke+MyClass:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_NeedsJitting():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x10] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x2, [fp, #0x18] ldr x1, [fp, #0x10] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 176 593: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_NeedsJitting() [Tier0, IL size=27, code size=176] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, #2 bl CORINFO_HELP_NEWARR_1_OBJ str x0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #202 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] str x2, [fp, #0x18] ldr x2, [fp, #0x18] ldr x0, [fp, #0x28] mov x1, xzr bl CORINFO_HELP_ARRADDR_ST movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] str x2, [fp, #0x10] ldr x2, [fp, #0x10] ldr x0, [fp, #0x28] mov x1, #1 bl CORINFO_HELP_ARRADDR_ST movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x15, [fp, #0x20] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 236 594: JIT compiled BenchmarkDotNet.Engines.EngineParameters:.cctor() [Tier0, IL size=33, code size=236] ; Assembly listing for method BenchmarkDotNet.Running.BenchmarkRunnerClean:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, #2 bl CORINFO_HELP_NEWARR_1_OBJ str x0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] str x2, [fp, #0x18] ldr x2, [fp, #0x18] ldr x0, [fp, #0x28] mov x1, xzr bl CORINFO_HELP_ARRADDR_ST movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] str x2, [fp, #0x10] ldr x2, [fp, #0x10] ldr x0, [fp, #0x28] mov x1, #1 bl CORINFO_HELP_ARRADDR_ST movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x15, [fp, #0x20] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 236 595: JIT compiled BenchmarkDotNet.Running.BenchmarkRunnerClean:.cctor() [Tier0, IL size=33, code size=236] ; Assembly listing for method BenchmarkDotNet.Environments.EnvironmentResolver:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, #2 bl CORINFO_HELP_NEWARR_1_OBJ str x0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x28] ldr x2, [fp, #0x20] mov x1, xzr bl CORINFO_HELP_ARRADDR_ST movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] str x2, [fp, #0x10] ldr x2, [fp, #0x10] ldr x0, [fp, #0x28] mov x1, #1 bl CORINFO_HELP_ARRADDR_ST movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 240 596: JIT compiled BenchmarkDotNet.Environments.EnvironmentResolver:.cctor() [Tier0, IL size=33, code size=240] ; Assembly listing for method BenchmarkDotNet.Environments.EnvironmentResolver:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! mov fp, sp movi v16.16b, #0 sub x9, fp, #16 mov x10, #184 stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40]! subs x10, x10, #64 bge pc-16 (-4 instructions) stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str xzr, [x9, #0x50] str x0, [fp, #0xD1FFAB1E] G_M000_IG02: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xF8] ldr x0, [fp, #0xD1FFAB1E] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xF8] ldr x2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xF0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xE8] ldr x0, [fp, #0xF0] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0xD1FFAB1E] ldr x3, [fp, #0xF0] ldr x2, [fp, #0xE8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xE0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD8] ldr x0, [fp, #0xE0] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD8] ldr x2, [fp, #0xE0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xD0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xC8] ldr x0, [fp, #0xD0] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xC8] ldr x2, [fp, #0xD0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xC0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xB8] ldr x0, [fp, #0xC0] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0xD1FFAB1E] ldr x3, [fp, #0xC0] ldr x2, [fp, #0xB8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xA8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 G_M000_IG03: movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xB0] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xA0] ldr x0, [fp, #0xA8] str x0, [fp, #0x98] ldr x0, [fp, #0xB0] str x0, [fp, #0x90] ldr x0, [fp, #0xB0] cbnz x0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x28] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x28] str x0, [fp, #0x90] G_M000_IG04: ldr x0, [fp, #0xA0] ldr x1, [fp, #0x98] ldr x2, [fp, #0x90] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x80] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x88] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x78] ldr x0, [fp, #0x80] str x0, [fp, #0x70] ldr x0, [fp, #0x88] str x0, [fp, #0x68] ldr x0, [fp, #0x88] cbnz x0, G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x30] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x30] str x0, [fp, #0x68] G_M000_IG05: ldr x0, [fp, #0x78] ldr x1, [fp, #0x70] ldr x2, [fp, #0x68] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x60] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x50] ldr x0, [fp, #0x58] str x0, [fp, #0x48] ldr x0, [fp, #0x60] str x0, [fp, #0x40] ldr x0, [fp, #0x60] cbnz x0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x38] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x38] str x0, [fp, #0x40] G_M000_IG06: ldr x0, [fp, #0x50] ldr x1, [fp, #0x48] ldr x2, [fp, #0x40] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG07: ldp fp, lr, [sp], #0xD1FFAB1E ret lr ; Total bytes of code 1544 597: JIT compiled BenchmarkDotNet.Environments.EnvironmentResolver:.ctor() [Tier0, IL size=248, code size=1544] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x18] add x14, x14, #8 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 108 598: JIT compiled BenchmarkDotNet.Characteristics.Resolver:.ctor() [Tier0, IL size=18, code size=108] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:Register[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],System.Func`1[int]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] str x14, [fp, #0x30] ldr x14, [fp, #0x30] add x14, x14, #8 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x48] ldr x0, [x0, #0x08] str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] ldr x1, [fp, #0x40] ldr x2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 220 599: JIT compiled BenchmarkDotNet.Characteristics.Resolver:Register[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],System.Func`1[int]) [Tier0, IL size=38, code size=220] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[int]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 600: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[int]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:Register[System.__Canon](BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon],System.Func`1[System.__Canon]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x1, [fp, #0x58] str x0, [fp, #0x50] str x1, [fp, #0x48] str x2, [fp, #0x40] str x3, [fp, #0x38] G_M000_IG02: ldr x0, [fp, #0x48] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x48] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x20] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x20] G_M000_IG05: ldr x0, [fp, #0x20] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] str x14, [fp, #0x30] ldr x14, [fp, #0x30] add x14, x14, #8 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x50] ldr x0, [x0, #0x08] str x0, [fp, #0x10] ldr x0, [fp, #0x18] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x10] ldr x1, [fp, #0x40] ldr x2, [fp, #0x18] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG06: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 280 601: JIT compiled BenchmarkDotNet.Characteristics.Resolver:Register[System.__Canon](BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon],System.Func`1[System.__Canon]) [Tier0, IL size=38, code size=280] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[System.__Canon]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 602: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[System.__Canon]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:Register[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],System.Func`1[int]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] str x14, [fp, #0x30] ldr x14, [fp, #0x30] add x14, x14, #8 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x48] ldr x0, [x0, #0x08] str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] ldr x1, [fp, #0x40] ldr x2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 220 603: JIT compiled BenchmarkDotNet.Characteristics.Resolver:Register[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],System.Func`1[int]) [Tier0, IL size=38, code size=220] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[int]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 604: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[int]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:Register[long](BenchmarkDotNet.Characteristics.Characteristic`1[long],System.Func`1[long]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] str x14, [fp, #0x30] ldr x14, [fp, #0x30] add x14, x14, #8 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x48] ldr x0, [x0, #0x08] str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] ldr x1, [fp, #0x40] ldr x2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 220 605: JIT compiled BenchmarkDotNet.Characteristics.Resolver:Register[long](BenchmarkDotNet.Characteristics.Characteristic`1[long],System.Func`1[long]) [Tier0, IL size=38, code size=220] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[long]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 606: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[long]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Environments.EnvironmentResolver+<>c:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 607: JIT compiled BenchmarkDotNet.Environments.EnvironmentResolver+<>c:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method BenchmarkDotNet.Environments.EnvironmentResolver+<>c:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 608: JIT compiled BenchmarkDotNet.Environments.EnvironmentResolver+<>c:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:Register[System.Nullable`1[System.Guid]](BenchmarkDotNet.Characteristics.Characteristic`1[System.Nullable`1[System.Guid]],System.Func`1[System.Nullable`1[System.Guid]]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] str x14, [fp, #0x30] ldr x14, [fp, #0x30] add x14, x14, #8 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x48] ldr x0, [x0, #0x08] str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] ldr x1, [fp, #0x40] ldr x2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 220 609: JIT compiled BenchmarkDotNet.Characteristics.Resolver:Register[System.Nullable`1[System.Guid]](BenchmarkDotNet.Characteristics.Characteristic`1[System.Nullable`1[System.Guid]],System.Func`1[System.Nullable`1[System.Guid]]) [Tier0, IL size=38, code size=220] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[System.Nullable`1[System.Guid]]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 610: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[System.Nullable`1[System.Guid]]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:Register[bool](BenchmarkDotNet.Characteristics.Characteristic`1[bool],System.Func`1[bool]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] str x14, [fp, #0x30] ldr x14, [fp, #0x30] add x14, x14, #8 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x48] ldr x0, [x0, #0x08] str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] ldr x1, [fp, #0x40] ldr x2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 220 611: JIT compiled BenchmarkDotNet.Characteristics.Resolver:Register[bool](BenchmarkDotNet.Characteristics.Characteristic`1[bool],System.Func`1[bool]) [Tier0, IL size=38, code size=220] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[bool]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 612: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[bool]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:Register[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],System.Func`2[BenchmarkDotNet.Characteristics.CharacteristicObject,int]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] str x14, [fp, #0x30] ldr x14, [fp, #0x30] add x14, x14, #8 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x48] ldr x0, [x0, #0x08] str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] ldr x1, [fp, #0x40] ldr x2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 220 613: JIT compiled BenchmarkDotNet.Characteristics.Resolver:Register[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],System.Func`2[BenchmarkDotNet.Characteristics.CharacteristicObject,int]) [Tier0, IL size=38, code size=220] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass2_0`1[int]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 614: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass2_0`1[int]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Environments.GcResolver:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 615: JIT compiled BenchmarkDotNet.Environments.GcResolver:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method BenchmarkDotNet.Environments.GcResolver:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! mov fp, sp movi v16.16b, #0 add x9, fp, #80 add x10, fp, #0xD1FFAB1E stp q16, q16, [x9, #-0x40] stp q16, q16, [x9, #-0x20] bfm x9, xzr, #0, #5 dczva x9 add x9, x9, #64 cmp x9, x10 blo pc-16 (-4 instructions) stp q16, q16, [x10] stp q16, q16, [x10, #0x20] str x0, [fp, #0xD1FFAB1E] G_M000_IG02: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x40] ldr x1, [fp, #0x40] ldr x0, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x48] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x48] str x0, [fp, #0xD1FFAB1E] G_M000_IG03: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x50] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x38] ldr x1, [fp, #0x38] ldr x0, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x50] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x50] str x0, [fp, #0xD1FFAB1E] G_M000_IG04: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x30] ldr x1, [fp, #0x30] ldr x0, [fp, #0x58] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x58] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x58] str x0, [fp, #0xD1FFAB1E] G_M000_IG05: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xF8] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x60] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x28] ldr x1, [fp, #0x28] ldr x0, [fp, #0x60] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x60] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x60] str x0, [fp, #0xF8] G_M000_IG06: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xF8] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xE8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xF0] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xE0] ldr x0, [fp, #0xE8] str x0, [fp, #0xD8] ldr x0, [fp, #0xF0] str x0, [fp, #0xD0] ldr x0, [fp, #0xF0] cbnz x0, G_M000_IG07 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x68] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x68] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x68] str x0, [fp, #0xD0] G_M000_IG07: ldr x0, [fp, #0xE0] ldr x1, [fp, #0xD8] ldr x2, [fp, #0xD0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xC0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xC8] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xB8] ldr x0, [fp, #0xC0] str x0, [fp, #0xB0] ldr x0, [fp, #0xC8] str x0, [fp, #0xA8] ldr x0, [fp, #0xC8] cbnz x0, G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x70] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x70] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x70] str x0, [fp, #0xA8] G_M000_IG08: ldr x0, [fp, #0xB8] ldr x1, [fp, #0xB0] ldr x2, [fp, #0xA8] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x98] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xA0] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x90] ldr x0, [fp, #0x98] str x0, [fp, #0x88] ldr x0, [fp, #0xA0] str x0, [fp, #0x80] ldr x0, [fp, #0xA0] cbnz x0, G_M000_IG09 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x78] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x78] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x78] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x78] str x0, [fp, #0x80] G_M000_IG09: ldr x0, [fp, #0x90] ldr x1, [fp, #0x88] ldr x2, [fp, #0x80] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG10: ldp fp, lr, [sp], #0xD1FFAB1E ret lr ; Total bytes of code 1996 616: JIT compiled BenchmarkDotNet.Environments.GcResolver:.ctor() [Tier0, IL size=301, code size=1996] ; Assembly listing for method BenchmarkDotNet.Environments.GcResolver+<>c:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 617: JIT compiled BenchmarkDotNet.Environments.GcResolver+<>c:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method BenchmarkDotNet.Environments.GcResolver+<>c:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 618: JIT compiled BenchmarkDotNet.Environments.GcResolver+<>c:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver:.ctor(BenchmarkDotNet.Characteristics.IResolver[]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x18] add x14, x14, #8 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 64 619: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver:.ctor(BenchmarkDotNet.Characteristics.IResolver[]) [Tier0, IL size=14, code size=64] ; Assembly listing for method BenchmarkDotNet.Environments.InfrastructureResolver:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 620: JIT compiled BenchmarkDotNet.Environments.InfrastructureResolver:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method BenchmarkDotNet.Environments.InfrastructureResolver:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xE0]! mov fp, sp movi v16.16b, #0 sub x9, fp, #16 mov x10, #136 stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40]! subs x10, x10, #64 bge pc-16 (-4 instructions) str xzr, [x9, #0x20] str x0, [fp, #0xD8] G_M000_IG02: ldr x0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xC8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD0] ldr x0, [fp, #0xD8] str x0, [fp, #0xC0] ldr x0, [fp, #0xC8] str x0, [fp, #0xB8] ldr x0, [fp, #0xD0] str x0, [fp, #0xB0] ldr x0, [fp, #0xD0] cbnz x0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x28] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x28] str x0, [fp, #0xB0] G_M000_IG03: ldr x0, [fp, #0xC0] ldr x3, [fp, #0xB0] ldr x2, [fp, #0xB8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xA0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xA8] ldr x0, [fp, #0xD8] str x0, [fp, #0x98] ldr x0, [fp, #0xA0] str x0, [fp, #0x90] ldr x0, [fp, #0xA8] str x0, [fp, #0x88] ldr x0, [fp, #0xA8] cbnz x0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x30] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x30] str x0, [fp, #0x88] G_M000_IG04: ldr x0, [fp, #0x98] ldr x3, [fp, #0x88] ldr x2, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x78] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x80] ldr x0, [fp, #0xD8] str x0, [fp, #0x70] ldr x0, [fp, #0x78] str x0, [fp, #0x68] ldr x0, [fp, #0x80] str x0, [fp, #0x60] ldr x0, [fp, #0x80] cbnz x0, G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x38] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x38] str x0, [fp, #0x60] G_M000_IG05: ldr x0, [fp, #0x70] ldr x3, [fp, #0x60] ldr x2, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x50] ldr x0, [fp, #0x58] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0xD8] ldr x3, [fp, #0x58] ldr x2, [fp, #0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x40] ldr x0, [fp, #0x48] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0xD8] ldr x3, [fp, #0x48] ldr x2, [fp, #0x40] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG06: ldp fp, lr, [sp], #0xE0 ret lr ; Total bytes of code 1200 621: JIT compiled BenchmarkDotNet.Environments.InfrastructureResolver:.ctor() [Tier0, IL size=179, code size=1200] ; Assembly listing for method BenchmarkDotNet.Environments.InfrastructureResolver+<>c:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 622: JIT compiled BenchmarkDotNet.Environments.InfrastructureResolver+<>c:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method BenchmarkDotNet.Environments.InfrastructureResolver+<>c:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 623: JIT compiled BenchmarkDotNet.Environments.InfrastructureResolver+<>c:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Engines.EngineResolver:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 624: JIT compiled BenchmarkDotNet.Engines.EngineResolver:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method BenchmarkDotNet.Engines.EngineResolver:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: sub sp, sp, #0xD1FFAB1E stp fp, lr, [sp] mov fp, sp movi v16.16b, #0 add x9, fp, #80 add x10, fp, #0xD1FFAB1E stp q16, q16, [x9, #-0x40] stp q16, q16, [x9, #-0x20] bfm x9, xzr, #0, #5 dczva x9 add x9, x9, #64 cmp x9, x10 blo pc-16 (-4 instructions) stp q16, q16, [x10] stp q16, q16, [x10, #0x20] str x0, [fp, #0xD1FFAB1E] G_M000_IG02: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x68] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x60] ldr x1, [fp, #0x60] ldr x0, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x68] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x68] str x0, [fp, #0xD1FFAB1E] G_M000_IG03: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x70] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x58] ldr x1, [fp, #0x58] ldr x0, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x70] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x70] str x0, [fp, #0xD1FFAB1E] G_M000_IG04: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x78] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x50] ldr x1, [fp, #0x50] ldr x0, [fp, #0x78] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x78] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x78] str x0, [fp, #0xD1FFAB1E] G_M000_IG05: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x80] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x48] ldr x1, [fp, #0x48] ldr x0, [fp, #0x80] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x80] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x80] str x0, [fp, #0xD1FFAB1E] G_M000_IG06: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG07 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x88] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x40] ldr x1, [fp, #0x40] ldr x0, [fp, #0x88] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x88] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x88] str x0, [fp, #0xD1FFAB1E] G_M000_IG07: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x90] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x38] ldr x1, [fp, #0x38] ldr x0, [fp, #0x90] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x90] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x90] str x0, [fp, #0xD1FFAB1E] G_M000_IG08: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG09 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x98] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x30] ldr x1, [fp, #0x30] ldr x0, [fp, #0x98] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x98] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x98] str x0, [fp, #0xD1FFAB1E] G_M000_IG09: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG10 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xA0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x28] ldr x1, [fp, #0x28] ldr x0, [fp, #0xA0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0xA0] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0xA0] str x0, [fp, #0xD1FFAB1E] G_M000_IG10: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG11 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xA8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0xA8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0xA8] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0xA8] str x0, [fp, #0xD1FFAB1E] G_M000_IG11: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xF8] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG12 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xB0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0xB0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0xB0] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0xB0] str x0, [fp, #0xF8] G_M000_IG12: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xF8] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xE8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xF0] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xE0] ldr x0, [fp, #0xE8] str x0, [fp, #0xD8] ldr x0, [fp, #0xF0] str x0, [fp, #0xD0] ldr x0, [fp, #0xF0] cbnz x0, G_M000_IG13 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xB8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0xB8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0xB8] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0xB8] str x0, [fp, #0xD0] G_M000_IG13: ldr x0, [fp, #0xE0] ldr x1, [fp, #0xD8] ldr x2, [fp, #0xD0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xC8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xC0] ldr x0, [fp, #0xC8] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xC0] ldr x2, [fp, #0xC8] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG14: ldp fp, lr, [sp] add sp, sp, #0xD1FFAB1E ret lr ; Total bytes of code 3204 625: JIT compiled BenchmarkDotNet.Engines.EngineResolver:.ctor() [Tier0, IL size=492, code size=3204] ; Assembly listing for method BenchmarkDotNet.Engines.EngineResolver+<>c:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 626: JIT compiled BenchmarkDotNet.Engines.EngineResolver+<>c:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method BenchmarkDotNet.Engines.EngineResolver+<>c:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 627: JIT compiled BenchmarkDotNet.Engines.EngineResolver+<>c:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:Register[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],System.Func`1[int]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] str x14, [fp, #0x30] ldr x14, [fp, #0x30] add x14, x14, #8 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x48] ldr x0, [x0, #0x08] str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] ldr x1, [fp, #0x40] ldr x2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 220 628: JIT compiled BenchmarkDotNet.Characteristics.Resolver:Register[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],System.Func`1[int]) [Tier0, IL size=38, code size=220] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[int]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 629: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[int]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:Register[Perfolizer.Horology.TimeInterval](BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval],System.Func`1[Perfolizer.Horology.TimeInterval]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] str x14, [fp, #0x30] ldr x14, [fp, #0x30] add x14, x14, #8 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x48] ldr x0, [x0, #0x08] str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] ldr x1, [fp, #0x40] ldr x2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 220 630: JIT compiled BenchmarkDotNet.Characteristics.Resolver:Register[Perfolizer.Horology.TimeInterval](BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval],System.Func`1[Perfolizer.Horology.TimeInterval]) [Tier0, IL size=38, code size=220] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[Perfolizer.Horology.TimeInterval]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 631: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[Perfolizer.Horology.TimeInterval]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:Register[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],System.Func`1[int]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] str x14, [fp, #0x30] ldr x14, [fp, #0x30] add x14, x14, #8 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x48] ldr x0, [x0, #0x08] str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] ldr x1, [fp, #0x40] ldr x2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 220 632: JIT compiled BenchmarkDotNet.Characteristics.Resolver:Register[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],System.Func`1[int]) [Tier0, IL size=38, code size=220] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[int]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 633: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[int]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:Register[double](BenchmarkDotNet.Characteristics.Characteristic`1[double],System.Func`1[double]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] str x14, [fp, #0x30] ldr x14, [fp, #0x30] add x14, x14, #8 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x48] ldr x0, [x0, #0x08] str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] ldr x1, [fp, #0x40] ldr x2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 220 634: JIT compiled BenchmarkDotNet.Characteristics.Resolver:Register[double](BenchmarkDotNet.Characteristics.Characteristic`1[double],System.Func`1[double]) [Tier0, IL size=38, code size=220] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[double]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 635: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[double]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:Register[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],System.Func`2[BenchmarkDotNet.Characteristics.CharacteristicObject,int]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] str x14, [fp, #0x30] ldr x14, [fp, #0x30] add x14, x14, #8 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x48] ldr x0, [x0, #0x08] str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] ldr x1, [fp, #0x40] ldr x2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 220 636: JIT compiled BenchmarkDotNet.Characteristics.Resolver:Register[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],System.Func`2[BenchmarkDotNet.Characteristics.CharacteristicObject,int]) [Tier0, IL size=38, code size=220] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass2_0`1[int]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 637: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass2_0`1[int]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],BenchmarkDotNet.Characteristics.IResolver):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x10] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] ldr x3, [fp, #0x10] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 638: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],BenchmarkDotNet.Characteristics.IResolver) [Tier0, IL size=9, code size=84] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver:Resolve[int](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[int]):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str x0, [fp, #0x78] str x1, [fp, #0x70] str x2, [fp, #0x68] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x50] ldr x0, [fp, #0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x50] str x14, [fp, #0x60] ldr x14, [fp, #0x60] add x14, x14, #8 ldr x15, [fp, #0x68] bl CORINFO_HELP_ASSIGN_REF ldr x1, [fp, #0x60] ldr x1, [x1, #0x08] ldr x0, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG04 ldr x0, [fp, #0x60] ldr x0, [x0, #0x08] ldr x1, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] ldr x0, [fp, #0x78] ldr x0, [x0, #0x08] str x0, [fp, #0x40] ldr x0, [fp, #0x48] ldr x1, [fp, #0x60] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x2, [fp, #0x48] ldr x1, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x58] ldr x0, [fp, #0x58] cbz x0, G_M000_IG06 ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x30] ldr x2, [fp, #0x60] ldr x2, [x2, #0x08] ldr x0, [fp, #0x58] ldr x1, [fp, #0x70] ldr x3, [fp, #0x30] blr x3 G_M000_IG05: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] ldr x0, [fp, #0x60] ldr x0, [x0, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x38] bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 540 639: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver:Resolve[int](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[int]) [Tier0, IL size=108, code size=540] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[int]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 640: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[int]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Linq.Enumerable:FirstOrDefault[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,bool]):System.__Canon ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] str x2, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x3, [fp, #0x30] ldr x3, [x3, #0x10] ldr x3, [x3, #0x10] str x3, [fp, #0x10] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x10] G_M000_IG05: add x3, fp, #24 ldr x0, [fp, #0x10] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG06: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 128 641: JIT compiled System.Linq.Enumerable:FirstOrDefault[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,bool]) [Tier0, IL size=10, code size=128] ; Assembly listing for method System.Linq.Enumerable:TryGetFirst[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,bool],byref):System.__Canon ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x90]! mov fp, sp str xzr, [fp, #0x58] str xzr, [fp, #0x50] str xzr, [fp, #0x48] str xzr, [fp, #0x40] add x4, sp, #144 str x4, [fp, #0x88] str x0, [fp, #0x80] str x0, [fp, #0x78] str x1, [fp, #0x70] str x2, [fp, #0x68] str x3, [fp, #0x60] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x18] ldr x0, [fp, #0x70] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x68] cbnz x0, G_M000_IG04 mov w0, #12 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldr x0, [fp, #0x78] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x78] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x38] b G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x38] G_M000_IG07: ldr x0, [fp, #0x38] str x0, [fp, #0x30] ldr x0, [fp, #0x70] ldr x11, [fp, #0x30] ldr x1, [fp, #0x30] ldr x1, [x1] blr x1 str x0, [fp, #0x58] G_M000_IG08: b G_M000_IG13 G_M000_IG09: ldr x0, [fp, #0x78] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] cbz x0, G_M000_IG11 G_M000_IG10: ldr x0, [fp, #0x78] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] str x0, [fp, #0x28] b G_M000_IG12 G_M000_IG11: ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x28] G_M000_IG12: ldr x0, [fp, #0x28] str x0, [fp, #0x20] ldr x0, [fp, #0x58] ldr x11, [fp, #0x20] ldr x1, [fp, #0x20] ldr x1, [x1] blr x1 str x0, [fp, #0x50] ldr x0, [fp, #0x68] ldr x0, [x0, #0x08] ldr x1, [fp, #0x50] ldr x2, [fp, #0x68] ldr x2, [x2, #0x18] blr x2 cbz w0, G_M000_IG13 ldr x0, [fp, #0x60] mov w1, #1 strb w1, [x0] ldr x0, [fp, #0x50] str x0, [fp, #0x48] b G_M000_IG18 G_M000_IG13: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG15 G_M000_IG14: add x0, fp, #24 mov w1, #52 bl CORINFO_HELP_PATCHPOINT G_M000_IG15: ldr x0, [fp, #0x58] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG09 b G_M000_IG16 G_M000_IG16: ldr x0, [fp, #0x88] bl G_M000_IG24 G_M000_IG17: b G_M000_IG20 G_M000_IG18: ldr x0, [fp, #0x88] bl G_M000_IG24 G_M000_IG19: b G_M000_IG22 G_M000_IG20: ldr x0, [fp, #0x60] strb wzr, [x0] str xzr, [fp, #0x40] ldr x0, [fp, #0x40] G_M000_IG21: ldp fp, lr, [sp], #0x90 ret lr G_M000_IG22: ldr x0, [fp, #0x48] G_M000_IG23: ldp fp, lr, [sp], #0x90 ret lr G_M000_IG24: stp fp, lr, [sp, #-0x20]! add x3, fp, #144 str x3, [sp, #0x18] G_M000_IG25: ldr x0, [fp, #0x58] cbz x0, G_M000_IG26 ldr x0, [fp, #0x58] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG26: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 544 642: JIT compiled System.Linq.Enumerable:TryGetFirst[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,bool],byref) [Tier0, IL size=87, code size=544] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[int]:b__0(BenchmarkDotNet.Characteristics.IResolver):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x1, [fp, #0x18] ldr x1, [x1, #0x08] ldr x0, [fp, #0x10] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 643: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[int]:b__0(BenchmarkDotNet.Characteristics.IResolver) [Tier0, IL size=13, code size=56] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver:CanResolve(BenchmarkDotNet.Characteristics.Characteristic):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str x1, [fp, #0x30] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x20] str x14, [fp, #0x28] ldr x14, [fp, #0x28] add x14, x14, #8 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x38] ldr x0, [x0, #0x08] str x0, [fp, #0x10] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x2, [fp, #0x18] ldr x1, [fp, #0x10] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 220 644: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver:CanResolve(BenchmarkDotNet.Characteristics.Characteristic) [Tier0, IL size=37, code size=220] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass2_0:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 645: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass2_0:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Linq.Enumerable:Any[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,bool]):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp str xzr, [fp, #0x50] str xzr, [fp, #0x48] add x3, sp, #128 str x3, [fp, #0x78] str x0, [fp, #0x70] str x0, [fp, #0x68] str x1, [fp, #0x60] str x2, [fp, #0x58] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x18] ldr x0, [fp, #0x60] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x58] cbnz x0, G_M000_IG04 mov w0, #12 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldr x0, [fp, #0x68] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x68] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x38] b G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x38] G_M000_IG07: ldr x0, [fp, #0x38] str x0, [fp, #0x30] ldr x0, [fp, #0x60] ldr x11, [fp, #0x30] ldr x1, [fp, #0x30] ldr x1, [x1] blr x1 str x0, [fp, #0x50] G_M000_IG08: b G_M000_IG13 G_M000_IG09: ldr x0, [fp, #0x68] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] cbz x0, G_M000_IG11 G_M000_IG10: ldr x0, [fp, #0x68] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] str x0, [fp, #0x28] b G_M000_IG12 G_M000_IG11: ldr x0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x28] G_M000_IG12: ldr x0, [fp, #0x28] str x0, [fp, #0x20] ldr x0, [fp, #0x50] ldr x11, [fp, #0x20] ldr x1, [fp, #0x20] ldr x1, [x1] blr x1 str x0, [fp, #0x48] ldr x0, [fp, #0x58] ldr x0, [x0, #0x08] ldr x1, [fp, #0x48] ldr x2, [fp, #0x58] ldr x2, [x2, #0x18] blr x2 cbz w0, G_M000_IG13 mov w0, #1 str w0, [fp, #0x44] b G_M000_IG18 G_M000_IG13: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG15 G_M000_IG14: add x0, fp, #24 mov w1, #49 bl CORINFO_HELP_PATCHPOINT G_M000_IG15: ldr x0, [fp, #0x50] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG09 b G_M000_IG16 G_M000_IG16: ldr x0, [fp, #0x78] bl G_M000_IG24 G_M000_IG17: b G_M000_IG20 G_M000_IG18: ldr x0, [fp, #0x78] bl G_M000_IG24 G_M000_IG19: b G_M000_IG22 G_M000_IG20: mov w0, wzr G_M000_IG21: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG22: ldr w0, [fp, #0x44] G_M000_IG23: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG24: stp fp, lr, [sp, #-0x20]! add x3, fp, #128 str x3, [sp, #0x18] G_M000_IG25: ldr x0, [fp, #0x50] cbz x0, G_M000_IG26 ldr x0, [fp, #0x50] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG26: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 508 646: JIT compiled System.Linq.Enumerable:Any[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,bool]) [Tier0, IL size=73, code size=508] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass2_0:b__0(BenchmarkDotNet.Characteristics.IResolver):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x1, [fp, #0x18] ldr x1, [x1, #0x08] ldr x0, [fp, #0x10] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 647: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass2_0:b__0(BenchmarkDotNet.Characteristics.IResolver) [Tier0, IL size=13, code size=56] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:CanResolve(BenchmarkDotNet.Characteristics.Characteristic):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] ldr x1, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 60 648: JIT compiled BenchmarkDotNet.Characteristics.Resolver:CanResolve(BenchmarkDotNet.Characteristics.Characteristic) [Tier0, IL size=13, code size=60] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:Resolve[int](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[int]):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x0, [fp, #0x58] str x1, [fp, #0x50] str x2, [fp, #0x48] G_M000_IG02: ldr x0, [fp, #0x50] ldr x1, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG04 ldr x0, [fp, #0x48] ldr x1, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG04: ldr x0, [fp, #0x58] ldr x0, [x0, #0x08] add x2, fp, #64 ldr x1, [fp, #0x48] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 cbz w0, G_M000_IG06 ldr x0, [fp, #0x40] ldr x0, [x0, #0x08] ldr x1, [fp, #0x50] ldr x2, [fp, #0x40] ldr x2, [x2, #0x18] blr x2 str x0, [fp, #0x30] ldr x1, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [x0] G_M000_IG05: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x38] bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 384 649: JIT compiled BenchmarkDotNet.Characteristics.Resolver:Resolve[int](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[int]) [Tier0, IL size=68, code size=384] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[int]:b__0(BenchmarkDotNet.Characteristics.CharacteristicObject):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x08] ldr x1, [fp, #0x10] ldr x1, [x1, #0x18] blr x1 ldr x1, [fp, #0x18] str w0, [x1, #0x08] ldr x0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 650: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[int]:b__0(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=17, code size=96] ; Assembly listing for method BenchmarkDotNet.Engines.EngineResolver+<>c:<.ctor>b__7_0():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 24 651: JIT compiled BenchmarkDotNet.Engines.EngineResolver+<>c:<.ctor>b__7_0() [Tier0, IL size=2, code size=24] ; Assembly listing for method BenchmarkDotNet.Engines.RunStrategyExtensions:NeedsJitting(int):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str w0, [fp, #0x1C] G_M000_IG02: ldr w0, [fp, #0x1C] cmp w0, #0 cset x0, eq G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 32 652: JIT compiled BenchmarkDotNet.Engines.RunStrategyExtensions:NeedsJitting(int) [Tier0, IL size=5, code size=32] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_HasInvocationCount():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 96 653: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_HasInvocationCount() [Tier0, IL size=17, code size=96] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_HasUnrollFactor():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 96 654: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_HasUnrollFactor() [Tier0, IL size=17, code size=96] ; Assembly listing for method BenchmarkDotNet.Engines.EngineFactory:CreateSingleActionEngine(BenchmarkDotNet.Engines.EngineParameters):BenchmarkDotNet.Engines.Engine ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x0, [fp, #0x48] G_M000_IG02: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x30] ldr x0, [fp, #0x30] mov x1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x28] ldr x0, [fp, #0x28] mov w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x20] ldr x0, [fp, #0x20] mov w1, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x40] ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x38] ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x18] ldr x3, [fp, #0x18] ldr x1, [fp, #0x40] ldr x2, [fp, #0x38] ldr x0, [fp, #0x48] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 264 655: JIT compiled BenchmarkDotNet.Engines.EngineFactory:CreateSingleActionEngine(BenchmarkDotNet.Engines.EngineParameters) [Tier0, IL size=44, code size=264] ; Assembly listing for method BenchmarkDotNet.Jobs.JobExtensions:WithInvocationCount(BenchmarkDotNet.Jobs.Job,long):BenchmarkDotNet.Jobs.Job ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x38] str x1, [fp, #0x30] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x20] str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x1, [fp, #0x30] str x1, [x0, #0x08] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x38] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 188 656: JIT compiled BenchmarkDotNet.Jobs.JobExtensions:WithInvocationCount(BenchmarkDotNet.Jobs.Job,long) [Tier0, IL size=32, code size=188] ; Assembly listing for method BenchmarkDotNet.Jobs.JobExtensions+<>c__DisplayClass28_0:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 657: JIT compiled BenchmarkDotNet.Jobs.JobExtensions+<>c__DisplayClass28_0:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Jobs.JobExtensions:WithCore(BenchmarkDotNet.Jobs.Job,System.Action`1[BenchmarkDotNet.Jobs.Job]):BenchmarkDotNet.Jobs.Job ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] str x0, [fp, #0x48] str x1, [fp, #0x40] G_M000_IG02: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr x0, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbnz w0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x20] str x0, [fp, #0x28] b G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x30] ldr x2, [fp, #0x48] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x30] str x0, [fp, #0x28] G_M000_IG04: ldr x0, [fp, #0x28] str x0, [fp, #0x38] ldr x0, [fp, #0x40] ldr x0, [x0, #0x08] ldr x1, [fp, #0x38] ldr x2, [fp, #0x40] ldr x2, [x2, #0x18] blr x2 ldr x0, [fp, #0x38] G_M000_IG05: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 276 658: JIT compiled BenchmarkDotNet.Jobs.JobExtensions:WithCore(BenchmarkDotNet.Jobs.Job,System.Action`1[BenchmarkDotNet.Jobs.Job]) [Tier0, IL size=43, code size=276] ; Assembly listing for method BenchmarkDotNet.Jobs.Job:.ctor(BenchmarkDotNet.Characteristics.CharacteristicObject):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x2, [fp, #0x10] mov x1, xzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 659: JIT compiled BenchmarkDotNet.Jobs.Job:.ctor(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=9, code size=56] ; Assembly listing for method BenchmarkDotNet.Jobs.JobExtensions+<>c__DisplayClass28_0:b__0(BenchmarkDotNet.Jobs.Job):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr x1, [x1, #0x08] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 660: JIT compiled BenchmarkDotNet.Jobs.JobExtensions+<>c__DisplayClass28_0:b__0(BenchmarkDotNet.Jobs.Job) [Tier0, IL size=18, code size=96] ; Assembly listing for method BenchmarkDotNet.Jobs.Job:get_Run():BenchmarkDotNet.Jobs.RunMode:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 64 661: JIT compiled BenchmarkDotNet.Jobs.Job:get_Run() [Tier0, IL size=12, code size=64] ; Assembly listing for method BenchmarkDotNet.Jobs.RunMode:set_InvocationCount(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] ldr x1, [fp, #0x18] ldr x2, [fp, #0x10] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 72 662: JIT compiled BenchmarkDotNet.Jobs.RunMode:set_InvocationCount(long) [Tier0, IL size=13, code size=72] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[long]:set_Item(BenchmarkDotNet.Characteristics.CharacteristicObject,long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] ldr x2, [fp, #0x18] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 64 663: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[long]:set_Item(BenchmarkDotNet.Characteristics.CharacteristicObject,long) [Tier0, IL size=9, code size=64] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue[long](BenchmarkDotNet.Characteristics.Characteristic`1[long],long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x2, [fp, #0x10] ldr x0, [fp, #0x18] str x0, [x2, #0x08] ldr x2, [fp, #0x10] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 664: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue[long](BenchmarkDotNet.Characteristics.Characteristic`1[long],long) [Tier0, IL size=14, code size=96] ; Assembly listing for method BenchmarkDotNet.Jobs.JobExtensions:WithUnrollFactor(BenchmarkDotNet.Jobs.Job,int):BenchmarkDotNet.Jobs.Job ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x38] str w1, [fp, #0x34] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x20] str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr w1, [fp, #0x34] str w1, [x0, #0x08] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x38] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 188 665: JIT compiled BenchmarkDotNet.Jobs.JobExtensions:WithUnrollFactor(BenchmarkDotNet.Jobs.Job,int) [Tier0, IL size=32, code size=188] ; Assembly listing for method BenchmarkDotNet.Jobs.JobExtensions+<>c__DisplayClass29_0:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 666: JIT compiled BenchmarkDotNet.Jobs.JobExtensions+<>c__DisplayClass29_0:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Jobs.JobExtensions+<>c__DisplayClass29_0:b__0(BenchmarkDotNet.Jobs.Job):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr w1, [x1, #0x08] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 667: JIT compiled BenchmarkDotNet.Jobs.JobExtensions+<>c__DisplayClass29_0:b__0(BenchmarkDotNet.Jobs.Job) [Tier0, IL size=18, code size=96] ; Assembly listing for method BenchmarkDotNet.Jobs.JobExtensions:WithEvaluateOverhead(BenchmarkDotNet.Jobs.Job,bool):BenchmarkDotNet.Jobs.Job ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x38] str w1, [fp, #0x34] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x20] str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr w1, [fp, #0x34] strb w1, [x0, #0x08] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x38] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 188 668: JIT compiled BenchmarkDotNet.Jobs.JobExtensions:WithEvaluateOverhead(BenchmarkDotNet.Jobs.Job,bool) [Tier0, IL size=32, code size=188] ; Assembly listing for method BenchmarkDotNet.Jobs.JobExtensions+<>c__DisplayClass58_0:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 669: JIT compiled BenchmarkDotNet.Jobs.JobExtensions+<>c__DisplayClass58_0:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Jobs.JobExtensions+<>c__DisplayClass58_0:b__0(BenchmarkDotNet.Jobs.Job):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldrb w1, [x1, #0x08] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 670: JIT compiled BenchmarkDotNet.Jobs.JobExtensions+<>c__DisplayClass58_0:b__0(BenchmarkDotNet.Jobs.Job) [Tier0, IL size=18, code size=96] ; Assembly listing for method BenchmarkDotNet.Jobs.Job:get_Accuracy():BenchmarkDotNet.Jobs.AccuracyMode:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 64 671: JIT compiled BenchmarkDotNet.Jobs.Job:get_Accuracy() [Tier0, IL size=12, code size=64] ; Assembly listing for method BenchmarkDotNet.Jobs.AccuracyMode:set_EvaluateOverhead(bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] ldr w2, [fp, #0x14] uxtb w2, w2 ldr x1, [fp, #0x18] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 76 672: JIT compiled BenchmarkDotNet.Jobs.AccuracyMode:set_EvaluateOverhead(bool) [Tier0, IL size=13, code size=76] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[bool]:set_Item(BenchmarkDotNet.Characteristics.CharacteristicObject,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] G_M000_IG02: ldr w2, [fp, #0x1C] uxtb w2, w2 ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 68 673: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[bool]:set_Item(BenchmarkDotNet.Characteristics.CharacteristicObject,bool) [Tier0, IL size=9, code size=68] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue[bool](BenchmarkDotNet.Characteristics.Characteristic`1[bool],bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x2, [fp, #0x10] ldr w0, [fp, #0x1C] strb w0, [x2, #0x08] ldr x2, [fp, #0x10] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 674: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:SetValue[bool](BenchmarkDotNet.Characteristics.Characteristic`1[bool],bool) [Tier0, IL size=14, code size=96] ; Assembly listing for method BenchmarkDotNet.Engines.EngineFactory:CreateEngine(BenchmarkDotNet.Engines.EngineParameters,BenchmarkDotNet.Jobs.Job,System.Action`1[long],System.Action`1[long]):BenchmarkDotNet.Engines.Engine ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: sub sp, sp, #224 stp fp, lr, [sp, #0x40] add fp, sp, #64 add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] str xzr, [x9, #0x60] str x0, [fp, #0x98] str x1, [fp, #0x90] str x2, [fp, #0x88] str x3, [fp, #0x80] G_M000_IG02: ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x78] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x70] ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x68] ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x60] ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x58] ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x50] ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x48] ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x40] ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x38] ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x30] ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str w0, [fp, #0x2C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] str x1, [sp, #0x38] ldr x1, [fp, #0x78] ldr x2, [fp, #0x70] ldr x3, [fp, #0x68] ldr x4, [fp, #0x60] ldr x5, [fp, #0x58] ldr x6, [fp, #0x88] ldr x7, [fp, #0x80] ldr x0, [fp, #0x90] str x0, [sp] ldr x0, [fp, #0x50] str x0, [sp, #0x08] ldr x0, [fp, #0x48] str x0, [sp, #0x10] ldr x0, [fp, #0x40] str x0, [sp, #0x18] ldr x0, [fp, #0x38] str x0, [sp, #0x20] ldr x0, [fp, #0x30] str x0, [sp, #0x28] ldr w0, [fp, #0x2C] str w0, [sp, #0x30] ldr x0, [fp, #0x20] movz x8, #0xD1FFAB1E movk x8, #0xD1FFAB1E LSL #16 movk x8, #0xD1FFAB1E LSL #32 ldr x8, [x8] blr x8 ldr x0, [fp, #0x20] G_M000_IG03: ldp fp, lr, [sp, #0x40] add sp, sp, #224 ret lr ; Total bytes of code 576 675: JIT compiled BenchmarkDotNet.Engines.EngineFactory:CreateEngine(BenchmarkDotNet.Engines.EngineParameters,BenchmarkDotNet.Jobs.Job,System.Action`1[long],System.Action`1[long]) [Tier0, IL size=80, code size=576] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_Host():BenchmarkDotNet.Engines.IHost:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 676: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_Host() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_GlobalCleanupAction():System.Action:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x58] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 677: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_GlobalCleanupAction() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_IterationSetupAction():System.Action:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x60] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 678: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_IterationSetupAction() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_IterationCleanupAction():System.Action:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x68] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 679: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_IterationCleanupAction() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_OperationsPerInvoke():long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x78] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 680: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_OperationsPerInvoke() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_MeasureExtraStats():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldrb w0, [x0, #0x80] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 681: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_MeasureExtraStats() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_BenchmarkName():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x70] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 682: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_BenchmarkName() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:.ctor(BenchmarkDotNet.Engines.IHost,BenchmarkDotNet.Characteristics.IResolver,System.Action,System.Action,System.Action,System.Action`1[long],System.Action`1[long],BenchmarkDotNet.Jobs.Job,System.Action,System.Action,System.Action,System.Action,long,bool,System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xE0]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] str xzr, [x9, #0x80] str x0, [fp, #0xD8] str x1, [fp, #0xD0] str x2, [fp, #0xC8] str x3, [fp, #0xC0] str x4, [fp, #0xB8] str x5, [fp, #0xB0] str x6, [fp, #0xA8] str x7, [fp, #0xA0] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x98] ldr x0, [fp, #0x98] mov w1, #10 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0xD8] add x14, x14, #128 ldr x15, [fp, #0x98] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0xD8] add x14, x14, #8 ldr x15, [fp, #0xD0] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0xD8] add x14, x14, #48 ldr x15, [fp, #0xA8] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0xD8] add x14, x14, #24 ldr x15, [fp, #0xC0] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0xD8] add x14, x14, #32 ldr x15, [fp, #0xB8] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0xD8] add x14, x14, #40 ldr x15, [fp, #0xB0] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0xD8] add x14, x14, #16 ldr x15, [fp, #0xA0] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0xD8] add x14, x14, #56 ldr x15, [fp, #0xE0] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0xD8] add x14, x14, #64 ldr x15, [fp, #0xE8] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0xD8] add x14, x14, #72 ldr x15, [fp, #0xF0] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0xD8] add x14, x14, #80 ldr x15, [fp, #0xF8] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0xD8] add x14, x14, #88 ldr x15, [fp, #0xD1FFAB1E] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0xD8] ldr x15, [fp, #0xD1FFAB1E] str x15, [x14, #0xA8] ldr x14, [fp, #0xD8] ldr w15, [fp, #0xD1FFAB1E] strb w15, [x14, #0xBB] ldr x14, [fp, #0xD8] add x14, x14, #112 ldr x15, [fp, #0xD1FFAB1E] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0xD8] add x14, x14, #96 ldr x15, [fp, #0xC8] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x90] ldr x0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x40] ldr x3, [fp, #0x40] ldr x0, [fp, #0xE0] ldr x2, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] ldr wzr, [x0] blr x4 ldr x14, [fp, #0xD8] add x14, x14, #120 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x88] ldr x0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x38] ldr x2, [fp, #0x38] ldr x1, [fp, #0x88] ldr x0, [fp, #0xE0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr x1, [fp, #0xD8] strb w0, [x1, #0xB8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x80] ldr x0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x30] ldr x2, [fp, #0x30] ldr x1, [fp, #0x80] ldr x0, [fp, #0xE0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr x1, [fp, #0xD8] str w0, [x1, #0xB0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x78] ldr x0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x28] ldr x2, [fp, #0x28] ldr x1, [fp, #0x78] ldr x0, [fp, #0xE0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr x1, [fp, #0xD8] str w0, [x1, #0xB4] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x70] ldr x0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x20] ldr x2, [fp, #0x20] ldr x1, [fp, #0x70] ldr x0, [fp, #0xE0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 G_M000_IG03: movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr x1, [fp, #0xD8] strb w0, [x1, #0xB9] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x68] ldr x0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x2, [fp, #0x18] ldr x1, [fp, #0x68] ldr x0, [fp, #0xE0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr x1, [fp, #0xD8] strb w0, [x1, #0xBA] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x60] ldr x0, [fp, #0x60] ldr x1, [fp, #0xD8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0xD8] add x14, x14, #144 ldr x15, [fp, #0x60] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x58] ldr x0, [fp, #0x58] ldr x1, [fp, #0xD8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0xD8] add x14, x14, #136 ldr x15, [fp, #0x58] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x50] ldr x0, [fp, #0x50] ldr x1, [fp, #0xD8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0xD8] add x14, x14, #152 ldr x15, [fp, #0x50] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] ldr x0, [fp, #0x48] mov w1, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0xD8] add x14, x14, #160 ldr x15, [fp, #0x48] bl CORINFO_HELP_ASSIGN_REF G_M000_IG04: ldp fp, lr, [sp], #0xE0 ret lr ; Total bytes of code 1224 683: JIT compiled BenchmarkDotNet.Engines.Engine:.ctor(BenchmarkDotNet.Engines.IHost,BenchmarkDotNet.Characteristics.IResolver,System.Action,System.Action,System.Action,System.Action`1[long],System.Action`1[long],BenchmarkDotNet.Jobs.Job,System.Action,System.Action,System.Action,System.Action,long,bool,System.String) [Tier0, IL size=333, code size=1224] ; Assembly listing for method System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:.ctor(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w0, [fp, #0x14] tbz w0, #31, G_M000_IG03 mov w0, #22 mov w1, #13 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldr w0, [fp, #0x14] cbnz w0, G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #47 bl CORINFO_HELP_CLASSINIT_SHARED_DYNAMICCLASS movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 ldr x15, [x14] ldr x14, [fp, #0x18] add x14, x14, #8 bl CORINFO_HELP_ASSIGN_REF G_M000_IG04: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG05: ldr w1, [fp, #0x14] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC ldr x14, [fp, #0x18] add x14, x14, #8 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG06: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 188 684: JIT compiled System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:.ctor(int) [Tier0, IL size=47, code size=188] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_Resolver():BenchmarkDotNet.Characteristics.IResolver:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x60] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 685: JIT compiled BenchmarkDotNet.Engines.Engine:get_Resolver() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValue[System.__Canon](BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon],BenchmarkDotNet.Characteristics.IResolver):System.__Canon:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str x1, [fp, #0x48] str x0, [fp, #0x40] str x1, [fp, #0x38] str x2, [fp, #0x30] str x3, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x38] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x38] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x20] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x20] G_M000_IG05: ldr x0, [fp, #0x28] ldr x2, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x18] ldr x0, [fp, #0x28] ldr x1, [fp, #0x40] ldr x2, [fp, #0x30] ldr x3, [fp, #0x18] blr x3 G_M000_IG06: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 144 686: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValue[System.__Canon](BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon],BenchmarkDotNet.Characteristics.IResolver) [Tier0, IL size=9, code size=144] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver:Resolve[System.__Canon](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon]):System.__Canon:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] str x1, [fp, #0x98] str x0, [fp, #0x90] str x1, [fp, #0x88] str x2, [fp, #0x80] str x3, [fp, #0x78] G_M000_IG02: ldr x0, [fp, #0x88] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x88] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x58] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x58] G_M000_IG05: ldr x0, [fp, #0x58] bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x60] ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x60] str x14, [fp, #0x70] ldr x14, [fp, #0x70] add x14, x14, #8 ldr x15, [fp, #0x78] bl CORINFO_HELP_ASSIGN_REF ldr x1, [fp, #0x70] ldr x1, [x1, #0x08] ldr x0, [fp, #0x80] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG07 ldr x0, [fp, #0x70] ldr x0, [x0, #0x08] ldr x1, [fp, #0x80] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG06: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG07: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x50] ldr x0, [fp, #0x90] ldr x0, [x0, #0x08] str x0, [fp, #0x48] ldr x0, [fp, #0x50] ldr x1, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x2, [fp, #0x50] ldr x1, [fp, #0x48] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x68] ldr x0, [fp, #0x68] cbz x0, G_M000_IG12 ldr x0, [fp, #0x88] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] cbz x0, G_M000_IG09 G_M000_IG08: ldr x0, [fp, #0x88] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] str x0, [fp, #0x38] b G_M000_IG10 G_M000_IG09: ldr x0, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x38] G_M000_IG10: ldr x0, [fp, #0x68] ldr x2, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x30] ldr x2, [fp, #0x70] ldr x2, [x2, #0x08] ldr x0, [fp, #0x68] ldr x1, [fp, #0x80] ldr x3, [fp, #0x30] blr x3 G_M000_IG11: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG12: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x40] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] ldr x0, [fp, #0x70] ldr x0, [x0, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x40] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x40] bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 652 687: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver:Resolve[System.__Canon](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon]) [Tier0, IL size=108, code size=652] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[System.__Canon]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 688: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[System.__Canon]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[System.__Canon]:b__0(BenchmarkDotNet.Characteristics.IResolver):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x1, [fp, #0x18] ldr x1, [x1, #0x08] ldr x0, [fp, #0x10] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 689: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[System.__Canon]:b__0(BenchmarkDotNet.Characteristics.IResolver) [Tier0, IL size=13, code size=56] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:Resolve[System.__Canon](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon]):System.__Canon:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x1, [fp, #0x68] str x0, [fp, #0x60] str x1, [fp, #0x58] str x2, [fp, #0x50] str x3, [fp, #0x48] G_M000_IG02: ldr x0, [fp, #0x50] ldr x1, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG04 ldr x0, [fp, #0x48] ldr x1, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG04: ldr x0, [fp, #0x60] ldr x0, [x0, #0x08] add x2, fp, #64 ldr x1, [fp, #0x48] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 cbz w0, G_M000_IG06 ldr x0, [fp, #0x40] ldr x0, [x0, #0x08] ldr x1, [fp, #0x50] ldr x2, [fp, #0x40] ldr x2, [x2, #0x18] blr x2 str x0, [fp, #0x30] ldr x1, [fp, #0x30] ldr x0, [fp, #0x58] ldr x0, [x0, #0x10] ldr x0, [x0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG05: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x38] bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 388 690: JIT compiled BenchmarkDotNet.Characteristics.Resolver:Resolve[System.__Canon](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[System.__Canon]) [Tier0, IL size=68, code size=388] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[System.__Canon]:b__0(BenchmarkDotNet.Characteristics.CharacteristicObject):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] ldr x1, [fp, #0x18] ldr x1, [x1, #0x18] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 60 691: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[System.__Canon]:b__0(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=17, code size=60] ; Assembly listing for method BenchmarkDotNet.Environments.InfrastructureResolver+<>c:<.ctor>b__1_0():Perfolizer.Horology.IClock:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #70 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 692: JIT compiled BenchmarkDotNet.Environments.InfrastructureResolver+<>c:<.ctor>b__1_0() [Tier0, IL size=6, code size=56] ; Assembly listing for method Perfolizer.Horology.Chronometer:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x28] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x20] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x10] ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbz w0, G_M000_IG04 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 ldr x15, [x14] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 ldr x15, [x14] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 388 693: JIT compiled Perfolizer.Horology.Chronometer:.cctor() [Tier0, IL size=76, code size=388] ; Assembly listing for method Perfolizer.Horology.StopwatchClock:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 694: JIT compiled Perfolizer.Horology.StopwatchClock:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method Perfolizer.Horology.DateTimeClock:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 695: JIT compiled Perfolizer.Horology.DateTimeClock:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method Perfolizer.Horology.WindowsClock:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #83 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 64 696: JIT compiled Perfolizer.Horology.WindowsClock:.ctor() [Tier0, IL size=7, code size=64] ; Assembly listing for method Perfolizer.Horology.WindowsClock:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 strb w0, [x1] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 64 697: JIT compiled Perfolizer.Horology.WindowsClock:.cctor() [Tier0, IL size=16, code size=64] ; Assembly listing for method Perfolizer.Horology.WindowsClock:Initialize(byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] add x1, sp, #80 str x1, [fp, #0x48] str x0, [fp, #0x40] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #83 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG04 ldr x0, [fp, #0x40] str xzr, [x0] mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG04: ldr x0, [fp, #0x40] bl Perfolizer.Horology.WindowsClock:QueryPerformanceFrequency(byref):bool cbz w0, G_M000_IG05 add x0, fp, #56 bl Perfolizer.Horology.WindowsClock:QueryPerformanceCounter(byref):bool str w0, [fp, #0x24] b G_M000_IG06 G_M000_IG05: str wzr, [fp, #0x24] G_M000_IG06: ldr w0, [fp, #0x24] uxtb w0, w0 str w0, [fp, #0x34] b G_M000_IG07 G_M000_IG07: ldr w0, [fp, #0x34] G_M000_IG08: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG09: stp fp, lr, [sp, #-0x20]! add x3, fp, #80 str x3, [sp, #0x18] G_M000_IG10: str x0, [fp, #0x18] ldr x0, [fp, #0x40] str xzr, [x0] str wzr, [fp, #0x34] adr x0, [G_M000_IG07] G_M000_IG11: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 228 698: JIT compiled Perfolizer.Horology.WindowsClock:Initialize(byref) [Tier0, IL size=51, code size=228] ; Assembly listing for method (dynamicClass):IL_STUB_PInvoke(byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0xC0]! stp x19, x20, [sp, #0x70] stp x21, x22, [sp, #0x80] stp x23, x24, [sp, #0x90] stp x25, x26, [sp, #0xA0] stp x27, x28, [sp, #0xB0] mov fp, sp str x12, [fp, #0x60] str xzr, [fp, #0x68] mov x19, x0 G_M000_IG02: add x0, fp, #32 mov x1, x12 bl CORINFO_HELP_INIT_PINVOKE_FRAME mov x20, x0 mov x0, sp str x0, [fp, #0x40] mov x0, fp str x0, [fp, #0x50] add x0, fp, #32 str x0, [x20, #0x10] str x19, [fp, #0x68] ldr x0, [fp, #0x60] ldr x0, [x0, #0x18] ldr x1, [x0] mov x0, x19 ldr x2, [fp, #0x60] str x2, [fp, #0x30] adr x2, [G_M000_IG04] str x2, [fp, #0x48] strb wzr, [x20, #0x0C] G_M000_IG03: blr x1 G_M000_IG04: mov w19, w0 mov w0, #1 strb w0, [x20, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG05 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG05: cmp w19, #0 cset x0, ne uxtb w0, w0 ldr x1, [fp, #0x28] str x1, [x20, #0x10] G_M000_IG06: ldp x27, x28, [sp, #0xB0] ldp x25, x26, [sp, #0xA0] ldp x23, x24, [sp, #0x90] ldp x21, x22, [sp, #0x80] ldp x19, x20, [sp, #0x70] ldp fp, lr, [sp], #0xC0 ret lr ; Total bytes of code 212 699: JIT compiled (dynamicClass):IL_STUB_PInvoke(byref) [FullOpts, IL size=40, code size=212] ; Assembly listing for method Perfolizer.Horology.WindowsClock:get_IsAvailable():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldrb w0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 36 700: JIT compiled Perfolizer.Horology.WindowsClock:get_IsAvailable() [Tier0, IL size=6, code size=36] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValue[bool](BenchmarkDotNet.Characteristics.Characteristic`1[bool],BenchmarkDotNet.Characteristics.IResolver):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x10] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] ldr x3, [fp, #0x10] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 701: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValue[bool](BenchmarkDotNet.Characteristics.Characteristic`1[bool],BenchmarkDotNet.Characteristics.IResolver) [Tier0, IL size=9, code size=84] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver:Resolve[bool](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[bool]):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str x0, [fp, #0x78] str x1, [fp, #0x70] str x2, [fp, #0x68] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x50] ldr x0, [fp, #0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x50] str x14, [fp, #0x60] ldr x14, [fp, #0x60] add x14, x14, #8 ldr x15, [fp, #0x68] bl CORINFO_HELP_ASSIGN_REF ldr x1, [fp, #0x60] ldr x1, [x1, #0x08] ldr x0, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG04 ldr x0, [fp, #0x60] ldr x0, [x0, #0x08] ldr x1, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] ldr x0, [fp, #0x78] ldr x0, [x0, #0x08] str x0, [fp, #0x40] ldr x0, [fp, #0x48] ldr x1, [fp, #0x60] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x2, [fp, #0x48] ldr x1, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x58] ldr x0, [fp, #0x58] cbz x0, G_M000_IG06 ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x30] ldr x2, [fp, #0x60] ldr x2, [x2, #0x08] ldr x0, [fp, #0x58] ldr x1, [fp, #0x70] ldr x3, [fp, #0x30] blr x3 G_M000_IG05: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] ldr x0, [fp, #0x60] ldr x0, [x0, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x38] bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 540 702: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver:Resolve[bool](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[bool]) [Tier0, IL size=108, code size=540] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[bool]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 703: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[bool]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[bool]:b__0(BenchmarkDotNet.Characteristics.IResolver):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x1, [fp, #0x18] ldr x1, [x1, #0x08] ldr x0, [fp, #0x10] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 704: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[bool]:b__0(BenchmarkDotNet.Characteristics.IResolver) [Tier0, IL size=13, code size=56] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:Resolve[bool](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[bool]):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x0, [fp, #0x58] str x1, [fp, #0x50] str x2, [fp, #0x48] G_M000_IG02: ldr x0, [fp, #0x50] ldr x1, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG04 ldr x0, [fp, #0x48] ldr x1, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG04: ldr x0, [fp, #0x58] ldr x0, [x0, #0x08] add x2, fp, #64 ldr x1, [fp, #0x48] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 cbz w0, G_M000_IG06 ldr x0, [fp, #0x40] ldr x0, [x0, #0x08] ldr x1, [fp, #0x50] ldr x2, [fp, #0x40] ldr x2, [x2, #0x18] blr x2 str x0, [fp, #0x30] ldr x1, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldrb w0, [x0] G_M000_IG05: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x38] bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 384 705: JIT compiled BenchmarkDotNet.Characteristics.Resolver:Resolve[bool](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[bool]) [Tier0, IL size=68, code size=384] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[bool]:b__0(BenchmarkDotNet.Characteristics.CharacteristicObject):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x08] ldr x1, [fp, #0x10] ldr x1, [x1, #0x18] blr x1 ldr x1, [fp, #0x18] strb w0, [x1, #0x08] ldr x0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 706: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[bool]:b__0(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=17, code size=96] ; Assembly listing for method BenchmarkDotNet.Environments.GcResolver+<>c:<.ctor>b__1_3():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: mov w0, #1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 24 707: JIT compiled BenchmarkDotNet.Environments.GcResolver+<>c:<.ctor>b__1_3() [Tier0, IL size=2, code size=24] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],BenchmarkDotNet.Characteristics.IResolver):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x10] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] ldr x3, [fp, #0x10] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 708: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],BenchmarkDotNet.Characteristics.IResolver) [Tier0, IL size=9, code size=84] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver:Resolve[int](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[int]):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str x0, [fp, #0x78] str x1, [fp, #0x70] str x2, [fp, #0x68] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x50] ldr x0, [fp, #0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x50] str x14, [fp, #0x60] ldr x14, [fp, #0x60] add x14, x14, #8 ldr x15, [fp, #0x68] bl CORINFO_HELP_ASSIGN_REF ldr x1, [fp, #0x60] ldr x1, [x1, #0x08] ldr x0, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG04 ldr x0, [fp, #0x60] ldr x0, [x0, #0x08] ldr x1, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] ldr x0, [fp, #0x78] ldr x0, [x0, #0x08] str x0, [fp, #0x40] ldr x0, [fp, #0x48] ldr x1, [fp, #0x60] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x2, [fp, #0x48] ldr x1, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x58] ldr x0, [fp, #0x58] cbz x0, G_M000_IG06 ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x30] ldr x2, [fp, #0x60] ldr x2, [x2, #0x08] ldr x0, [fp, #0x58] ldr x1, [fp, #0x70] ldr x3, [fp, #0x30] blr x3 G_M000_IG05: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] ldr x0, [fp, #0x60] ldr x0, [x0, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x38] bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 540 709: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver:Resolve[int](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[int]) [Tier0, IL size=108, code size=540] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[int]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 710: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[int]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[int]:get_Item(BenchmarkDotNet.Characteristics.CharacteristicObject):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 711: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[int]:get_Item(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=8, code size=56] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:GetValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int]):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 100 712: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:GetValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int]) [Tier0, IL size=13, code size=100] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[bool]:get_Item(BenchmarkDotNet.Characteristics.CharacteristicObject):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 713: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[bool]:get_Item(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=8, code size=56] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:GetValue[bool](BenchmarkDotNet.Characteristics.Characteristic`1[bool]):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldrb w0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 100 714: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:GetValue[bool](BenchmarkDotNet.Characteristics.Characteristic`1[bool]) [Tier0, IL size=13, code size=100] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[bool]:ResolveValueCore(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Object):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] G_M000_IG02: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz x0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x38] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x20] ldr x1, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldrb w0, [x0] ldr x1, [fp, #0x28] strb w0, [x1, #0x08] ldr x0, [fp, #0x28] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG04: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x38] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x18] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldrb w2, [x0] str w2, [fp, #0x14] ldr w2, [fp, #0x14] ldr x1, [fp, #0x40] ldr x0, [fp, #0x30] ldr x0, [x0, #0x08] ldr x3, [fp, #0x30] ldr x3, [x3, #0x18] blr x3 ldr x1, [fp, #0x28] strb w0, [x1, #0x08] ldr x0, [fp, #0x28] G_M000_IG05: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 356 715: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[bool]:ResolveValueCore(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Object) [Tier0, IL size=58, code size=356] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[bool]:get_Resolver():System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,bool,bool]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 716: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[bool]:get_Resolver() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EngineResolver+<>c:<.ctor>b__7_10():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 24 717: JIT compiled BenchmarkDotNet.Engines.EngineResolver+<>c:<.ctor>b__7_10() [Tier0, IL size=2, code size=24] ; Assembly listing for method BenchmarkDotNet.Engines.EngineWarmupStage:.ctor(BenchmarkDotNet.Engines.IEngine):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x18] add x14, x14, #16 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 68 718: JIT compiled BenchmarkDotNet.Engines.EngineWarmupStage:.ctor(BenchmarkDotNet.Engines.IEngine) [Tier0, IL size=15, code size=68] ; Assembly listing for method BenchmarkDotNet.Engines.EngineStage:.ctor(BenchmarkDotNet.Engines.IEngine):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x18] add x14, x14, #8 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 64 719: JIT compiled BenchmarkDotNet.Engines.EngineStage:.ctor(BenchmarkDotNet.Engines.IEngine) [Tier0, IL size=14, code size=64] ; Assembly listing for method BenchmarkDotNet.Engines.EnginePilotStage:.ctor(BenchmarkDotNet.Engines.IEngine):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xD0]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] stp q16, q16, [x9, #0x80] stp xzr, xzr, [x9, #0xA0] str x0, [fp, #0xC8] str x1, [fp, #0xC0] G_M000_IG02: ldr x0, [fp, #0xC8] ldr x1, [fp, #0xC0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xC0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0xB0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xA8] ldr x0, [fp, #0xC0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x40] ldr x2, [fp, #0x40] ldr x1, [fp, #0xA8] ldr x0, [fp, #0xB0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr x11, [fp, #0xC8] str w0, [x11, #0x28] ldr x0, [fp, #0xC0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0xA0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x98] ldr x0, [fp, #0xC0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x38] ldr x2, [fp, #0x38] ldr x1, [fp, #0x98] ldr x0, [fp, #0xA0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr x0, [fp, #0xC8] str d0, [x0, #0x30] ldr x0, [fp, #0xC0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x90] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x88] ldr x0, [fp, #0xC0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x30] ldr x2, [fp, #0x30] ldr x1, [fp, #0x88] ldr x0, [fp, #0x90] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr x11, [fp, #0xC8] str w0, [x11, #0x2C] ldr x0, [fp, #0xC0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x80] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x78] ldr x0, [fp, #0xC0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x28] ldr x2, [fp, #0x28] ldr x1, [fp, #0x78] ldr x0, [fp, #0x80] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr x0, [fp, #0xC8] str d0, [x0, #0x10] ldr x0, [fp, #0xC0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 str x0, [fp, #0x68] str x1, [fp, #0x70] ldr x0, [fp, #0xC8] ldp x1, x2, [fp, #0x68] stp x1, x2, [x0, #0x38] ldr x0, [fp, #0xC0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x60] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x58] ldr x0, [fp, #0xC0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x18] ldr x2, [fp, #0x18] ldr x1, [fp, #0x58] ldr x0, [fp, #0x60] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 str d0, [fp, #0xB8] add x0, fp, #184 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xC8] str d0, [x0, #0x18] ldr x0, [fp, #0xC0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x50] G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x48] ldr x0, [fp, #0xC0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x10] ldr x3, [fp, #0x10] ldr x0, [fp, #0x50] ldr x2, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] ldr wzr, [x0] blr x4 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0xB8] add x0, fp, #184 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xC8] str d0, [x0, #0x20] G_M000_IG04: ldp fp, lr, [sp], #0xD0 ret lr ; Total bytes of code 984 720: JIT compiled BenchmarkDotNet.Engines.EnginePilotStage:.ctor(BenchmarkDotNet.Engines.IEngine) [Tier0, IL size=219, code size=984] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_TargetJob():BenchmarkDotNet.Jobs.Job:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x38] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 721: JIT compiled BenchmarkDotNet.Engines.Engine:get_TargetJob() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValue[Perfolizer.Horology.TimeInterval](BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval],BenchmarkDotNet.Characteristics.IResolver):Perfolizer.Horology.TimeInterval:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x10] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] ldr x3, [fp, #0x10] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 722: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValue[Perfolizer.Horology.TimeInterval](BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval],BenchmarkDotNet.Characteristics.IResolver) [Tier0, IL size=9, code size=84] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver:Resolve[Perfolizer.Horology.TimeInterval](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval]):Perfolizer.Horology.TimeInterval:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str x0, [fp, #0x78] str x1, [fp, #0x70] str x2, [fp, #0x68] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x50] ldr x0, [fp, #0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x50] str x14, [fp, #0x60] ldr x14, [fp, #0x60] add x14, x14, #8 ldr x15, [fp, #0x68] bl CORINFO_HELP_ASSIGN_REF ldr x1, [fp, #0x60] ldr x1, [x1, #0x08] ldr x0, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG04 ldr x0, [fp, #0x60] ldr x0, [x0, #0x08] ldr x1, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] ldr x0, [fp, #0x78] ldr x0, [x0, #0x08] str x0, [fp, #0x40] ldr x0, [fp, #0x48] ldr x1, [fp, #0x60] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x2, [fp, #0x48] ldr x1, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x58] ldr x0, [fp, #0x58] cbz x0, G_M000_IG06 ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x30] ldr x2, [fp, #0x60] ldr x2, [x2, #0x08] ldr x0, [fp, #0x58] ldr x1, [fp, #0x70] ldr x3, [fp, #0x30] blr x3 G_M000_IG05: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] ldr x0, [fp, #0x60] ldr x0, [x0, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x38] bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 540 723: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver:Resolve[Perfolizer.Horology.TimeInterval](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval]) [Tier0, IL size=108, code size=540] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[Perfolizer.Horology.TimeInterval]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 724: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[Perfolizer.Horology.TimeInterval]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[Perfolizer.Horology.TimeInterval]:b__0(BenchmarkDotNet.Characteristics.IResolver):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x1, [fp, #0x18] ldr x1, [x1, #0x08] ldr x0, [fp, #0x10] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 725: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[Perfolizer.Horology.TimeInterval]:b__0(BenchmarkDotNet.Characteristics.IResolver) [Tier0, IL size=13, code size=56] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:Resolve[Perfolizer.Horology.TimeInterval](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval]):Perfolizer.Horology.TimeInterval:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x0, [fp, #0x58] str x1, [fp, #0x50] str x2, [fp, #0x48] G_M000_IG02: ldr x0, [fp, #0x50] ldr x1, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG04 ldr x0, [fp, #0x48] ldr x1, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG04: ldr x0, [fp, #0x58] ldr x0, [x0, #0x08] add x2, fp, #64 ldr x1, [fp, #0x48] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 cbz w0, G_M000_IG06 ldr x0, [fp, #0x40] ldr x0, [x0, #0x08] ldr x1, [fp, #0x50] ldr x2, [fp, #0x40] ldr x2, [x2, #0x18] blr x2 str x0, [fp, #0x30] ldr x1, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr d0, [x0] G_M000_IG05: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x38] bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 384 726: JIT compiled BenchmarkDotNet.Characteristics.Resolver:Resolve[Perfolizer.Horology.TimeInterval](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval]) [Tier0, IL size=68, code size=384] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[Perfolizer.Horology.TimeInterval]:b__0(BenchmarkDotNet.Characteristics.CharacteristicObject):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x08] ldr x1, [fp, #0x10] ldr x1, [x1, #0x18] blr x1 ldr x0, [fp, #0x18] str d0, [x0, #0x08] ldr x0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 727: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[Perfolizer.Horology.TimeInterval]:b__0(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=17, code size=96] ; Assembly listing for method BenchmarkDotNet.Engines.EngineResolver+<>c:<.ctor>b__7_7():Perfolizer.Horology.TimeInterval:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #80 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr d0, [x0] str d0, [fp, #0x10] ldr d0, [fp, #0x10] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 88 728: JIT compiled BenchmarkDotNet.Engines.EngineResolver+<>c:<.ctor>b__7_7() [Tier0, IL size=16, code size=88] ; Assembly listing for method Perfolizer.Horology.TimeInterval:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] mov x1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str d0, [x0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] mov x1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str d0, [x0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] mov x1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str d0, [x0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] mov x1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str d0, [x0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] mov x1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str d0, [x0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] mov x1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str d0, [x0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] mov x1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str d0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 436 729: JIT compiled Perfolizer.Horology.TimeInterval:.cctor() [Tier0, IL size=120, code size=436] ; Assembly listing for method Perfolizer.Horology.TimeUnit:ToInterval(long):Perfolizer.Horology.TimeInterval:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: str xzr, [fp, #0x18] ldr x0, [fp, #0x20] scvtf d0, x0 add x0, fp, #24 ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr d0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 68 730: JIT compiled Perfolizer.Horology.TimeUnit:ToInterval(long) [Tier0, IL size=9, code size=68] ; Assembly listing for method Perfolizer.Horology.TimeInterval:.ctor(double,Perfolizer.Horology.TimeUnit):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x18] str d0, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 scvtf d0, x0 ldr d16, [fp, #0x20] fmul d0, d0, d16 str d0, [fp, #0x10] ldr d0, [fp, #0x10] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 100 731: JIT compiled Perfolizer.Horology.TimeInterval:.ctor(double,Perfolizer.Horology.TimeUnit) [Tier0, IL size=16, code size=100] ; Assembly listing for method Perfolizer.Horology.TimeInterval:op_Multiply(Perfolizer.Horology.TimeInterval,int):Perfolizer.Horology.TimeInterval ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str w0, [fp, #0x24] str d0, [fp, #0x28] G_M000_IG02: str xzr, [fp, #0x18] add x0, fp, #40 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w0, [fp, #0x24] scvtf d16, w0 fmul d0, d0, d16 str d0, [fp, #0x10] ldr d0, [fp, #0x10] add x0, fp, #24 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 100 732: JIT compiled Perfolizer.Horology.TimeInterval:op_Multiply(Perfolizer.Horology.TimeInterval,int) [Tier0, IL size=16, code size=100] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[int]:b__0(BenchmarkDotNet.Characteristics.IResolver):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x1, [fp, #0x18] ldr x1, [x1, #0x08] ldr x0, [fp, #0x10] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 733: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[int]:b__0(BenchmarkDotNet.Characteristics.IResolver) [Tier0, IL size=13, code size=56] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:Resolve[int](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[int]):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x0, [fp, #0x58] str x1, [fp, #0x50] str x2, [fp, #0x48] G_M000_IG02: ldr x0, [fp, #0x50] ldr x1, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG04 ldr x0, [fp, #0x48] ldr x1, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG04: ldr x0, [fp, #0x58] ldr x0, [x0, #0x08] add x2, fp, #64 ldr x1, [fp, #0x48] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 cbz w0, G_M000_IG06 ldr x0, [fp, #0x40] ldr x0, [x0, #0x08] ldr x1, [fp, #0x50] ldr x2, [fp, #0x40] ldr x2, [x2, #0x18] blr x2 str x0, [fp, #0x30] ldr x1, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [x0] G_M000_IG05: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x38] bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 384 734: JIT compiled BenchmarkDotNet.Characteristics.Resolver:Resolve[int](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[int]) [Tier0, IL size=68, code size=384] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[int]:b__0(BenchmarkDotNet.Characteristics.CharacteristicObject):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x08] ldr x1, [fp, #0x10] ldr x1, [x1, #0x18] blr x1 ldr x1, [fp, #0x18] str w0, [x1, #0x08] ldr x0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 735: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[int]:b__0(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=17, code size=96] ; Assembly listing for method BenchmarkDotNet.Engines.EngineResolver+<>c:<.ctor>b__7_8():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: mov w0, #4 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 24 736: JIT compiled BenchmarkDotNet.Engines.EngineResolver+<>c:<.ctor>b__7_8() [Tier0, IL size=2, code size=24] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValue[double](BenchmarkDotNet.Characteristics.Characteristic`1[double],BenchmarkDotNet.Characteristics.IResolver):double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x10] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] ldr x3, [fp, #0x10] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 737: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValue[double](BenchmarkDotNet.Characteristics.Characteristic`1[double],BenchmarkDotNet.Characteristics.IResolver) [Tier0, IL size=9, code size=84] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver:Resolve[double](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[double]):double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str x0, [fp, #0x78] str x1, [fp, #0x70] str x2, [fp, #0x68] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x50] ldr x0, [fp, #0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x50] str x14, [fp, #0x60] ldr x14, [fp, #0x60] add x14, x14, #8 ldr x15, [fp, #0x68] bl CORINFO_HELP_ASSIGN_REF ldr x1, [fp, #0x60] ldr x1, [x1, #0x08] ldr x0, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG04 ldr x0, [fp, #0x60] ldr x0, [x0, #0x08] ldr x1, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] ldr x0, [fp, #0x78] ldr x0, [x0, #0x08] str x0, [fp, #0x40] ldr x0, [fp, #0x48] ldr x1, [fp, #0x60] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x2, [fp, #0x48] ldr x1, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x58] ldr x0, [fp, #0x58] cbz x0, G_M000_IG06 ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x30] ldr x2, [fp, #0x60] ldr x2, [x2, #0x08] ldr x0, [fp, #0x58] ldr x1, [fp, #0x70] ldr x3, [fp, #0x30] blr x3 G_M000_IG05: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] ldr x0, [fp, #0x60] ldr x0, [x0, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x38] bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 540 738: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver:Resolve[double](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[double]) [Tier0, IL size=108, code size=540] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[double]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 739: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[double]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[double]:b__0(BenchmarkDotNet.Characteristics.IResolver):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x1, [fp, #0x18] ldr x1, [x1, #0x08] ldr x0, [fp, #0x10] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 740: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[double]:b__0(BenchmarkDotNet.Characteristics.IResolver) [Tier0, IL size=13, code size=56] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:Resolve[double](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[double]):double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x0, [fp, #0x58] str x1, [fp, #0x50] str x2, [fp, #0x48] G_M000_IG02: ldr x0, [fp, #0x50] ldr x1, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG04 ldr x0, [fp, #0x48] ldr x1, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG04: ldr x0, [fp, #0x58] ldr x0, [x0, #0x08] add x2, fp, #64 ldr x1, [fp, #0x48] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 cbz w0, G_M000_IG06 ldr x0, [fp, #0x40] ldr x0, [x0, #0x08] ldr x1, [fp, #0x50] ldr x2, [fp, #0x40] ldr x2, [x2, #0x18] blr x2 str x0, [fp, #0x30] ldr x1, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr d0, [x0] G_M000_IG05: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x38] bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 384 741: JIT compiled BenchmarkDotNet.Characteristics.Resolver:Resolve[double](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[double]) [Tier0, IL size=68, code size=384] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[double]:b__0(BenchmarkDotNet.Characteristics.CharacteristicObject):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x08] ldr x1, [fp, #0x10] ldr x1, [x1, #0x18] blr x1 ldr x0, [fp, #0x18] str d0, [x0, #0x08] ldr x0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 742: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass1_0`1[double]:b__0(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=17, code size=96] ; Assembly listing for method BenchmarkDotNet.Engines.EngineResolver+<>c:<.ctor>b__7_6():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr d0, [@RWD00] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr RWD00 dq 3F947AE147AE147Bh ; 0.02 ; Total bytes of code 24 743: JIT compiled BenchmarkDotNet.Engines.EngineResolver+<>c:<.ctor>b__7_6() [Tier0, IL size=10, code size=24] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValueAsNullable[Perfolizer.Horology.TimeInterval](BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval]):System.Nullable`1[Perfolizer.Horology.TimeInterval]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x38] str x0, [fp, #0x48] str x1, [fp, #0x40] G_M000_IG02: ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG04 movi v16.4s, #0 str q16, [fp, #0x30] ldr x0, [fp, #0x30] ldr x1, [fp, #0x38] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG04: movi v16.4s, #0 str q16, [fp, #0x20] ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str d0, [fp, #0x18] add x0, fp, #32 ldr d0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] G_M000_IG05: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 164 744: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValueAsNullable[Perfolizer.Horology.TimeInterval](BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval]) [Tier0, IL size=32, code size=164] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval]:get_Item(BenchmarkDotNet.Characteristics.CharacteristicObject):Perfolizer.Horology.TimeInterval:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 745: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval]:get_Item(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=8, code size=56] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:GetValue[Perfolizer.Horology.TimeInterval](BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval]):Perfolizer.Horology.TimeInterval:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr d0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 100 746: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:GetValue[Perfolizer.Horology.TimeInterval](BenchmarkDotNet.Characteristics.Characteristic`1[Perfolizer.Horology.TimeInterval]) [Tier0, IL size=13, code size=100] ; Assembly listing for method Perfolizer.Horology.TimeInterval:ToNanoseconds():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr d1, [x0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 64 747: JIT compiled Perfolizer.Horology.TimeInterval:ToNanoseconds() [Tier0, IL size=17, code size=64] ; Assembly listing for method Perfolizer.Horology.TimeInterval:op_Division(Perfolizer.Horology.TimeInterval,Perfolizer.Horology.TimeInterval):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str d0, [fp, #0x28] str d1, [fp, #0x20] G_M000_IG02: add x0, fp, #40 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 fmov d16, #1.0000 fmul d16, d0, d16 str d16, [fp, #0x18] add x0, fp, #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0x18] fdiv d0, d16, d0 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 92 748: JIT compiled Perfolizer.Horology.TimeInterval:op_Division(Perfolizer.Horology.TimeInterval,Perfolizer.Horology.TimeInterval) [Tier0, IL size=26, code size=92] ; Assembly listing for method Perfolizer.Horology.ClockExtensions:GetResolution(Perfolizer.Horology.IClock):Perfolizer.Horology.TimeInterval ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str d0, [fp, #0x10] add x0, fp, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 76 749: JIT compiled Perfolizer.Horology.ClockExtensions:GetResolution(Perfolizer.Horology.IClock) [Tier0, IL size=15, code size=76] ; Assembly listing for method Perfolizer.Horology.WindowsClock:get_Frequency():Perfolizer.Horology.Frequency:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: str xzr, [fp, #0x10] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] scvtf d0, x0 add x0, fp, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 72 750: JIT compiled Perfolizer.Horology.WindowsClock:get_Frequency() [Tier0, IL size=12, code size=72] ; Assembly listing for method Perfolizer.Horology.Frequency:.ctor(double):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str d0, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr d16, [fp, #0x10] str d16, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 36 751: JIT compiled Perfolizer.Horology.Frequency:.ctor(double) [Tier0, IL size=8, code size=36] ; Assembly listing for method Perfolizer.Horology.Frequency:ToResolution():Perfolizer.Horology.TimeInterval:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x1, [x0] str x1, [fp, #0x20] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x18] ldr d1, [fp, #0x18] ldr d0, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 752: JIT compiled Perfolizer.Horology.Frequency:ToResolution() [Tier0, IL size=17, code size=96] ; Assembly listing for method Perfolizer.Horology.Frequency:get_Hertz():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 753: JIT compiled Perfolizer.Horology.Frequency:get_Hertz() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Horology.TimeInterval:op_Division(Perfolizer.Horology.TimeInterval,double):Perfolizer.Horology.TimeInterval ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str d0, [fp, #0x28] str d1, [fp, #0x20] G_M000_IG02: str xzr, [fp, #0x18] add x0, fp, #40 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0x20] fdiv d0, d0, d16 str d0, [fp, #0x10] ldr d0, [fp, #0x10] add x0, fp, #24 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 754: JIT compiled Perfolizer.Horology.TimeInterval:op_Division(Perfolizer.Horology.TimeInterval,double) [Tier0, IL size=15, code size=96] ; Assembly listing for method BenchmarkDotNet.Engines.EngineActualStage:.ctor(BenchmarkDotNet.Engines.IEngine):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] str x0, [fp, #0x98] str x1, [fp, #0x90] G_M000_IG02: ldr x0, [fp, #0x98] ldr x1, [fp, #0x90] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x38] ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x11, [fp, #0x98] str x0, [x11, #0x24] ldr x0, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x88] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x80] ldr x0, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x30] ldr x2, [fp, #0x30] ldr x1, [fp, #0x80] ldr x0, [fp, #0x88] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr x0, [fp, #0x98] str d0, [x0, #0x10] ldr x0, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 str x0, [fp, #0x70] str x1, [fp, #0x78] ldr x0, [fp, #0x98] ldp x1, x2, [fp, #0x70] stp x1, x2, [x0, #0x30] ldr x0, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x68] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x60] ldr x0, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x20] ldr x2, [fp, #0x20] ldr x1, [fp, #0x60] ldr x0, [fp, #0x68] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr x11, [fp, #0x98] str w0, [x11, #0x18] ldr x0, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x50] ldr x0, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x18] ldr x2, [fp, #0x18] ldr x1, [fp, #0x50] ldr x0, [fp, #0x58] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr x11, [fp, #0x98] str w0, [x11, #0x1C] ldr x0, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x48] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x40] ldr x0, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x10] ldr x2, [fp, #0x10] ldr x1, [fp, #0x40] ldr x0, [fp, #0x48] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr x1, [fp, #0x98] str w0, [x1, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0xA0 ret lr ; Total bytes of code 728 755: JIT compiled BenchmarkDotNet.Engines.EngineActualStage:.ctor(BenchmarkDotNet.Engines.IEngine) [Tier0, IL size=164, code size=728] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValueAsNullable[int](BenchmarkDotNet.Characteristics.Characteristic`1[int]):System.Nullable`1[int]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x28] str x0, [fp, #0x38] str x1, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x38] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG04 str xzr, [fp, #0x28] ldr x0, [fp, #0x28] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG04: str xzr, [fp, #0x20] ldr x0, [fp, #0x38] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x1C] ldr w1, [fp, #0x1C] add x0, fp, #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x20] G_M000_IG05: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 144 756: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValueAsNullable[int](BenchmarkDotNet.Characteristics.Characteristic`1[int]) [Tier0, IL size=32, code size=144] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],BenchmarkDotNet.Characteristics.IResolver):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x10] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] ldr x3, [fp, #0x10] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 757: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],BenchmarkDotNet.Characteristics.IResolver) [Tier0, IL size=9, code size=84] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver:Resolve[int](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[int]):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str x0, [fp, #0x78] str x1, [fp, #0x70] str x2, [fp, #0x68] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x50] ldr x0, [fp, #0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x50] str x14, [fp, #0x60] ldr x14, [fp, #0x60] add x14, x14, #8 ldr x15, [fp, #0x68] bl CORINFO_HELP_ASSIGN_REF ldr x1, [fp, #0x60] ldr x1, [x1, #0x08] ldr x0, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG04 ldr x0, [fp, #0x60] ldr x0, [x0, #0x08] ldr x1, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] ldr x0, [fp, #0x78] ldr x0, [x0, #0x08] str x0, [fp, #0x40] ldr x0, [fp, #0x48] ldr x1, [fp, #0x60] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x2, [fp, #0x48] ldr x1, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x58] ldr x0, [fp, #0x58] cbz x0, G_M000_IG06 ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x30] ldr x2, [fp, #0x60] ldr x2, [x2, #0x08] ldr x0, [fp, #0x58] ldr x1, [fp, #0x70] ldr x3, [fp, #0x30] blr x3 G_M000_IG05: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] ldr x0, [fp, #0x60] ldr x0, [x0, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x38] bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 540 758: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver:Resolve[int](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[int]) [Tier0, IL size=108, code size=540] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[int]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 759: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[int]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[int]:b__0(BenchmarkDotNet.Characteristics.IResolver):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x1, [fp, #0x18] ldr x1, [x1, #0x08] ldr x0, [fp, #0x10] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 760: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass4_0`1[int]:b__0(BenchmarkDotNet.Characteristics.IResolver) [Tier0, IL size=13, code size=56] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver:Resolve[int](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[int]):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x0, [fp, #0x58] str x1, [fp, #0x50] str x2, [fp, #0x48] G_M000_IG02: ldr x0, [fp, #0x50] ldr x1, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG04 ldr x0, [fp, #0x48] ldr x1, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG04: ldr x0, [fp, #0x58] ldr x0, [x0, #0x08] add x2, fp, #64 ldr x1, [fp, #0x48] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 cbz w0, G_M000_IG06 ldr x0, [fp, #0x40] ldr x0, [x0, #0x08] ldr x1, [fp, #0x50] ldr x2, [fp, #0x40] ldr x2, [x2, #0x18] blr x2 str x0, [fp, #0x30] ldr x1, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [x0] G_M000_IG05: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x38] bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 384 761: JIT compiled BenchmarkDotNet.Characteristics.Resolver:Resolve[int](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[int]) [Tier0, IL size=68, code size=384] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass2_0`1[int]:b__0(BenchmarkDotNet.Characteristics.CharacteristicObject):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x08] ldr x1, [fp, #0x20] ldr x2, [fp, #0x10] ldr x2, [x2, #0x18] blr x2 ldr x1, [fp, #0x18] str w0, [x1, #0x08] ldr x0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 100 762: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass2_0`1[int]:b__0(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=18, code size=100] ; Assembly listing for method BenchmarkDotNet.Engines.EngineResolver:<.ctor>b__7_11(BenchmarkDotNet.Characteristics.CharacteristicObject):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] str xzr, [x9, #0x40] str x0, [fp, #0x68] str x1, [fp, #0x60] G_M000_IG02: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr x0, [fp, #0x60] ldr x2, [fp, #0x68] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 cbz w0, G_M000_IG04 mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG04: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr x0, [fp, #0x60] ldr x2, [fp, #0x68] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 str w0, [fp, #0x5C] ldr w0, [fp, #0x5C] cbz w0, G_M000_IG06 ldr w0, [fp, #0x5C] sub w0, w0, #1 cmp w0, #1 bls G_M000_IG08 G_M000_IG05: b G_M000_IG10 G_M000_IG06: mov w0, #1 G_M000_IG07: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG08: mov w0, wzr G_M000_IG09: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG10: add x0, fp, #48 mov w1, #21 mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x20] ldr x1, [fp, #0x20] add x0, fp, #48 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #48 ldr w1, [fp, #0x5C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x28] bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 404 763: JIT compiled BenchmarkDotNet.Engines.EngineResolver:<.ctor>b__7_11(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=87, code size=404] ; Assembly listing for method BenchmarkDotNet.Engines.EngineFactory:Jit(BenchmarkDotNet.Engines.Engine,int,int,int):Perfolizer.Horology.TimeInterval ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! mov fp, sp movi v16.16b, #0 add x9, fp, #88 add x10, fp, #232 stp q16, q16, [x9, #-0x40] stp q16, q16, [x9, #-0x20] bfm x9, xzr, #0, #5 dczva x9 add x9, x9, #64 cmp x9, x10 blo pc-16 (-4 instructions) stp q16, q16, [x10] stp q16, q16, [x10, #0x20] str x0, [fp, #0xD1FFAB1E] str w1, [fp, #0xD1FFAB1E] str w2, [fp, #0xD1FFAB1E] str w3, [fp, #0xD1FFAB1E] G_M000_IG02: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] ldr x1, [fp, #0x28] ldr x1, [x1, #0x18] blr x1 stp xzr, xzr, [fp, #0xE8] stp xzr, xzr, [fp, #0xF8] ldr w4, [fp, #0xD1FFAB1E] sxtw x4, w4 add x0, fp, #232 ldr w5, [fp, #0xD1FFAB1E] ldr w3, [fp, #0xD1FFAB1E] mov w1, wzr mov w2, wzr movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x80] ldp x0, x1, [fp, #0xE8] stp x0, x1, [fp, #0x88] ldp x0, x1, [fp, #0xF8] stp x0, x1, [fp, #0x98] ldr x0, [fp, #0x80] add x1, fp, #136 add x8, fp, #200 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: add x0, fp, #104 ldp q16, q17, [x0, #0x60] stp q16, q17, [fp, #0x60] G_M000_IG04: add x0, fp, #96 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x0, [x0, #0x08] ldr x1, [fp, #0x20] ldr x1, [x1, #0x18] blr x1 stp xzr, xzr, [fp, #0xA8] stp xzr, xzr, [fp, #0xB8] ldr w4, [fp, #0xD1FFAB1E] sxtw x4, w4 add x0, fp, #168 ldr w5, [fp, #0xD1FFAB1E] ldr w3, [fp, #0xD1FFAB1E] mov w1, #1 mov w2, wzr movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x38] G_M000_IG05: add x0, fp, #104 ldp q16, q17, [x0, #0x40] stp q16, q17, [fp, #0x40] G_M000_IG06: ldr x0, [fp, #0x38] add x1, fp, #64 add x8, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] ldr x1, [fp, #0x18] ldr x1, [x1, #0x18] blr x1 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x30] ldr d0, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG07: ldp fp, lr, [sp], #0xD1FFAB1E ret lr ; Total bytes of code 580 764: JIT compiled BenchmarkDotNet.Engines.EngineFactory:Jit(BenchmarkDotNet.Engines.Engine,int,int,int) [Tier0, IL size=92, code size=580] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_Dummy1Action():System.Action:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 765: JIT compiled BenchmarkDotNet.Engines.Engine:get_Dummy1Action() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Autogenerated.Runnable_0:Dummy1():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] G_M000_IG03: str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] G_M000_IG04: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 1300 766: JIT compiled BenchmarkDotNet.Autogenerated.Runnable_0:Dummy1() [Tier0, IL size=897, code size=1300] ; Assembly listing for method BenchmarkDotNet.Engines.IterationData:.ctor(int,int,int,long,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str w1, [fp, #0x34] str w2, [fp, #0x30] str w3, [fp, #0x2C] str x4, [fp, #0x20] str w5, [fp, #0x1C] G_M000_IG02: ldr x0, [fp, #0x38] ldr w1, [fp, #0x34] str w1, [x0] ldr x0, [fp, #0x38] ldr w1, [fp, #0x30] str w1, [x0, #0x04] ldr x0, [fp, #0x38] ldr w1, [fp, #0x2C] str w1, [x0, #0x08] ldr x0, [fp, #0x38] ldr x1, [fp, #0x20] str x1, [x0, #0x10] ldr x0, [fp, #0x38] ldr w1, [fp, #0x1C] str w1, [x0, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 100 767: JIT compiled BenchmarkDotNet.Engines.IterationData:.ctor(int,int,int,long,int) [Tier0, IL size=38, code size=100] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:RunIteration(BenchmarkDotNet.Engines.IterationData):BenchmarkDotNet.Reports.Measurement:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: sub sp, sp, #0xD1FFAB1E stp fp, lr, [sp, #0xD1FFAB1E] add fp, sp, #0xD1FFAB1E movi v16.16b, #0 sub x9, fp, #0xD1FFAB1E sub x10, fp, #88 stp q16, q16, [x9, #-0x40] stp q16, q16, [x9, #-0x20] bfm x9, xzr, #0, #5 dczva x9 add x9, x9, #64 cmp x9, x10 blo pc-16 (-4 instructions) stp q16, q16, [x10] stp q16, q16, [x10, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movn xip1, #0xD1FFAB1E str x2, [fp, xip1] str x0, [fp, #-0x08] str x1, [fp, #-0x18] str x8, [fp, #-0x10] G_M000_IG02: ldr x0, [fp, #-0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #-0x20] ldr x0, [fp, #-0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #-0x24] ldr x0, [fp, #-0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #-0x20] mul x0, x0, x1 str x0, [fp, #-0x30] ldr x0, [fp, #-0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cmp w0, #0 cset x0, eq str w0, [fp, #-0x34] ldr w0, [fp, #-0x34] cbnz w0, G_M000_IG03 ldr x0, [fp, #-0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #-0xB0] b G_M000_IG04 G_M000_IG03: str wzr, [fp, #-0xB0] G_M000_IG04: ldr w0, [fp, #-0xB0] uxtb w0, w0 str w0, [fp, #-0x38] ldr w0, [fp, #-0x34] cbnz w0, G_M000_IG05 ldr x0, [fp, #-0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #-0xB8] b G_M000_IG06 G_M000_IG05: ldr x0, [fp, #-0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #-0xB8] G_M000_IG06: ldr x0, [fp, #-0xB8] str x0, [fp, #-0x40] ldr w0, [fp, #-0x34] cbnz w0, G_M000_IG07 ldr x0, [fp, #-0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movn xip1, #0xD1FFAB1E str x0, [fp, xip1] movn xip1, #0xD1FFAB1E ldr x0, [fp, xip1] ldr x0, [x0, #0x08] movn xip1, #0xD1FFAB1E ldr x1, [fp, xip1] ldr x1, [x1, #0x18] blr x1 G_M000_IG07: ldr x0, [fp, #-0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbz w0, G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] movn xip1, #0xD1FFAB1E str x0, [fp, xip1] ldr x0, [fp, #-0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movn xip1, #0xD1FFAB1E str w0, [fp, xip1] ldr x0, [fp, #-0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movn xip1, #0xD1FFAB1E str w0, [fp, xip1] movn xip1, #0xD1FFAB1E ldr w2, [fp, xip1] movn xip1, #0xD1FFAB1E ldr w1, [fp, xip1] movn xip1, #0xD1FFAB1E ldr x0, [fp, xip1] ldr x3, [fp, #-0x30] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] ldr wzr, [x0] blr x4 G_M000_IG08: ldr w0, [fp, #-0x38] cbz w0, G_M000_IG13 ldr x0, [fp, #-0x08] ldr x0, [x0, #0xA0] movn xip1, #0xD1FFAB1E str x0, [fp, xip1] movn xip1, #0xD1FFAB1E ldr x0, [fp, xip1] mov w1, #32 movn xip1, #0xD1FFAB1E ldr x2, [fp, xip1] ldr x2, [x2] ldr x2, [x2, #0x40] ldr x2, [x2, #0x28] blr x2 str w0, [fp, #-0xAC] ldr w1, [fp, #-0xAC] mov w1, w1 tst x1, x1 beq G_M000_IG10 add x1, x1, #15 and x1, x1, #-16 G_M000_IG09: stp xzr, xzr, [sp, #-0x10]! subs x1, x1, #16 bne G_M000_IG09 mov x1, sp G_M000_IG10: sub x0, fp, #0xD1FFAB1E ldr w2, [fp, #-0xAC] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG11: ldp x0, x1, [fp, #0xD1FFAB1E] stp x0, x1, [fp, #-0xA8] G_M000_IG12: b G_M000_IG15 G_M000_IG13: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #-0xC8] str x1, [fp, #-0xC0] G_M000_IG14: ldp x0, x1, [fp, #-0xC8] stp x0, x1, [fp, #-0xA8] G_M000_IG15: ldp x0, x1, [fp, #-0xA8] stp x0, x1, [fp, #-0x50] G_M000_IG16: ldr x0, [fp, #-0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #-0xD8] str x1, [fp, #-0xD0] G_M000_IG17: ldp x0, x1, [fp, #-0xD8] stp x0, x1, [fp, #-0x60] G_M000_IG18: ldr x1, [fp, #-0x20] ldr w0, [fp, #-0x24] sxtw x0, w0 cmp x0, #0 beq G_M000_IG28 cmn x0, #1 bne G_M000_IG19 cmp x1, #1 bvs G_M000_IG27 G_M000_IG19: sdiv x1, x1, x0 ldr x0, [fp, #-0x40] ldr x0, [x0, #0x08] ldr x2, [fp, #-0x40] ldr x2, [x2, #0x18] blr x2 sub x0, fp, #96 sub x8, fp, #120 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbz w0, G_M000_IG20 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #-0xF0] ldr x0, [fp, #-0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #-0xF4] ldr x0, [fp, #-0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movn xip1, #0xD1FFAB1E str w0, [fp, xip1] movn xip1, #0xD1FFAB1E ldr w2, [fp, xip1] ldr w1, [fp, #-0xF4] ldr x0, [fp, #-0xF0] ldr x3, [fp, #-0x30] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] ldr wzr, [x0] blr x4 G_M000_IG20: ldr w0, [fp, #-0x34] cbnz w0, G_M000_IG21 ldr x0, [fp, #-0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movn xip1, #0xD1FFAB1E str x0, [fp, xip1] movn xip1, #0xD1FFAB1E ldr x0, [fp, xip1] ldr x0, [x0, #0x08] movn xip1, #0xD1FFAB1E ldr x1, [fp, xip1] ldr x1, [x1, #0x18] blr x1 G_M000_IG21: ldr w0, [fp, #-0x38] cbz w0, G_M000_IG22 ldr x0, [fp, #-0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG22: ldr x0, [fp, #-0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #-0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #-0xDC] ldr x0, [fp, #-0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #-0xE0] ldr x0, [fp, #-0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #-0xE4] sub x0, fp, #120 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movn xip1, #0xD1FFAB1E str d0, [fp, xip1] movn xip1, #0xD1FFAB1E ldr d0, [fp, xip1] sub x0, fp, #152 ldr w2, [fp, #-0xDC] ldr w3, [fp, #-0xE0] ldr w4, [fp, #-0xE4] ldr x5, [fp, #-0x30] mov w1, wzr movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 sub x0, fp, #152 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movn xip1, #0xD1FFAB1E str x0, [fp, xip1] movn xip1, #0xD1FFAB1E ldr x1, [fp, xip1] ldr x0, [fp, #-0x08] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sub x0, fp, #152 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG23 ldr x0, [fp, #-0x08] ldr x0, [x0, #0x80] movn xip1, #0xD1FFAB1E str x0, [fp, xip1] ldp x0, x1, [fp, #-0x98] stp x0, x1, [fp, #0xD1FFAB1E] ldp x0, x1, [fp, #-0x88] stp x0, x1, [fp, #0xD1FFAB1E] movn xip1, #0xD1FFAB1E ldr x0, [fp, xip1] sub x1, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG23: sub x1, fp, #80 ldr x0, [fp, #-0x08] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #-0x10] G_M000_IG24: sub x1, fp, #152 ldp q16, q17, [x1] stp q16, q17, [x0] G_M000_IG25: movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 movn xip1, #0xD1FFAB1E ldr xip1, [fp, xip1] cmp xip0, xip1 beq G_M000_IG26 bl CORINFO_HELP_FAIL_FAST G_M000_IG26: sub sp, fp, #0xD1FFAB1E ldp fp, lr, [sp, #0xD1FFAB1E] add sp, sp, #0xD1FFAB1E ret lr G_M000_IG27: bl CORINFO_HELP_OVERFLOW G_M000_IG28: bl CORINFO_HELP_THROWDIVZERO brk_windows #0 ; Total bytes of code 1768 768: JIT compiled BenchmarkDotNet.Engines.Engine:RunIteration(BenchmarkDotNet.Engines.IterationData) [Tier0, IL size=361, code size=1768] ; Assembly listing for method BenchmarkDotNet.Engines.IterationData:get_InvokeCount():long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 769: JIT compiled BenchmarkDotNet.Engines.IterationData:get_InvokeCount() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.IterationData:get_UnrollFactor():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 770: JIT compiled BenchmarkDotNet.Engines.IterationData:get_UnrollFactor() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_OperationsPerInvoke():long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0xA8] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 771: JIT compiled BenchmarkDotNet.Engines.Engine:get_OperationsPerInvoke() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.IterationData:get_IterationMode():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 772: JIT compiled BenchmarkDotNet.Engines.IterationData:get_IterationMode() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_OverheadAction():System.Action`1[long]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 773: JIT compiled BenchmarkDotNet.Engines.Engine:get_OverheadAction() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:GcCollect():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG04 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 76 774: JIT compiled BenchmarkDotNet.Engines.Engine:GcCollect() [Tier0, IL size=15, code size=76] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_ForceGcCleanups():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldrb w0, [x0, #0xB8] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 775: JIT compiled BenchmarkDotNet.Engines.Engine:get_ForceGcCleanups() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:ForceGcCollect() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 76 776: JIT compiled BenchmarkDotNet.Engines.Engine:ForceGcCollect() [Tier0, IL size=16, code size=76] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 777: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 778: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Text.Ascii:ChangeCase[ushort,ushort,System.Text.Ascii+ToUpperConversion](ulong,ulong,ulong):ulong ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! mov fp, sp str x0, [fp, #0xD1FFAB1E] str x1, [fp, #0xD1FFAB1E] str x2, [fp, #0xD1FFAB1E] G_M000_IG02: str wzr, [fp, #0xD1FFAB1E] str wzr, [fp, #0xD1FFAB1E] mov w0, #0xD1FFAB1E str w0, [fp, #0x20] ldr w0, [fp, #0xD1FFAB1E] cbz w0, G_M000_IG03 ldr w0, [fp, #0xD1FFAB1E] cmp w0, #0 cset x0, eq str w0, [fp, #0x48] b G_M000_IG04 G_M000_IG03: str wzr, [fp, #0x48] G_M000_IG04: ldr w0, [fp, #0x48] uxtb w0, w0 str w0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] cmp w0, #0 cset x0, eq ldr w1, [fp, #0xD1FFAB1E] and w0, w0, w1 str w0, [fp, #0xD1FFAB1E] mov w0, #1 str w0, [fp, #0xD1FFAB1E] mov w0, #1 str w0, [fp, #0xD1FFAB1E] mov w0, #16 mov w1, #2 udiv w0, w0, w1 str w0, [fp, #0xD1FFAB1E] str xzr, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] cbnz w0, G_M000_IG05 G_M000_IG05: ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xD1FFAB1E] mov w1, w1 cmp x0, x1 blo G_M000_IG12 ldr x0, [fp, #0xD1FFAB1E] ldr q0, [x0] str q0, [fp, #0xD1FFAB1E] ldr q0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbnz w0, G_M000_IG12 mov w0, #1 mov w1, #2 lsl w1, w1, #3 sub w1, w1, #1 lsl w0, w0, w1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] cbnz w0, G_M000_IG06 mov w0, #65 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x1C] ldr w1, [fp, #0x1C] ldr w0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x2C] b G_M000_IG07 G_M000_IG06: mov w0, #97 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x18] ldr w1, [fp, #0x18] ldr w0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x2C] G_M000_IG07: ldr w0, [fp, #0x2C] dup v16.8h, w0 str q16, [fp, #0xD1FFAB1E] mov w0, #26 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x14] ldr w1, [fp, #0x14] ldr w0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 dup v16.8h, w0 str q16, [fp, #0xD1FFAB1E] mov w0, #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 dup v0.8h, w0 str q0, [fp, #0xF0] ldr q0, [fp, #0xD1FFAB1E] ldr q1, [fp, #0xD1FFAB1E] sub v0.8h, v0.8h, v1.8h ldr q1, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str q0, [fp, #0xE0] ldr q0, [fp, #0xE0] ldr q16, [fp, #0xF0] and v0.8h, v0.8h, v16.8h ldr q16, [fp, #0xD1FFAB1E] eor v0.8h, v16.8h, v0.8h str q0, [fp, #0xD1FFAB1E] ldr q0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [fp, #0xD1FFAB1E] lsl w0, w0, #1 str w0, [fp, #0xDC] ldr w0, [fp, #0xD1FFAB1E] str w0, [fp, #0x10] ldr w0, [fp, #0x10] ldr w1, [fp, #0xDC] cmp w1, #0 beq G_M000_IG44 udiv w0, w0, w1 ldr w1, [fp, #0xDC] mul w0, w0, w1 ldr w1, [fp, #0x10] sub w0, w1, w0 lsr w0, w0, #1 ldr w1, [fp, #0xD1FFAB1E] sub w0, w1, w0 mov w0, w0 str x0, [fp, #0xD1FFAB1E] G_M000_IG08: ldr w0, [fp, #0x20] sub w0, w0, #1 str w0, [fp, #0x20] ldr w0, [fp, #0x20] cmp w0, #0 bgt G_M000_IG10 G_M000_IG09: add x0, fp, #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG10: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] sub x0, x0, x1 ldr w1, [fp, #0xD1FFAB1E] mov w1, w1 cmp x0, x1 bhs G_M000_IG11 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] cmp x0, x1 beq G_M000_IG42 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xD1FFAB1E] mov w1, w1 sub x0, x0, x1 str x0, [fp, #0xD1FFAB1E] G_M000_IG11: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] lsl x1, x1, #1 ldr q0, [x0, x1] str q0, [fp, #0xD1FFAB1E] ldr q0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbnz w0, G_M000_IG12 ldr q0, [fp, #0xD1FFAB1E] ldr q1, [fp, #0xD1FFAB1E] sub v0.8h, v0.8h, v1.8h ldr q1, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str q0, [fp, #0xE0] ldr q0, [fp, #0xE0] ldr q16, [fp, #0xF0] and v0.8h, v0.8h, v16.8h ldr q16, [fp, #0xD1FFAB1E] eor v0.8h, v16.8h, v0.8h str q0, [fp, #0xD1FFAB1E] ldr q0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xD1FFAB1E] mov w1, w1 add x0, x0, x1 str x0, [fp, #0xD1FFAB1E] b G_M000_IG08 G_M000_IG12: ldr w0, [fp, #0x20] sub w0, w0, #1 str w0, [fp, #0x20] ldr w0, [fp, #0x20] cmp w0, #0 bgt G_M000_IG14 G_M000_IG13: add x0, fp, #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG14: mov w0, #8 mov w1, #2 udiv w0, w0, w1 sxtw x0, w0 ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] sub x1, x1, x2 cmp x0, x1 bhi G_M000_IG24 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] lsl x1, x1, #1 add x0, x0, x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD0] ldr w0, [fp, #0xD1FFAB1E] cbz w0, G_M000_IG17 ldr x0, [fp, #0xD0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG24 ldr w0, [fp, #0xD1FFAB1E] cbnz w0, G_M000_IG15 ldr x0, [fp, #0xD0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x30] b G_M000_IG16 G_M000_IG15: ldr x0, [fp, #0xD0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x30] G_M000_IG16: ldr x0, [fp, #0x30] str x0, [fp, #0xD0] b G_M000_IG20 G_M000_IG17: ldr x0, [fp, #0xD0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG24 ldr w0, [fp, #0xD1FFAB1E] cbnz w0, G_M000_IG18 ldr x0, [fp, #0xD0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x38] b G_M000_IG19 G_M000_IG18: ldr x0, [fp, #0xD0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x38] G_M000_IG19: ldr x0, [fp, #0x38] str x0, [fp, #0xD0] G_M000_IG20: ldr w0, [fp, #0xD1FFAB1E] cbz w0, G_M000_IG21 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] lsl x1, x1, #1 add x0, x0, x1 ldr x1, [fp, #0xD0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG23 G_M000_IG21: ldr x0, [fp, #0xD0] ins v16.d[0], x0 str q16, [fp, #0xC0] ldr w0, [fp, #0xD1FFAB1E] cbz w0, G_M000_IG22 ldr q16, [fp, #0xC0] uxtl v16.8h, v16.8b ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] lsl x1, x1, #1 str q16, [x0, x1] b G_M000_IG23 G_M000_IG22: ldr q16, [fp, #0xC0] str q16, [fp, #0xB0] ldr q16, [fp, #0xB0] xtn v16.8b, v16.8h ldr q17, [fp, #0xB0] xtn2 v16.16b, v17.8h str q16, [fp, #0xA0] ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] lsl x1, x1, #1 add x0, x0, x1 ldr q16, [fp, #0xA0] umov w1, v16.s[0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG23: mov w0, #8 mov w1, #2 udiv w0, w0, w1 sxtw x0, w0 ldr x1, [fp, #0xD1FFAB1E] add x0, x0, x1 str x0, [fp, #0xD1FFAB1E] G_M000_IG24: ldr w0, [fp, #0x20] sub w0, w0, #1 str w0, [fp, #0x20] ldr w0, [fp, #0x20] cmp w0, #0 bgt G_M000_IG26 G_M000_IG25: add x0, fp, #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG26: mov w0, #4 mov w1, #2 udiv w0, w0, w1 sxtw x0, w0 ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] sub x1, x1, x2 cmp x0, x1 bhi G_M000_IG39 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] lsl x1, x1, #1 add x0, x0, x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x9C] ldr w0, [fp, #0xD1FFAB1E] cbz w0, G_M000_IG29 ldr w0, [fp, #0x9C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG39 ldr w0, [fp, #0xD1FFAB1E] cbnz w0, G_M000_IG27 ldr w0, [fp, #0x9C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x40] b G_M000_IG28 G_M000_IG27: ldr w0, [fp, #0x9C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x40] G_M000_IG28: ldr w0, [fp, #0x40] str w0, [fp, #0x9C] b G_M000_IG32 G_M000_IG29: ldr w0, [fp, #0x9C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG39 ldr w0, [fp, #0xD1FFAB1E] cbnz w0, G_M000_IG30 ldr w0, [fp, #0x9C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x44] b G_M000_IG31 G_M000_IG30: ldr w0, [fp, #0x9C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x44] G_M000_IG31: ldr w0, [fp, #0x44] str w0, [fp, #0x9C] G_M000_IG32: ldr w0, [fp, #0xD1FFAB1E] cbz w0, G_M000_IG33 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] lsl x1, x1, #1 add x0, x0, x1 ldr w1, [fp, #0x9C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG35 G_M000_IG33: ldr w0, [fp, #0x9C] ins v16.s[0], w0 str q16, [fp, #0x80] ldr w0, [fp, #0xD1FFAB1E] cbz w0, G_M000_IG34 ldr q16, [fp, #0x80] uxtl v16.8h, v16.8b str q16, [fp, #0x70] ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] lsl x1, x1, #1 add x0, x0, x1 ldr q16, [fp, #0x70] umov x1, v16.d[0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG35 G_M000_IG34: ldr q16, [fp, #0x80] str q16, [fp, #0x60] ldr q16, [fp, #0x60] xtn v16.8b, v16.8h ldr q17, [fp, #0x60] xtn2 v16.16b, v17.8h str q16, [fp, #0x50] ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] lsl x1, x1, #1 add x0, x0, x1 ldr q16, [fp, #0x50] umov w1, v16.h[0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG35: mov w0, #4 mov w1, #2 udiv w0, w0, w1 sxtw x0, w0 ldr x1, [fp, #0xD1FFAB1E] add x0, x0, x1 str x0, [fp, #0xD1FFAB1E] b G_M000_IG39 G_M000_IG36: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] lsl x1, x1, #1 ldrh w0, [x0, x1] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x4C] ldr w0, [fp, #0x4C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG42 ldr w0, [fp, #0xD1FFAB1E] cbz w0, G_M000_IG37 ldr w0, [fp, #0x4C] mov w1, #97 mov w2, #122 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 cbz w0, G_M000_IG38 ldr w0, [fp, #0x4C] sub w0, w0, #32 str w0, [fp, #0x4C] b G_M000_IG38 G_M000_IG37: ldr w0, [fp, #0x4C] mov w1, #65 mov w2, #90 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 cbz w0, G_M000_IG38 ldr w0, [fp, #0x4C] add w0, w0, #32 str w0, [fp, #0x4C] G_M000_IG38: ldr w0, [fp, #0x4C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0xD1FFAB1E] ldr x2, [fp, #0xD1FFAB1E] lsl x2, x2, #1 strh w0, [x1, x2] ldr x0, [fp, #0xD1FFAB1E] mov w1, #1 mov w1, w1 add x0, x0, x1 str x0, [fp, #0xD1FFAB1E] G_M000_IG39: ldr w0, [fp, #0x20] sub w0, w0, #1 str w0, [fp, #0x20] ldr w0, [fp, #0x20] cmp w0, #0 bgt G_M000_IG41 G_M000_IG40: add x0, fp, #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG41: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] cmp x0, x1 blo G_M000_IG36 G_M000_IG42: ldr x0, [fp, #0xD1FFAB1E] G_M000_IG43: ldp fp, lr, [sp], #0xD1FFAB1E ret lr G_M000_IG44: bl CORINFO_HELP_THROWDIVZERO brk_windows #0 ; Total bytes of code 2340 779: JIT compiled System.Text.Ascii:ChangeCase[ushort,ushort,System.Text.Ascii+ToUpperConversion](ulong,ulong,ulong) [Tier0, IL size=1153, code size=2340] ; Assembly listing for method System.Text.Ascii:VectorContainsAnyNonAsciiData[ushort](System.Runtime.Intrinsics.Vector128`1[ushort]):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str q0, [fp, #0x10] G_M000_IG02: b G_M000_IG03 G_M000_IG03: ldr q0, [fp, #0x10] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG05 mov w0, #1 G_M000_IG04: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG05: mov w0, wzr G_M000_IG06: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 68 780: JIT compiled System.Text.Ascii:VectorContainsAnyNonAsciiData[ushort](System.Runtime.Intrinsics.Vector128`1[ushort]) [Tier0, IL size=51, code size=68] ; Assembly listing for method System.Text.Ascii:VectorContainsNonAsciiChar(System.Runtime.Intrinsics.Vector128`1[ushort]):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x38] str xzr, [fp, #0x30] str q0, [fp, #0x40] G_M000_IG02: b G_M000_IG03 G_M000_IG03: ldr q16, [fp, #0x40] ldr q17, [fp, #0x40] umaxp v16.8h, v16.8h, v17.8h str q16, [fp, #0x20] ldr q16, [fp, #0x20] umov x0, v16.d[0] and x0, x0, #0xD1FFAB1E cmp x0, #0 cset x0, ne G_M000_IG04: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 68 781: JIT compiled System.Text.Ascii:VectorContainsNonAsciiChar(System.Runtime.Intrinsics.Vector128`1[ushort]) [Tier0, IL size=73, code size=68] ; Assembly listing for method System.UInt16:CreateTruncating[int](int):ushort ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str w0, [fp, #0x1C] G_M000_IG02: b G_M000_IG03 G_M000_IG03: add x1, fp, #16 ldr w0, [fp, #0x1C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG04 add x1, fp, #16 ldr w0, [fp, #0x1C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG04: ldr w0, [fp, #0x10] uxth w0, w0 G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 116 782: JIT compiled System.UInt16:CreateTruncating[int](int) [Tier0, IL size=74, code size=116] ; Assembly listing for method System.UInt16:TryConvertFromTruncating[int](int,byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str w0, [fp, #0x5C] str x1, [fp, #0x50] G_M000_IG02: b G_M000_IG03 G_M000_IG03: b G_M000_IG04 G_M000_IG04: b G_M000_IG05 G_M000_IG05: b G_M000_IG06 G_M000_IG06: b G_M000_IG07 G_M000_IG07: b G_M000_IG08 G_M000_IG08: b G_M000_IG09 G_M000_IG09: ldr x0, [fp, #0x50] strh wzr, [x0] mov w0, wzr G_M000_IG10: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 64 783: JIT compiled System.UInt16:TryConvertFromTruncating[int](int,byref) [Tier0, IL size=373, code size=64] ; Assembly listing for method System.Int32:System.Numerics.INumberBase.TryConvertToTruncating[ushort](int,byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str w0, [fp, #0x5C] str x1, [fp, #0x50] G_M000_IG02: b G_M000_IG03 G_M000_IG03: b G_M000_IG04 G_M000_IG04: b G_M000_IG05 G_M000_IG05: ldr w0, [fp, #0x5C] uxth w0, w0 str w0, [fp, #0x34] ldr x0, [fp, #0x50] ldr w1, [fp, #0x34] strh w1, [x0] mov w0, #1 G_M000_IG06: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 64 784: JIT compiled System.Int32:System.Numerics.INumberBase.TryConvertToTruncating[ushort](int,byref) [Tier0, IL size=416, code size=64] ; Assembly listing for method System.UInt16:CreateTruncating[ushort](ushort):ushort ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str w0, [fp, #0x1C] G_M000_IG02: b G_M000_IG03 G_M000_IG03: ldr w0, [fp, #0x1C] uxth w0, w0 add x1, fp, #16 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG04 ldr w0, [fp, #0x1C] uxth w0, w0 add x1, fp, #16 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG04: ldr w0, [fp, #0x10] uxth w0, w0 G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 124 785: JIT compiled System.UInt16:CreateTruncating[ushort](ushort) [Tier0, IL size=74, code size=124] ; Assembly listing for method System.UInt16:TryConvertFromTruncating[ushort](ushort,byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str w0, [fp, #0x5C] str x1, [fp, #0x50] G_M000_IG02: b G_M000_IG03 G_M000_IG03: ldr w0, [fp, #0x5C] uxth w0, w0 str w0, [fp, #0x48] ldr x0, [fp, #0x50] ldr w1, [fp, #0x48] strh w1, [x0] mov w0, #1 G_M000_IG04: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 56 786: JIT compiled System.UInt16:TryConvertFromTruncating[ushort](ushort,byref) [Tier0, IL size=373, code size=56] ; Assembly listing for method System.Text.Ascii:SignedLessThan[ushort](System.Runtime.Intrinsics.Vector128`1[ushort],System.Runtime.Intrinsics.Vector128`1[ushort]):System.Runtime.Intrinsics.Vector128`1[ushort] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str q0, [fp, #0x20] str q1, [fp, #0x10] G_M000_IG02: b G_M000_IG03 G_M000_IG03: ldr q0, [fp, #0x20] ldr q16, [fp, #0x10] cmgt v0.8h, v16.8h, v0.8h G_M000_IG04: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 40 787: JIT compiled System.Text.Ascii:SignedLessThan[ushort](System.Runtime.Intrinsics.Vector128`1[ushort],System.Runtime.Intrinsics.Vector128`1[ushort]) [Tier0, IL size=70, code size=40] ; Assembly listing for method System.Text.Ascii:ChangeWidthAndWriteTo[ushort,ushort](System.Runtime.Intrinsics.Vector128`1[ushort],ulong,ulong) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x28] str x0, [fp, #0x38] str x1, [fp, #0x30] str q0, [fp, #0x40] G_M000_IG02: ldr x0, [fp, #0x38] ldr x1, [fp, #0x30] lsl x1, x1, #1 ldr q16, [fp, #0x40] str q16, [x0, x1] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 52 788: JIT compiled System.Text.Ascii:ChangeWidthAndWriteTo[ushort,ushort](System.Runtime.Intrinsics.Vector128`1[ushort],ulong,ulong) [Tier0, IL size=149, code size=52] ; Assembly listing for method (dynamicClass):InvokeStub_EventSourceAttribute.set_Name(System.Object,System.Object,ulong):System.Object ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp mov x0, x1 G_M000_IG02: ldr x1, [x2] ldr x1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 mov x0, xzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 56 789: JIT compiled (dynamicClass):InvokeStub_EventSourceAttribute.set_Name(System.Object,System.Object,ulong) [FullOpts, IL size=25, code size=56] ; Assembly listing for method System.Number:TryParseBinaryIntegerStyle[ushort](System.ReadOnlySpan`1[ushort],int,System.Globalization.NumberFormatInfo,byref):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! mov fp, sp add x9, fp, #56 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] stp q16, q16, [x9, #0x80] str xzr, [x9, #0xA0] str x0, [fp, #0xD1FFAB1E] str x1, [fp, #0xD1FFAB1E] str w2, [fp, #0xD1FFAB1E] str x3, [fp, #0xD1FFAB1E] str x4, [fp, #0xF8] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x30] add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG52 str wzr, [fp, #0xF4] ldr w0, [fp, #0xD1FFAB1E] cmp w0, #0 bls G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldrh w0, [x0] str w0, [fp, #0xF0] ldr w0, [fp, #0xD1FFAB1E] and w0, w0, #1 cbz w0, G_M000_IG06 ldr w0, [fp, #0xF0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG06 G_M000_IG03: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG05 G_M000_IG04: add x0, fp, #48 mov w1, #37 bl CORINFO_HELP_PATCHPOINT G_M000_IG05: ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG52 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] ldr w0, [fp, #0xF0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG03 G_M000_IG06: str wzr, [fp, #0xEC] ldr w0, [fp, #0xD1FFAB1E] and w0, w0, #4 cbz w0, G_M000_IG17 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbz w0, G_M000_IG08 ldr w0, [fp, #0xF0] cmp w0, #45 bne G_M000_IG07 mov w0, #1 str w0, [fp, #0xEC] ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG52 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] b G_M000_IG17 G_M000_IG07: ldr w0, [fp, #0xF0] cmp w0, #43 bne G_M000_IG17 ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG52 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] b G_M000_IG17 G_M000_IG08: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbz w0, G_M000_IG09 ldr w0, [fp, #0xF0] cmp w0, #45 bne G_M000_IG09 mov w0, #1 str w0, [fp, #0xEC] ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG52 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] b G_M000_IG17 G_M000_IG09: add x0, fp, #0xD1FFAB1E ldr w1, [fp, #0xF4] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x78] str x1, [fp, #0x80] G_M000_IG10: ldp x0, x1, [fp, #0x78] stp x0, x1, [fp, #0xD1FFAB1E] G_M000_IG11: str wzr, [fp, #0xF4] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0xD8] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0xD0] ldr x0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG14 G_M000_IG12: ldp x0, x1, [fp, #0xD1FFAB1E] stp x0, x1, [fp, #0x38] G_M000_IG13: ldr x0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x48] str x1, [fp, #0x50] ldr x0, [fp, #0x38] ldr x1, [fp, #0x40] ldr x2, [fp, #0x48] ldr x3, [fp, #0x50] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 cbz w0, G_M000_IG14 ldr x0, [fp, #0xD8] ldr w0, [x0, #0x08] ldr w1, [fp, #0xF4] add w0, w0, w1 str w0, [fp, #0xF4] ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG52 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] b G_M000_IG17 G_M000_IG14: ldr x0, [fp, #0xD0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG17 G_M000_IG15: ldp x0, x1, [fp, #0xD1FFAB1E] stp x0, x1, [fp, #0x58] G_M000_IG16: ldr x0, [fp, #0xD0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x68] str x1, [fp, #0x70] ldr x0, [fp, #0x58] ldr x1, [fp, #0x60] ldr x2, [fp, #0x68] ldr x3, [fp, #0x70] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 cbz w0, G_M000_IG17 mov w0, #1 str w0, [fp, #0xEC] ldr x0, [fp, #0xD0] ldr w0, [x0, #0x08] ldr w1, [fp, #0xF4] add w0, w0, w1 str w0, [fp, #0xF4] ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG52 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] G_M000_IG17: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cmp w0, #0 cset x0, eq ldr w1, [fp, #0xEC] and w0, w0, w1 str w0, [fp, #0xE8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0xE4] ldr w0, [fp, #0xF0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG52 ldr w0, [fp, #0xF0] cmp w0, #48 bne G_M000_IG21 G_M000_IG18: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG20 G_M000_IG19: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG20: ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG43 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] ldr w0, [fp, #0xF0] cmp w0, #48 beq G_M000_IG18 ldr w0, [fp, #0xF0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG21 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbnz w0, G_M000_IG56 str wzr, [fp, #0xE8] b G_M000_IG56 G_M000_IG21: ldr w0, [fp, #0xF0] sub w0, w0, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xE4] ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] str wzr, [fp, #0xCC] b G_M000_IG24 G_M000_IG22: ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 blo G_M000_IG23 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbnz w0, G_M000_IG43 b G_M000_IG40 G_M000_IG23: ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] ldr w0, [fp, #0xF0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG56 ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] ldr w0, [fp, #0xE4] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xE4] ldr w0, [fp, #0xF0] sub w0, w0, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x2C] ldr w1, [fp, #0x2C] ldr w0, [fp, #0xE4] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0xE4] ldr w0, [fp, #0xCC] add w0, w0, #1 str w0, [fp, #0xCC] G_M000_IG24: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG26 G_M000_IG25: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG26: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 sub w0, w0, #2 ldr w1, [fp, #0xCC] cmp w0, w1 bgt G_M000_IG22 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 blo G_M000_IG27 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbnz w0, G_M000_IG43 b G_M000_IG40 G_M000_IG27: ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] ldr w0, [fp, #0xF0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG56 ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbnz w0, G_M000_IG31 ldr w0, [fp, #0xE8] str w0, [fp, #0x94] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0x28] ldr w1, [fp, #0x28] ldr w0, [fp, #0xE4] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG29 ldr w0, [fp, #0x94] str w0, [fp, #0x88] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0x24] ldr w1, [fp, #0x24] ldr w0, [fp, #0xE4] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG28 ldr w0, [fp, #0x88] str w0, [fp, #0x90] ldr w0, [fp, #0xF0] cmp w0, #53 cset x0, gt str w0, [fp, #0x8C] b G_M000_IG30 G_M000_IG28: ldr w0, [fp, #0x88] str w0, [fp, #0x90] str wzr, [fp, #0x8C] b G_M000_IG30 G_M000_IG29: ldr w0, [fp, #0x94] str w0, [fp, #0x90] mov w0, #1 str w0, [fp, #0x8C] G_M000_IG30: ldr w0, [fp, #0x90] ldr w1, [fp, #0x8C] orr w0, w0, w1 uxtb w0, w0 str w0, [fp, #0xE8] b G_M000_IG32 G_M000_IG31: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0x20] ldr w1, [fp, #0x20] ldr w0, [fp, #0xE4] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0xE8] G_M000_IG32: ldr w0, [fp, #0xE4] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xE4] ldr w0, [fp, #0xF0] sub w0, w0, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x1C] ldr w1, [fp, #0x1C] ldr w0, [fp, #0xE4] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0xE4] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG35 ldr w0, [fp, #0xE8] str w0, [fp, #0xB0] ldr w0, [fp, #0xE4] str w0, [fp, #0xAC] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0xA8] ldr w0, [fp, #0xEC] cbnz w0, G_M000_IG33 ldr w0, [fp, #0xB0] str w0, [fp, #0xA4] ldr w0, [fp, #0xAC] str w0, [fp, #0xA0] ldr w0, [fp, #0xA8] str w0, [fp, #0x9C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0x98] b G_M000_IG34 G_M000_IG33: ldr w0, [fp, #0xB0] str w0, [fp, #0xA4] ldr w0, [fp, #0xAC] str w0, [fp, #0xA0] ldr w0, [fp, #0xA8] str w0, [fp, #0x9C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0x98] G_M000_IG34: ldr w0, [fp, #0x9C] ldr w1, [fp, #0x98] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x18] ldr w1, [fp, #0x18] ldr w0, [fp, #0xA0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w1, [fp, #0xA4] orr w0, w0, w1 uxtb w0, w0 str w0, [fp, #0xE8] G_M000_IG35: ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG40 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] b G_M000_IG37 G_M000_IG36: mov w0, #1 str w0, [fp, #0xE8] ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG55 ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] str w0, [fp, #0xF0] G_M000_IG37: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG39 G_M000_IG38: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG39: ldr w0, [fp, #0xF0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG36 b G_M000_IG56 G_M000_IG40: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG42 G_M000_IG41: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG42: ldr w0, [fp, #0xE8] cbnz w0, G_M000_IG55 G_M000_IG43: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbnz w0, G_M000_IG44 ldr x0, [fp, #0xF8] ldr w1, [fp, #0xE4] strh w1, [x0] b G_M000_IG47 G_M000_IG44: ldr x0, [fp, #0xF8] str x0, [fp, #0xC0] ldr w0, [fp, #0xEC] cbnz w0, G_M000_IG45 ldr x0, [fp, #0xC0] str x0, [fp, #0xB8] ldr w0, [fp, #0xE4] str w0, [fp, #0xB4] b G_M000_IG46 G_M000_IG45: ldr x0, [fp, #0xC0] str x0, [fp, #0xB8] ldr w0, [fp, #0xE4] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xB4] G_M000_IG46: ldr x0, [fp, #0xB8] ldr w1, [fp, #0xB4] strh w1, [x0] G_M000_IG47: str wzr, [fp, #0xE0] G_M000_IG48: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG50 G_M000_IG49: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG50: ldr w0, [fp, #0xE0] G_M000_IG51: ldp fp, lr, [sp], #0xD1FFAB1E ret lr G_M000_IG52: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG54 G_M000_IG53: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG54: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr x1, [fp, #0xF8] strh w0, [x1] mov w0, #1 str w0, [fp, #0xE0] b G_M000_IG48 G_M000_IG55: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr x1, [fp, #0xF8] strh w0, [x1] mov w0, #2 str w0, [fp, #0xE0] b G_M000_IG48 G_M000_IG56: ldr w0, [fp, #0xF0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG62 ldr w0, [fp, #0xD1FFAB1E] and w0, w0, #2 cbz w0, G_M000_IG52 ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] b G_M000_IG58 G_M000_IG57: ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG63 ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xF4] mov w1, w1 lsl x1, x1, #1 ldrh w0, [x0, x1] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG61 ldr w0, [fp, #0xF4] add w0, w0, #1 str w0, [fp, #0xF4] G_M000_IG58: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG60 G_M000_IG59: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG60: ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 blt G_M000_IG57 G_M000_IG61: ldr w0, [fp, #0xF4] ldr w1, [fp, #0xD1FFAB1E] cmp w0, w1 bhs G_M000_IG40 G_M000_IG62: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr w2, [fp, #0xF4] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 cbnz w0, G_M000_IG40 b G_M000_IG52 G_M000_IG63: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 3308 790: JIT compiled System.Number:TryParseBinaryIntegerStyle[ushort](System.ReadOnlySpan`1[ushort],int,System.Globalization.NumberFormatInfo,byref) [Tier0, IL size=1142, code size=3308] ; Assembly listing for method System.UInt16:System.IBinaryIntegerParseAndFormatInfo.get_IsSigned():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 791: JIT compiled System.UInt16:System.IBinaryIntegerParseAndFormatInfo.get_IsSigned() [Tier0, IL size=2, code size=20] ; Assembly listing for method System.UInt16:System.IBinaryIntegerParseAndFormatInfo.get_MaxDigitCount():int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, #5 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 792: JIT compiled System.UInt16:System.IBinaryIntegerParseAndFormatInfo.get_MaxDigitCount() [Tier0, IL size=2, code size=20] ; Assembly listing for method (dynamicClass):InvokeStub_EventAttribute.set_Level(System.Object,System.Object,ulong):System.Object ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp mov x0, x1 G_M000_IG02: ldr x1, [x2] ldr w1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 mov x0, xzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 56 793: JIT compiled (dynamicClass):InvokeStub_EventAttribute.set_Level(System.Object,System.Object,ulong) [FullOpts, IL size=25, code size=56] ; Assembly listing for method (dynamicClass):InvokeStub_EventAttribute.set_Task(System.Object,System.Object,ulong):System.Object ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp mov x0, x1 G_M000_IG02: ldr x1, [x2] ldr w1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 mov x0, xzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 56 794: JIT compiled (dynamicClass):InvokeStub_EventAttribute.set_Task(System.Object,System.Object,ulong) [FullOpts, IL size=25, code size=56] ; Assembly listing for method (dynamicClass):InvokeStub_EventAttribute.set_Opcode(System.Object,System.Object,ulong):System.Object ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp mov x0, x1 G_M000_IG02: ldr x1, [x2] ldr w1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 mov x0, xzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 56 795: JIT compiled (dynamicClass):InvokeStub_EventAttribute.set_Opcode(System.Object,System.Object,ulong) [FullOpts, IL size=25, code size=56] ; Assembly listing for method BenchmarkDotNet.Engines.IterationData:get_IterationStage():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x04] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 796: JIT compiled BenchmarkDotNet.Engines.IterationData:get_IterationStage() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:IterationStart(int,int,long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str wzr, [fp, #0x34] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str w1, [fp, #0x44] str w2, [fp, #0x40] str x3, [fp, #0x38] G_M000_IG02: ldr w0, [fp, #0x40] str w0, [fp, #0x34] ldr w0, [fp, #0x34] cmp w0, #3 bhi G_M000_IG03 ldr w0, [fp, #0x34] mov w0, w0 adr x1, [@RWD00] ldr w1, [x1, x0, LSL #2] adr x2, [G_M000_IG02] add x1, x1, x2 br x1 G_M000_IG03: b G_M000_IG11 G_M000_IG04: ldr w0, [fp, #0x44] cbnz w0, G_M000_IG05 ldr x0, [fp, #0x48] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG12 G_M000_IG05: ldr w0, [fp, #0x44] cmp w0, #1 bne G_M000_IG11 ldr x0, [fp, #0x48] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG12 G_M000_IG06: ldr w0, [fp, #0x44] cmp w0, #1 bne G_M000_IG11 ldr x0, [fp, #0x48] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG12 G_M000_IG07: ldr w0, [fp, #0x44] cbnz w0, G_M000_IG08 ldr x0, [fp, #0x48] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG12 G_M000_IG08: ldr w0, [fp, #0x44] cmp w0, #1 bne G_M000_IG11 ldr x0, [fp, #0x48] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG12 G_M000_IG09: ldr w0, [fp, #0x44] cbnz w0, G_M000_IG10 ldr x0, [fp, #0x48] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG12 G_M000_IG10: ldr w0, [fp, #0x44] cmp w0, #1 bne G_M000_IG11 ldr x0, [fp, #0x48] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG12 G_M000_IG11: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr w1, [fp, #0x40] str w1, [x0, #0x08] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x2, [fp, #0x28] ldr x0, [fp, #0x20] mov x3, xzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x20] bl CORINFO_HELP_THROW G_M000_IG12: ldp fp, lr, [sp], #0x50 ret lr RWD00 dd G_M000_IG04 - G_M000_IG02 dd G_M000_IG06 - G_M000_IG02 dd G_M000_IG07 - G_M000_IG02 dd G_M000_IG09 - G_M000_IG02 ; Total bytes of code 516 797: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:IterationStart(int,int,long) [Tier0, IL size=125, code size=516] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:OverheadJittingStart(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x2, [fp, #0x10] mov w1, #3 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 798: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:OverheadJittingStart(long) [Tier0, IL size=9, code size=56] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_Clock():Perfolizer.Horology.IClock:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x78] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 799: JIT compiled BenchmarkDotNet.Engines.Engine:get_Clock() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Horology.ClockExtensions:Start(Perfolizer.Horology.IClock):Perfolizer.Horology.StartedClock ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: stp xzr, xzr, [fp, #0x18] ldr x0, [fp, #0x28] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x10] ldr x2, [fp, #0x10] add x0, fp, #24 ldr x1, [fp, #0x28] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] ldr x1, [fp, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 800: JIT compiled Perfolizer.Horology.ClockExtensions:Start(Perfolizer.Horology.IClock) [Tier0, IL size=13, code size=96] ; Assembly listing for method Perfolizer.Horology.WindowsClock:GetTimestamp():long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: add x0, fp, #16 bl Perfolizer.Horology.WindowsClock:QueryPerformanceCounter(byref):bool ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 36 801: JIT compiled Perfolizer.Horology.WindowsClock:GetTimestamp() [Tier0, IL size=10, code size=36] ; Assembly listing for method Perfolizer.Horology.StartedClock:.ctor(Perfolizer.Horology.IClock,long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x14, [fp, #0x28] ldr x15, [fp, #0x20] bl CORINFO_HELP_CHECKED_ASSIGN_REF ldr x0, [fp, #0x28] ldr x1, [fp, #0x18] str x1, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 52 802: JIT compiled Perfolizer.Horology.StartedClock:.ctor(Perfolizer.Horology.IClock,long) [Tier0, IL size=15, code size=52] ; Assembly listing for method BenchmarkDotNet.Autogenerated.Runnable_0:OverheadActionNoUnroll(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x18] str x21, [sp, #0x28] mov fp, sp mov x20, x0 mov x19, x1 G_M000_IG02: mov x21, xzr cmp x19, #0 ble G_M000_IG04 G_M000_IG03: ldr x1, [x20, #0x28] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 add x21, x21, #1 cmp x21, x19 blt G_M000_IG03 G_M000_IG04: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 80 803: JIT compiled BenchmarkDotNet.Autogenerated.Runnable_0:OverheadActionNoUnroll(long) [Tier1, IL size=26, code size=80] ; Assembly listing for method BenchmarkDotNet.Autogenerated.Runnable_0:__Overhead():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 20 804: JIT compiled BenchmarkDotNet.Autogenerated.Runnable_0:__Overhead() [Tier0, IL size=1, code size=20] ; Assembly listing for method Perfolizer.Horology.StartedClock:GetElapsed():Perfolizer.Horology.ClockSpan:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str x0, [fp, #0x48] str x8, [fp, #0x40] G_M000_IG02: ldr x0, [fp, #0x48] ldr x0, [x0, #0x08] str x0, [fp, #0x38] ldr x0, [fp, #0x48] ldr x0, [x0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x30] stp xzr, xzr, [fp, #0x18] str xzr, [fp, #0x28] ldr x0, [fp, #0x48] ldr x0, [x0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str d0, [fp, #0x10] add x0, fp, #24 ldr x1, [fp, #0x38] ldr x2, [fp, #0x30] ldr d0, [fp, #0x10] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x40] ldp x1, x2, [fp, #0x18] stp x1, x2, [x0] ldr x1, [fp, #0x28] str x1, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 164 805: JIT compiled Perfolizer.Horology.StartedClock:GetElapsed() [Tier0, IL size=34, code size=164] ; Assembly listing for method Perfolizer.Horology.ClockSpan:.ctor(long,long,Perfolizer.Horology.Frequency):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] str d0, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] str x1, [x0] ldr x0, [fp, #0x28] ldr x1, [fp, #0x18] str x1, [x0, #0x08] ldr x0, [fp, #0x28] ldr x1, [fp, #0x10] str x1, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 68 806: JIT compiled Perfolizer.Horology.ClockSpan:.ctor(long,long,Perfolizer.Horology.Frequency) [Tier0, IL size=22, code size=68] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:IterationStop(int,int,long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str wzr, [fp, #0x34] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str w1, [fp, #0x44] str w2, [fp, #0x40] str x3, [fp, #0x38] G_M000_IG02: ldr w0, [fp, #0x40] str w0, [fp, #0x34] ldr w0, [fp, #0x34] cmp w0, #3 bhi G_M000_IG03 ldr w0, [fp, #0x34] mov w0, w0 adr x1, [@RWD00] ldr w1, [x1, x0, LSL #2] adr x2, [G_M000_IG02] add x1, x1, x2 br x1 G_M000_IG03: b G_M000_IG11 G_M000_IG04: ldr w0, [fp, #0x44] cbnz w0, G_M000_IG05 ldr x0, [fp, #0x48] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG12 G_M000_IG05: ldr w0, [fp, #0x44] cmp w0, #1 bne G_M000_IG11 ldr x0, [fp, #0x48] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG12 G_M000_IG06: ldr w0, [fp, #0x44] cmp w0, #1 bne G_M000_IG11 ldr x0, [fp, #0x48] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG12 G_M000_IG07: ldr w0, [fp, #0x44] cbnz w0, G_M000_IG08 ldr x0, [fp, #0x48] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG12 G_M000_IG08: ldr w0, [fp, #0x44] cmp w0, #1 bne G_M000_IG11 ldr x0, [fp, #0x48] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG12 G_M000_IG09: ldr w0, [fp, #0x44] cbnz w0, G_M000_IG10 ldr x0, [fp, #0x48] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG12 G_M000_IG10: ldr w0, [fp, #0x44] cmp w0, #1 bne G_M000_IG11 ldr x0, [fp, #0x48] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG12 G_M000_IG11: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr w1, [fp, #0x40] str w1, [x0, #0x08] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x2, [fp, #0x28] ldr x0, [fp, #0x20] mov x3, xzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x20] bl CORINFO_HELP_THROW G_M000_IG12: ldp fp, lr, [sp], #0x50 ret lr RWD00 dd G_M000_IG04 - G_M000_IG02 dd G_M000_IG06 - G_M000_IG02 dd G_M000_IG07 - G_M000_IG02 dd G_M000_IG09 - G_M000_IG02 ; Total bytes of code 516 807: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:IterationStop(int,int,long) [Tier0, IL size=125, code size=516] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:OverheadJittingStop(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x2, [fp, #0x10] mov w1, #4 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 808: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:OverheadJittingStop(long) [Tier0, IL size=9, code size=56] ; Assembly listing for method BenchmarkDotNet.Engines.IterationData:get_Index():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 809: JIT compiled BenchmarkDotNet.Engines.IterationData:get_Index() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Horology.ClockSpan:GetNanoseconds():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x10] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 scvtf d0, x0 ldr d16, [fp, #0x10] fmul d0, d0, d16 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 100 810: JIT compiled Perfolizer.Horology.ClockSpan:GetNanoseconds() [Tier0, IL size=19, code size=100] ; Assembly listing for method Perfolizer.Horology.ClockSpan:GetSeconds():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x1, [fp, #0x18] ldr x1, [x1, #0x08] ldr x0, [fp, #0x18] ldr x0, [x0] sub x1, x1, x0 mov x0, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 scvtf d0, x0 fmov d16, #1.0000 fmul d0, d0, d16 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x10] ldr x0, [fp, #0x18] ldr d1, [x0, #0x10] ldr d0, [fp, #0x10] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 132 811: JIT compiled Perfolizer.Horology.ClockSpan:GetSeconds() [Tier0, IL size=48, code size=132] ; Assembly listing for method Perfolizer.Horology.Frequency:op_Implicit(double):Perfolizer.Horology.Frequency ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str d0, [fp, #0x18] G_M000_IG02: str xzr, [fp, #0x10] add x0, fp, #16 ldr d0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 812: JIT compiled Perfolizer.Horology.Frequency:op_Implicit(double) [Tier0, IL size=7, code size=56] ; Assembly listing for method Perfolizer.Horology.Frequency:op_Division(Perfolizer.Horology.Frequency,Perfolizer.Horology.Frequency):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str d0, [fp, #0x28] str d1, [fp, #0x20] G_M000_IG02: add x0, fp, #40 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 fmov d16, #1.0000 fmul d16, d0, d16 str d16, [fp, #0x18] add x0, fp, #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0x18] fdiv d0, d16, d0 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 92 813: JIT compiled Perfolizer.Horology.Frequency:op_Division(Perfolizer.Horology.Frequency,Perfolizer.Horology.Frequency) [Tier0, IL size=26, code size=92] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:.ctor(int,int,int,int,long,double):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str w1, [fp, #0x34] str w2, [fp, #0x30] str w3, [fp, #0x2C] str w4, [fp, #0x28] str x5, [fp, #0x20] str d0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x38] ldr x1, [fp, #0x20] str x1, [x0, #0x10] ldr x0, [fp, #0x38] ldr d16, [fp, #0x18] str d16, [x0, #0x18] ldr x0, [fp, #0x38] ldr w1, [fp, #0x34] str w1, [x0, #0x08] ldr x0, [fp, #0x38] ldr w1, [fp, #0x30] str w1, [x0] ldr x0, [fp, #0x38] ldr w1, [fp, #0x2C] str w1, [x0, #0x04] ldr x0, [fp, #0x38] ldr w1, [fp, #0x28] str w1, [x0, #0x0C] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 116 814: JIT compiled BenchmarkDotNet.Reports.Measurement:.ctor(int,int,int,int,long,double) [Tier0, IL size=46, code size=116] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:ToString():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xE0]! mov fp, sp movi v16.16b, #0 sub x9, fp, #8 mov x10, #128 stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40]! subs x10, x10, #64 bge pc-16 (-4 instructions) str x0, [fp, #0xD8] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xA8] ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xD4] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xA0] ldr x0, [fp, #0xA0] ldr w1, [fp, #0xD4] str w1, [x0, #0x08] ldr x0, [fp, #0xA0] str x0, [fp, #0x80] ldr x0, [fp, #0x80] ldr x1, [fp, #0x80] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x08] blr x1 str x0, [fp, #0x98] ldr x0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xD0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x90] ldr x0, [fp, #0x90] ldr w1, [fp, #0xD0] str w1, [x0, #0x08] ldr x0, [fp, #0x90] str x0, [fp, #0x78] ldr x0, [fp, #0x78] ldr x1, [fp, #0x78] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x08] blr x1 str x0, [fp, #0x70] ldr x1, [fp, #0x70] ldr x0, [fp, #0x98] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x68] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #217 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] str w0, [fp, #0x64] ldr x0, [fp, #0x68] ldr w1, [fp, #0x64] mov w2, #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 str x0, [fp, #0x58] ldr x1, [fp, #0x58] ldr x0, [fp, #0xA8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xA8] mov w1, #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xC8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #217 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x50] ldr x1, [fp, #0x50] add x0, fp, #200 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x48] ldr x0, [fp, #0x48] mov w1, #2 mov w2, #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 str x0, [fp, #0x40] ldr x1, [fp, #0x40] ldr x0, [fp, #0xA8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xC0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #217 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x38] ldr x1, [fp, #0x38] add x0, fp, #192 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x30] ldr x1, [fp, #0x30] ldr x0, [fp, #0xA8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] G_M000_IG03: blr x2 ldr x0, [fp, #0xA8] mov w1, #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0xB8] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #217 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] str x2, [fp, #0x28] ldr x2, [fp, #0x28] add x0, fp, #184 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x88] ldr x0, [fp, #0xA8] ldr x1, [fp, #0x88] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xA8] mov w1, #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xD8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0xB0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #217 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x20] ldr x1, [fp, #0x20] add x0, fp, #176 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 mov x3, xzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0xA8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xA8] ldr x1, [fp, #0xA8] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x08] blr x1 G_M000_IG04: ldp fp, lr, [sp], #0xE0 ret lr ; Total bytes of code 1404 815: JIT compiled BenchmarkDotNet.Reports.Measurement:ToString() [Tier0, IL size=304, code size=1404] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:get_IterationMode():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 816: JIT compiled BenchmarkDotNet.Reports.Measurement:get_IterationMode() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:get_IterationStage():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x04] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 817: JIT compiled BenchmarkDotNet.Reports.Measurement:get_IterationStage() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str xzr, [x9, #0x30] G_M000_IG02: movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 ldr x15, [x14] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0x48] movz x2, #48 movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x2, [fp, #0x48] ldr x1, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str w0, [fp, #0x3C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x30] movz x2, #72 movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x2, [fp, #0x30] ldr x1, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr w1, [fp, #0x3C] add w0, w0, w1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 str w0, [x1] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 448 818: JIT compiled BenchmarkDotNet.Reports.Measurement:.cctor() [Tier0, IL size=89, code size=448] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement+<>c:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 819: JIT compiled BenchmarkDotNet.Reports.Measurement+<>c:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement+<>c:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 820: JIT compiled BenchmarkDotNet.Reports.Measurement+<>c:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Linq.Enumerable:Max[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,int]):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] str x2, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x30] ldr x0, [x0, #0x10] ldr x0, [x0, #0x10] str x0, [fp, #0x18] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x18] G_M000_IG05: ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG06: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 124 821: JIT compiled System.Linq.Enumerable:Max[System.__Canon](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,int]) [Tier0, IL size=8, code size=124] ; Assembly listing for method System.Linq.Enumerable:MaxInteger[System.__Canon,int](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,int]):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! mov fp, sp str xzr, [fp, #0x68] str xzr, [fp, #0x20] str xzr, [fp, #0x18] add x3, sp, #160 str x3, [fp, #0x98] str x0, [fp, #0x90] str x0, [fp, #0x88] str x1, [fp, #0x80] str x2, [fp, #0x78] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x28] ldr x0, [fp, #0x80] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x78] cbnz x0, G_M000_IG04 mov w0, #15 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldr x0, [fp, #0x88] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] cbz x0, G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x88] ldr x0, [x0, #0x10] ldr x0, [x0, #0x18] str x0, [fp, #0x58] b G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x58] G_M000_IG07: ldr x0, [fp, #0x58] str x0, [fp, #0x50] ldr x0, [fp, #0x80] ldr x11, [fp, #0x50] ldr x1, [fp, #0x50] ldr x1, [x1] blr x1 str x0, [fp, #0x68] G_M000_IG08: ldr x0, [fp, #0x68] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG09 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG09: ldr x0, [fp, #0x88] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] cbz x0, G_M000_IG11 G_M000_IG10: ldr x0, [fp, #0x88] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] str x0, [fp, #0x48] b G_M000_IG12 G_M000_IG11: ldr x0, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x48] G_M000_IG12: ldr x0, [fp, #0x48] str x0, [fp, #0x40] ldr x0, [fp, #0x68] ldr x11, [fp, #0x40] ldr x1, [fp, #0x40] ldr x1, [x1] blr x1 str x0, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0x78] ldr x0, [x0, #0x08] ldr x2, [fp, #0x78] ldr x2, [x2, #0x18] blr x2 str w0, [fp, #0x74] b G_M000_IG17 G_M000_IG13: ldr x0, [fp, #0x88] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] cbz x0, G_M000_IG15 G_M000_IG14: ldr x0, [fp, #0x88] ldr x0, [x0, #0x10] ldr x0, [x0, #0x20] str x0, [fp, #0x38] b G_M000_IG16 G_M000_IG15: ldr x0, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_METHOD str x0, [fp, #0x38] G_M000_IG16: ldr x0, [fp, #0x38] str x0, [fp, #0x30] ldr x0, [fp, #0x68] ldr x11, [fp, #0x30] ldr x1, [fp, #0x30] ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x78] ldr x0, [x0, #0x08] ldr x2, [fp, #0x78] ldr x2, [x2, #0x18] blr x2 str w0, [fp, #0x64] ldr w0, [fp, #0x64] ldr w1, [fp, #0x74] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG17 ldr w0, [fp, #0x64] str w0, [fp, #0x74] G_M000_IG17: ldr w0, [fp, #0x28] sub w0, w0, #1 str w0, [fp, #0x28] ldr w0, [fp, #0x28] cmp w0, #0 bgt G_M000_IG19 G_M000_IG18: add x0, fp, #40 mov w1, #85 bl CORINFO_HELP_PATCHPOINT G_M000_IG19: ldr x0, [fp, #0x68] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG13 b G_M000_IG20 G_M000_IG20: ldr x0, [fp, #0x98] bl G_M000_IG24 G_M000_IG21: nop G_M000_IG22: ldr w0, [fp, #0x74] G_M000_IG23: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG24: stp fp, lr, [sp, #-0x20]! add x3, fp, #160 str x3, [sp, #0x18] G_M000_IG25: ldr x0, [fp, #0x68] cbz x0, G_M000_IG26 ldr x0, [fp, #0x68] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG26: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 684 822: JIT compiled System.Linq.Enumerable:MaxInteger[System.__Canon,int](System.Collections.Generic.IEnumerable`1[System.__Canon],System.Func`2[System.__Canon,int]) [Tier0, IL size=107, code size=684] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement+<>c:<.cctor>b__31_0(System.String):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x10] ldr w0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 32 823: JIT compiled BenchmarkDotNet.Reports.Measurement+<>c:<.cctor>b__31_0(System.String) [Tier0, IL size=7, code size=32] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement+<>c:<.cctor>b__31_1(System.String):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x10] ldr w0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 32 824: JIT compiled BenchmarkDotNet.Reports.Measurement+<>c:<.cctor>b__31_1(System.String) [Tier0, IL size=7, code size=32] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:get_IterationIndex():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x0C] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 825: JIT compiled BenchmarkDotNet.Reports.Measurement:get_IterationIndex() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:get_Operations():long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 826: JIT compiled BenchmarkDotNet.Reports.Measurement:get_Operations() [Tier0, IL size=7, code size=28] ; Assembly listing for method System.Number:UInt64ToDecChars[ushort](ulong,ulong):ulong ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str x0, [fp, #0x48] str x1, [fp, #0x40] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x18] ldr x0, [fp, #0x40] cmp x0, #10 blo G_M000_IG08 b G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x48] mov w1, #2 sxtw x1, w1 lsl x1, x1, #1 sub x0, x0, x1 str x0, [fp, #0x48] ldr x0, [fp, #0x40] mov x1, #100 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x20] str x1, [fp, #0x28] ldr x0, [fp, #0x20] str x0, [fp, #0x40] ldr x0, [fp, #0x28] str x0, [fp, #0x38] ldr w0, [fp, #0x38] ldr x1, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG04: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG06 G_M000_IG05: add x0, fp, #24 mov w1, #52 bl CORINFO_HELP_PATCHPOINT G_M000_IG06: ldr x0, [fp, #0x40] cmp x0, #100 bhs G_M000_IG03 ldr x0, [fp, #0x40] cmp x0, #10 blo G_M000_IG08 ldr x0, [fp, #0x48] mov w1, #2 sxtw x1, w1 lsl x1, x1, #1 sub x0, x0, x1 str x0, [fp, #0x48] ldr w0, [fp, #0x40] ldr x1, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x48] G_M000_IG07: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG08: ldr x0, [fp, #0x48] mov w1, #2 sxtw x1, w1 sub x0, x0, x1 str x0, [fp, #0x30] ldr x0, [fp, #0x30] str x0, [fp, #0x48] ldr x0, [fp, #0x40] add x0, x0, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x30] strh w0, [x1] ldr x0, [fp, #0x48] G_M000_IG09: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 344 827: JIT compiled System.Number:UInt64ToDecChars[ushort](ulong,ulong) [Tier0, IL size=121, code size=344] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:get_Nanoseconds():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 828: JIT compiled BenchmarkDotNet.Reports.Measurement:get_Nanoseconds() [Tier0, IL size=7, code size=28] ; Assembly listing for method System.Number:NumberToStringFormat[ushort](byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 12 inlinees with PGO data; 61 single block inlinees; 35 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! stp x19, x20, [sp, #0xC0] stp x21, x22, [sp, #0xD0] stp x23, x24, [sp, #0xE0] stp x25, x26, [sp, #0xF0] stp x27, x28, [sp, #0xD1FFAB1E] mov fp, sp str xzr, [fp, #0x68] str xzr, [fp, #0x40] movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 str x5, [fp, #0xB8] str x2, [fp, #0x98] str x3, [fp, #0xA0] mov x19, x0 mov x21, x1 mov x20, x4 G_M000_IG02: mov w22, wzr ldr x23, [x21, #0x10] ldr x0, [fp, #0x98] ldr w24, [fp, #0xA0] mov w1, w24 ldrb w2, [x23] cbz w2, G_M000_IG05 G_M000_IG03: ldrb w2, [x21, #0x08] cbnz w2, G_M000_IG04 mov w2, wzr b G_M000_IG06 align [0 bytes for IG08] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG04: mov w2, #1 b G_M000_IG06 G_M000_IG05: mov w2, #2 G_M000_IG06: movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov w25, w0 G_M000_IG07: mov w26, wzr movn w27, #0 movn w28, #0xD1FFAB1E LSL #16 str wzr, [fp, #0x94] mov w4, wzr movn w5, #0 mov w6, wzr mov w7, wzr mov w0, w25 ldr x8, [fp, #0x98] str x8, [fp, #0x68] b G_M000_IG31 G_M000_IG08: cmp w1, #69 bhi G_M000_IG13 sub w10, w1, #34 cmp w10, #5 bhi G_M000_IG10 mov w0, w10 adr x2, [@RWD00] ldr w2, [x2, x0, LSL #2] adr x10, [G_M000_IG02] add x2, x2, x10 br x2 G_M000_IG09: mov w0, w9 b G_M000_IG31 G_M000_IG10: sub w11, w1, #44 cmp w11, #4 bhi G_M000_IG12 mov w1, w11 adr x0, [@RWD24] ldr w0, [x0, x1, LSL #2] adr x2, [G_M000_IG02] add x0, x0, x2 br x0 G_M000_IG11: mov w0, w9 b G_M000_IG31 G_M000_IG12: cmp w1, #69 beq G_M000_IG25 mov w0, w9 b G_M000_IG31 G_M000_IG13: cmp w1, #92 beq G_M000_IG24 cmp w1, #101 beq G_M000_IG25 mov w0, #0xD1FFAB1E cmp w1, w0 mov w0, w9 bne G_M000_IG31 add w7, w7, #3 b G_M000_IG31 G_M000_IG14: add w26, w26, #1 mov w0, w9 b G_M000_IG31 G_M000_IG15: movn w3, #0xD1FFAB1E LSL #16 cmp w28, w3 bne G_M000_IG16 mov w28, w26 G_M000_IG16: add w26, w26, #1 mov w2, w26 str w2, [fp, #0x94] mov w0, w9 b G_M000_IG31 G_M000_IG17: mov w0, w9 tbz w27, #31, G_M000_IG31 mov w27, w26 b G_M000_IG31 G_M000_IG18: cmp w26, #0 ccmp w27, #0, z, gt mov w0, w9 bge G_M000_IG31 tbnz w5, #31, G_M000_IG20 cmp w5, w26 bne G_M000_IG19 add w22, w22, #1 b G_M000_IG31 G_M000_IG19: mov w6, #1 str w6, [fp, #0x88] ldr w6, [fp, #0x88] G_M000_IG20: mov w5, w26 mov w22, #1 b G_M000_IG31 G_M000_IG21: add w7, w7, #2 mov w0, w9 b G_M000_IG31 G_M000_IG22: cmp w9, w24 mov w0, w9 bge G_M000_IG31 ldrh w2, [x8, w0, SXTW #2] cbz w2, G_M000_IG31 add w0, w0, #1 str w0, [fp, #0x80] cmp w2, w1 ldr w9, [fp, #0x80] bne G_M000_IG22 G_M000_IG23: mov w0, w9 b G_M000_IG31 G_M000_IG24: cmp w9, w24 mov w0, w9 bge G_M000_IG31 ldrh w1, [x8, w0, SXTW #2] cbz w1, G_M000_IG31 add w0, w0, #1 b G_M000_IG31 G_M000_IG25: cmp w9, w24 bge G_M000_IG26 ldrh w1, [x8, w9, SXTW #2] cmp w1, #48 beq G_M000_IG29 G_M000_IG26: add w1, w9, #1 cmp w1, w24 mov w0, w9 bge G_M000_IG31 ldrh w1, [x8, w0, SXTW #2] cmp w1, #43 beq G_M000_IG27 cmp w1, #45 bne G_M000_IG31 G_M000_IG27: add w1, w0, #1 ldrh w1, [x8, w1, SXTW #2] cmp w1, #48 bne G_M000_IG31 G_M000_IG28: mov w9, w0 G_M000_IG29: add w9, w9, #1 cmp w9, w24 bge G_M000_IG30 ldrh w4, [x8, w9, SXTW #2] cmp w4, #48 beq G_M000_IG29 G_M000_IG30: mov w4, #1 mov w0, w9 G_M000_IG31: cmp w0, w24 bge G_M000_IG33 G_M000_IG32: add w1, w0, #1 mov w9, w1 ldrh w10, [x8, w0, SXTW #2] mov w1, w10 cbz w1, G_M000_IG33 cmp w1, #59 bne G_M000_IG08 G_M000_IG33: str xzr, [fp, #0x68] tbz w27, #31, G_M000_IG35 G_M000_IG34: mov w27, w26 G_M000_IG35: tbnz w5, #31, G_M000_IG38 G_M000_IG36: cmp w5, w27 bne G_M000_IG37 mov w0, #3 msub w7, w22, w0, w7 b G_M000_IG38 G_M000_IG37: mov w6, #1 str w6, [fp, #0x88] ldr w6, [fp, #0x88] G_M000_IG38: ldrb w0, [x23] cbz w0, G_M000_IG43 G_M000_IG39: add x0, x21, #4 ldr w1, [x0] add w1, w1, w7 str w1, [x0] str w4, [fp, #0x8C] cbnz w4, G_M000_IG41 G_M000_IG40: ldr w0, [x21, #0x04] add w0, w0, w26 sub w1, w0, w27 str w6, [fp, #0x88] b G_M000_IG42 G_M000_IG41: mov w1, w26 str w6, [fp, #0x88] G_M000_IG42: mov x0, x21 mov w2, wzr movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 ldrb w0, [x23] cbnz w0, G_M000_IG45 ldp x0, x1, [fp, #0x98] mov w2, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov w2, w0 cmp w2, w25 beq G_M000_IG45 mov w25, w2 b G_M000_IG07 G_M000_IG43: ldrb w2, [x21, #0x0A] cmp w2, #3 beq G_M000_IG44 strb wzr, [x21, #0x08] G_M000_IG44: str wzr, [x21, #0x04] stp w6, w4, [fp, #0x88] G_M000_IG45: sub w1, w27, w28 cmp w28, w27 csel w28, w1, wzr, lt ldr w3, [fp, #0x94] sub w1, w27, w3 cmp w3, w27 csel w3, w1, wzr, gt mov w22, w3 ldr w4, [fp, #0x8C] cbz w4, G_M000_IG47 G_M000_IG46: mov w2, w27 mov w3, wzr b G_M000_IG48 G_M000_IG47: ldr w3, [x21, #0x04] cmp w3, w27 csel w2, w3, w27, gt sub w3, w3, w27 G_M000_IG48: str w25, [fp, #0x80] add x7, fp, #168 str x7, [fp, #0x18] mov w8, #4 movn w9, #0 ldr w6, [fp, #0x88] cbz w6, G_M000_IG52 G_M000_IG49: ldr x1, [x20, #0x38] ldr w1, [x1, #0x08] cmp w1, #0 ble G_M000_IG51 ldr x10, [x20, #0x08] str x10, [fp, #0x28] str wzr, [fp, #0x64] mov w13, wzr ldr w14, [x10, #0x08] str w14, [fp, #0x5C] cbz w14, G_M000_IG50 ldr w13, [x10, #0x10] ldr x10, [fp, #0x28] G_M000_IG50: str w13, [fp, #0x60] mov w12, w13 str w2, [fp, #0x90] mov w1, w2 tbnz w3, #31, G_M000_IG53 mov w0, wzr b G_M000_IG54 G_M000_IG51: str w2, [fp, #0x90] b G_M000_IG60 G_M000_IG52: str w2, [fp, #0x90] b G_M000_IG60 G_M000_IG53: str w3, [fp, #0x84] mov w0, w3 ldr w3, [fp, #0x84] G_M000_IG54: add w1, w1, w0 cmp w28, w1 csel w15, w28, w1, gt str w15, [fp, #0x54] cmp w15, w12 ble G_M000_IG60 G_M000_IG55: str w12, [fp, #0x58] cbz w12, G_M000_IG60 add w9, w9, #1 str w9, [fp, #0x78] cmp w9, w8 blt G_M000_IG57 G_M000_IG56: str w3, [fp, #0x84] str w8, [fp, #0x34] lsl w1, w8, #1 sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC mov x3, x0 str x3, [fp, #0x20] add x0, x3, #16 ldr w2, [x3, #0x08] ldr w4, [fp, #0x34] cmp w4, w2 bhi G_M000_IG167 mov w2, w4 lsl x2, x2, #2 ldr x1, [fp, #0x18] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x1, [fp, #0x20] add x2, x1, #16 ldr w4, [x1, #0x08] mov x3, x2 str x3, [fp, #0x18] mov w8, w4 ldr w3, [fp, #0x84] ldr x10, [fp, #0x28] G_M000_IG57: ldr w9, [fp, #0x78] str w8, [fp, #0x34] cmp w9, w8 bhs G_M000_IG168 ldr x7, [fp, #0x18] str w9, [fp, #0x78] ldr w13, [fp, #0x60] str w13, [x7, w9, UXTW #2] ldr w14, [fp, #0x5C] sub w1, w14, #1 ldr w11, [fp, #0x64] cmp w11, w1 bge G_M000_IG59 G_M000_IG58: add w11, w11, #1 ldr w12, [x10, #0x08] cmp w11, w12 bhs G_M000_IG168 add x1, x10, #16 ldr w12, [x1, w11, UXTW #2] mov w1, w12 str w1, [fp, #0x58] G_M000_IG59: ldr w12, [fp, #0x58] add w13, w13, w12 ldr w15, [fp, #0x54] cmp w15, w13 stp w13, w11, [fp, #0x60] ldr w8, [fp, #0x34] ldr w9, [fp, #0x78] bgt G_M000_IG55 G_M000_IG60: ldrb w1, [x21, #0x08] cbz w1, G_M000_IG66 G_M000_IG61: ldr w5, [fp, #0x80] cbnz w5, G_M000_IG66 ldr w1, [x21, #0x04] cbz w1, G_M000_IG66 ldr x1, [x20, #0x28] cbz x1, G_M000_IG64 G_M000_IG62: add x0, x1, #12 ldr w10, [x1, #0x08] G_M000_IG63: mov x1, x0 ldr w0, [x19, #0x08] add x11, x19, #16 ldr x13, [x11] ldr w11, [x11, #0x08] cmp w0, w11 ccmp w10, #1, 0, lo bne G_M000_IG65 ubfiz x10, x0, #1, #32 add x10, x13, x10 ldrh w1, [x1] strh w1, [x10] add w1, w0, #1 str w1, [x19, #0x08] b G_M000_IG66 G_M000_IG64: mov x0, xzr mov w10, wzr b G_M000_IG63 G_M000_IG65: str w9, [fp, #0x78] str w3, [fp, #0x84] str w8, [fp, #0x34] mov w2, w10 mov x0, x19 movz x10, #0xD1FFAB1E movk x10, #0xD1FFAB1E LSL #16 movk x10, #0xD1FFAB1E LSL #32 ldr x10, [x10] blr x10 ldr w3, [fp, #0x84] ldr w8, [fp, #0x34] ldr w9, [fp, #0x78] G_M000_IG66: str wzr, [fp, #0x74] ldr x11, [fp, #0x98] str x11, [fp, #0x40] str x11, [fp, #0x48] mov x0, x23 b G_M000_IG156 G_M000_IG67: cmp w3, #0 ble G_M000_IG68 mov w13, #46 mov w14, #48 cmp w1, #35 ccmp w1, w13, z, ne str w1, [fp, #0x7C] ccmp w1, w14, z, ne beq G_M000_IG82 str w3, [fp, #0x84] b G_M000_IG83 G_M000_IG68: str w1, [fp, #0x7C] str w3, [fp, #0x84] b G_M000_IG83 G_M000_IG69: ldrb w13, [x0] cbnz w13, G_M000_IG70 mov w14, #48 b G_M000_IG71 G_M000_IG70: add x0, x0, #1 str x0, [fp, #0x38] mov w14, w13 ldr x0, [fp, #0x38] G_M000_IG71: uxth w13, w14 ldr w14, [x19, #0x08] add x12, x19, #16 str x12, [fp, #0x10] mov x15, x12 ldr xip0, [x15] ldr w15, [x15, #0x08] cmp w14, w15 bhs G_M000_IG72 cmp w14, w15 bhs G_M000_IG168 strh w13, [xip0, w14, UXTW #2] add w13, w14, #1 str w13, [x19, #0x08] b G_M000_IG73 G_M000_IG72: str w9, [fp, #0x78] str x0, [fp, #0x38] str w8, [fp, #0x34] mov x0, x19 mov w1, w13 movz x13, #0xD1FFAB1E movk x13, #0xD1FFAB1E LSL #16 movk x13, #0xD1FFAB1E LSL #32 ldr x13, [x13] blr x13 ldr x0, [fp, #0x38] ldr w8, [fp, #0x34] ldr w9, [fp, #0x78] G_M000_IG73: ldr w6, [fp, #0x88] cbz w6, G_M000_IG81 ldr w2, [fp, #0x90] cmp w2, #1 ccmp w9, #0, nc, gt blt G_M000_IG77 str w8, [fp, #0x34] cmp w9, w8 bhs G_M000_IG168 ldr x7, [fp, #0x18] str w9, [fp, #0x78] ldr w13, [x7, w9, UXTW #2] add w13, w13, #1 str w2, [fp, #0x90] cmp w13, w2 bne G_M000_IG76 ldr x13, [x20, #0x38] cbz x13, G_M000_IG78 G_M000_IG74: add x14, x13, #12 ldr w15, [x13, #0x08] G_M000_IG75: ldr w13, [x19, #0x08] ldr x12, [fp, #0x10] ldr xip0, [x12] ldr w12, [x12, #0x08] cmp w13, w12 ccmp w15, #1, 0, lo bne G_M000_IG79 cmp w13, w12 bhs G_M000_IG168 ubfiz x12, x13, #1, #32 add x12, xip0, x12 cmp w15, #0 bls G_M000_IG168 ldrh w14, [x14] strh w14, [x12] add w15, w13, #1 str w15, [x19, #0x08] b G_M000_IG80 G_M000_IG76: ldr w8, [fp, #0x34] ldr w9, [fp, #0x78] b G_M000_IG81 G_M000_IG77: str w2, [fp, #0x90] b G_M000_IG81 G_M000_IG78: mov x14, xzr mov w15, wzr b G_M000_IG75 G_M000_IG79: str x0, [fp, #0x38] mov x1, x14 mov w2, w15 mov x0, x19 movz x13, #0xD1FFAB1E movk x13, #0xD1FFAB1E LSL #16 movk x13, #0xD1FFAB1E LSL #32 ldr x13, [x13] blr x13 ldr x0, [fp, #0x38] G_M000_IG80: ldr w9, [fp, #0x78] sub w9, w9, #1 str w9, [fp, #0x78] ldr w8, [fp, #0x34] ldr w9, [fp, #0x78] G_M000_IG81: ldr w2, [fp, #0x90] sub w2, w2, #1 str w2, [fp, #0x90] ldr w3, [fp, #0x84] sub w3, w3, #1 str w3, [fp, #0x84] ldr w3, [fp, #0x84] G_M000_IG82: str w3, [fp, #0x84] cmp w3, #0 bgt G_M000_IG69 G_M000_IG83: ldr w1, [fp, #0x7C] cmp w1, #69 bhi G_M000_IG87 sub w13, w1, #34 cmp w13, #5 bhi G_M000_IG84 mov w13, w13 adr x14, [@RWD44] ldr w14, [x14, x13, LSL #2] adr x12, [G_M000_IG02] add x14, x14, x12 br x14 G_M000_IG84: sub w14, w1, #44 cmp w14, #4 bhi G_M000_IG86 mov w13, w14 adr x14, [@RWD68] ldr w14, [x14, x13, LSL #2] adr x12, [G_M000_IG02] add x14, x14, x12 br x14 G_M000_IG85: ldr w3, [fp, #0x84] ldr x11, [fp, #0x48] b G_M000_IG156 G_M000_IG86: cmp w1, #69 beq G_M000_IG130 b G_M000_IG154 G_M000_IG87: cmp w1, #92 beq G_M000_IG128 cmp w1, #101 beq G_M000_IG130 mov w13, #0xD1FFAB1E cmp w1, w13 bne G_M000_IG154 ldrsb wzr, [x20] b G_M000_IG112 G_M000_IG88: ldr w3, [fp, #0x84] tbz w3, #31, G_M000_IG91 add w3, w3, #1 str w3, [fp, #0x84] ldr w2, [fp, #0x90] cmp w2, w28 ble G_M000_IG89 mov w1, wzr b G_M000_IG90 G_M000_IG89: mov w1, #48 G_M000_IG90: uxth w1, w1 mov w13, w1 b G_M000_IG95 G_M000_IG91: ldrb w13, [x0] cbnz w13, G_M000_IG93 ldr w2, [fp, #0x90] cmp w2, w22 bgt G_M000_IG92 mov w1, wzr b G_M000_IG94 G_M000_IG92: mov w1, #48 b G_M000_IG94 G_M000_IG93: mov x1, x0 add x0, x1, #1 str x0, [fp, #0x38] ldrb w1, [x1] ldr x0, [fp, #0x38] G_M000_IG94: uxth w13, w1 str w3, [fp, #0x84] ldr w2, [fp, #0x90] G_M000_IG95: cbz w13, G_M000_IG104 mov w1, w13 ldr w13, [x19, #0x08] add x14, x19, #16 str x14, [fp, #0x10] mov x12, x14 ldr x15, [x12] ldr w12, [x12, #0x08] cmp w13, w12 bhs G_M000_IG96 cmp w13, w12 bhs G_M000_IG168 strh w1, [x15, w13, UXTW #2] add w1, w13, #1 str w1, [x19, #0x08] b G_M000_IG97 G_M000_IG96: str w9, [fp, #0x78] str w2, [fp, #0x90] str x0, [fp, #0x38] str w8, [fp, #0x34] mov x0, x19 movz x13, #0xD1FFAB1E movk x13, #0xD1FFAB1E LSL #16 movk x13, #0xD1FFAB1E LSL #32 ldr x13, [x13] blr x13 ldr x0, [fp, #0x38] ldr w2, [fp, #0x90] ldr w8, [fp, #0x34] ldr w9, [fp, #0x78] G_M000_IG97: ldr w6, [fp, #0x88] cbz w6, G_M000_IG104 cmp w2, #1 ccmp w9, #0, nc, gt blt G_M000_IG104 str w8, [fp, #0x34] cmp w9, w8 bhs G_M000_IG168 ldr x7, [fp, #0x18] str w9, [fp, #0x78] ldr w1, [x7, w9, UXTW #2] add w1, w1, #1 str w2, [fp, #0x90] cmp w1, w2 bne G_M000_IG100 ldr x1, [x20, #0x38] cbz x1, G_M000_IG101 G_M000_IG98: add x13, x1, #12 ldr w12, [x1, #0x08] G_M000_IG99: mov x1, x13 ldr w13, [x19, #0x08] ldr x14, [fp, #0x10] ldr x15, [x14] ldr w14, [x14, #0x08] cmp w13, w14 ccmp w12, #1, 0, lo bne G_M000_IG102 cmp w13, w14 bhs G_M000_IG168 ubfiz x14, x13, #1, #32 add x14, x15, x14 cmp w12, #0 bls G_M000_IG168 ldrh w1, [x1] strh w1, [x14] add w1, w13, #1 str w1, [x19, #0x08] b G_M000_IG103 G_M000_IG100: ldr w2, [fp, #0x90] ldr w8, [fp, #0x34] ldr w9, [fp, #0x78] b G_M000_IG104 G_M000_IG101: mov x13, xzr mov w12, wzr b G_M000_IG99 G_M000_IG102: str x0, [fp, #0x38] mov w2, w12 mov x0, x19 movz x13, #0xD1FFAB1E movk x13, #0xD1FFAB1E LSL #16 movk x13, #0xD1FFAB1E LSL #32 ldr x13, [x13] blr x13 ldr x0, [fp, #0x38] G_M000_IG103: ldr w9, [fp, #0x78] sub w9, w9, #1 str w9, [fp, #0x78] ldr w2, [fp, #0x90] ldr w8, [fp, #0x34] ldr w9, [fp, #0x78] G_M000_IG104: sub w2, w2, #1 str w2, [fp, #0x90] ldr w3, [fp, #0x84] ldr x11, [fp, #0x48] b G_M000_IG156 G_M000_IG105: ldr w2, [fp, #0x90] cmp w2, #0 cset x1, ne ldr w10, [fp, #0x74] orr w1, w1, w10 str w10, [fp, #0x74] ldr w3, [fp, #0x84] ldr x11, [fp, #0x48] cbnz w1, G_M000_IG156 tbnz w22, #31, G_M000_IG106 cmp w27, w26 bge G_M000_IG156 str x0, [fp, #0x38] ldrb w1, [x0] ldr x0, [fp, #0x38] cbz w1, G_M000_IG156 G_M000_IG106: ldr x1, [x20, #0x30] cbz x1, G_M000_IG109 G_M000_IG107: add x10, x1, #12 ldr w13, [x1, #0x08] G_M000_IG108: mov x1, x10 ldr w10, [x19, #0x08] add x12, x19, #16 mov x14, x12 ldr x12, [x14] ldr w14, [x14, #0x08] cmp w10, w14 ccmp w13, #1, 0, lo bne G_M000_IG110 cmp w10, w14 bhs G_M000_IG168 ubfiz x14, x10, #1, #32 add x14, x12, x14 cmp w13, #0 bls G_M000_IG168 ldrh w1, [x1] strh w1, [x14] add w1, w10, #1 str w1, [x19, #0x08] b G_M000_IG111 G_M000_IG109: mov x10, xzr mov w13, wzr b G_M000_IG108 G_M000_IG110: str w9, [fp, #0x78] str w3, [fp, #0x84] str x0, [fp, #0x38] str w8, [fp, #0x34] mov w2, w13 mov x0, x19 movz x10, #0xD1FFAB1E movk x10, #0xD1FFAB1E LSL #16 movk x10, #0xD1FFAB1E LSL #32 ldr x10, [x10] blr x10 ldr x0, [fp, #0x38] ldr w3, [fp, #0x84] ldr w8, [fp, #0x34] ldr w9, [fp, #0x78] ldr x11, [fp, #0x48] G_M000_IG111: mov w10, #1 str w10, [fp, #0x74] b G_M000_IG156 G_M000_IG112: ldr x1, [x20, #0x88] cbz x1, G_M000_IG115 G_M000_IG113: add x13, x1, #12 ldr w14, [x1, #0x08] G_M000_IG114: mov x1, x13 ldr w13, [x19, #0x08] add x12, x19, #16 ldr x15, [x12] ldr w12, [x12, #0x08] cmp w13, w12 ccmp w14, #1, 0, lo bne G_M000_IG116 cmp w13, w12 bhs G_M000_IG168 ubfiz x12, x13, #1, #32 add x12, x15, x12 cmp w14, #0 bls G_M000_IG168 ldrh w1, [x1] strh w1, [x12] add w1, w13, #1 str w1, [x19, #0x08] ldr w3, [fp, #0x84] ldr x11, [fp, #0x48] b G_M000_IG156 G_M000_IG115: mov x13, xzr mov w14, wzr b G_M000_IG114 G_M000_IG116: str w9, [fp, #0x78] str x0, [fp, #0x38] str w8, [fp, #0x34] mov w2, w14 mov x0, x19 movz x13, #0xD1FFAB1E movk x13, #0xD1FFAB1E LSL #16 movk x13, #0xD1FFAB1E LSL #32 ldr x13, [x13] blr x13 ldr x0, [fp, #0x38] ldr w3, [fp, #0x84] ldr w8, [fp, #0x34] ldr w9, [fp, #0x78] ldr x11, [fp, #0x48] b G_M000_IG156 G_M000_IG117: ldr x1, [x20, #0x80] cbz x1, G_M000_IG120 G_M000_IG118: add x13, x1, #12 ldr w14, [x1, #0x08] G_M000_IG119: mov x1, x13 ldr w13, [x19, #0x08] add x12, x19, #16 ldr x15, [x12] ldr w12, [x12, #0x08] cmp w13, w12 ccmp w14, #1, 0, lo bne G_M000_IG121 cmp w13, w12 bhs G_M000_IG168 ubfiz x12, x13, #1, #32 add x12, x15, x12 cmp w14, #0 bls G_M000_IG168 ldrh w1, [x1] strh w1, [x12] add w1, w13, #1 str w1, [x19, #0x08] ldr w3, [fp, #0x84] ldr x11, [fp, #0x48] b G_M000_IG156 G_M000_IG120: mov x13, xzr mov w14, wzr b G_M000_IG119 G_M000_IG121: str w9, [fp, #0x78] str x0, [fp, #0x38] str w8, [fp, #0x34] mov w2, w14 mov x0, x19 movz x13, #0xD1FFAB1E movk x13, #0xD1FFAB1E LSL #16 movk x13, #0xD1FFAB1E LSL #32 ldr x13, [x13] blr x13 ldr x0, [fp, #0x38] ldr w3, [fp, #0x84] ldr w8, [fp, #0x34] ldr w9, [fp, #0x78] ldr x11, [fp, #0x48] b G_M000_IG156 G_M000_IG122: add w5, w5, #1 str w5, [fp, #0x80] ldr w14, [x19, #0x08] add x12, x19, #16 ldr x15, [x12] ldr w12, [x12, #0x08] cmp w14, w12 bhs G_M000_IG123 cmp w14, w12 bhs G_M000_IG168 strh w13, [x15, w14, UXTW #2] add w13, w14, #1 str w13, [x19, #0x08] ldr w1, [fp, #0x7C] b G_M000_IG124 G_M000_IG123: str w9, [fp, #0x78] str x0, [fp, #0x38] str w8, [fp, #0x34] mov x0, x19 mov w1, w13 movz x13, #0xD1FFAB1E movk x13, #0xD1FFAB1E LSL #16 movk x13, #0xD1FFAB1E LSL #32 ldr x13, [x13] blr x13 ldr x0, [fp, #0x38] ldr w1, [fp, #0x7C] ldr w8, [fp, #0x34] ldr w9, [fp, #0x78] G_M000_IG124: ldr w5, [fp, #0x80] cmp w5, w24 bge G_M000_IG125 ldr x11, [fp, #0x48] ldrh w13, [x11, w5, SXTW #2] cbz w13, G_M000_IG126 str w1, [fp, #0x7C] cmp w13, w1 bne G_M000_IG122 G_M000_IG125: cmp w5, w24 bge G_M000_IG127 G_M000_IG126: ldr x11, [fp, #0x48] ldrh w13, [x11, w5, SXTW #2] str w5, [fp, #0x80] ldr w3, [fp, #0x84] ldr x11, [fp, #0x48] cbz w13, G_M000_IG156 ldr w5, [fp, #0x80] add w5, w5, #1 str w5, [fp, #0x80] b G_M000_IG156 G_M000_IG127: str w5, [fp, #0x80] ldr w3, [fp, #0x84] ldr x11, [fp, #0x48] b G_M000_IG156 G_M000_IG128: ldr w5, [fp, #0x80] cmp w5, w24 str w5, [fp, #0x80] ldr w3, [fp, #0x84] ldr x11, [fp, #0x48] bge G_M000_IG156 ldr w5, [fp, #0x80] ldrh w1, [x11, w5, SXTW #2] str w5, [fp, #0x80] ldr x11, [fp, #0x48] cbz w1, G_M000_IG156 ldr w5, [fp, #0x80] add w5, w5, #1 str w5, [fp, #0x80] ldr w13, [x19, #0x08] add x12, x19, #16 mov x14, x12 ldr x12, [x14] ldr w14, [x14, #0x08] cmp w13, w14 bhs G_M000_IG129 cmp w13, w14 bhs G_M000_IG168 strh w1, [x12, w13, UXTW #2] add w1, w13, #1 str w1, [x19, #0x08] b G_M000_IG156 G_M000_IG129: str w9, [fp, #0x78] str w3, [fp, #0x84] str x0, [fp, #0x38] str w8, [fp, #0x34] mov x0, x19 movz x13, #0xD1FFAB1E movk x13, #0xD1FFAB1E LSL #16 movk x13, #0xD1FFAB1E LSL #32 ldr x13, [x13] blr x13 ldr x0, [fp, #0x38] ldr w3, [fp, #0x84] ldr w8, [fp, #0x34] ldr w9, [fp, #0x78] ldr x11, [fp, #0x48] b G_M000_IG156 G_M000_IG130: mov w13, wzr mov w14, wzr ldr w4, [fp, #0x8C] cbz w4, G_M000_IG145 ldr w5, [fp, #0x80] cmp w5, w24 bge G_M000_IG131 ldr x11, [fp, #0x48] ldrh w12, [x11, w5, SXTW #2] cmp w12, #48 beq G_M000_IG137 G_M000_IG131: add w12, w5, #1 cmp w12, w24 bge G_M000_IG133 ldr x11, [fp, #0x48] ldrh w12, [x11, w5, SXTW #2] cmp w12, #43 bne G_M000_IG132 add w15, w5, #1 ldrh w15, [x11, w15, SXTW #2] cmp w15, #48 bne G_M000_IG132 mov w13, #1 b G_M000_IG138 G_M000_IG132: cmp w12, #45 bne G_M000_IG135 str w5, [fp, #0x80] add w12, w5, #1 ldrh w12, [x11, w12, SXTW #2] cmp w12, #48 ldr w5, [fp, #0x80] beq G_M000_IG134 G_M000_IG133: ldr w13, [x19, #0x08] add x14, x19, #16 ldr x12, [x14] ldr w14, [x14, #0x08] cmp w13, w14 bhs G_M000_IG136 cmp w13, w14 bhs G_M000_IG168 strh w1, [x12, w13, UXTW #2] add w1, w13, #1 str w1, [x19, #0x08] str w5, [fp, #0x80] ldr w3, [fp, #0x84] ldr x11, [fp, #0x48] b G_M000_IG156 G_M000_IG134: ldr x11, [fp, #0x48] b G_M000_IG138 G_M000_IG135: b G_M000_IG133 G_M000_IG136: str w5, [fp, #0x80] str w9, [fp, #0x78] str x0, [fp, #0x38] str w8, [fp, #0x34] mov x0, x19 movz x13, #0xD1FFAB1E movk x13, #0xD1FFAB1E LSL #16 movk x13, #0xD1FFAB1E LSL #32 ldr x13, [x13] blr x13 ldr x0, [fp, #0x38] ldr w3, [fp, #0x84] ldr w8, [fp, #0x34] ldr w9, [fp, #0x78] ldr x11, [fp, #0x48] b G_M000_IG156 G_M000_IG137: add w14, w14, #1 G_M000_IG138: add w5, w5, #1 mov w12, w5 cmp w12, w24 bge G_M000_IG140 str w12, [fp, #0x80] ldrh w4, [x11, w12, SXTW #2] cmp w4, #48 ldr x11, [fp, #0x48] beq G_M000_IG142 G_M000_IG139: ldr w12, [fp, #0x80] G_M000_IG140: cmp w14, #10 ble G_M000_IG141 mov w14, #10 G_M000_IG141: ldrb w4, [x23] cbz w4, G_M000_IG143 ldr w4, [x21, #0x04] sub w4, w4, w27 stp w1, w12, [fp, #0x7C] str w9, [fp, #0x78] str x0, [fp, #0x38] str w8, [fp, #0x34] b G_M000_IG144 G_M000_IG142: ldr w5, [fp, #0x80] b G_M000_IG137 G_M000_IG143: mov w4, wzr stp w1, w12, [fp, #0x7C] str w9, [fp, #0x78] str x0, [fp, #0x38] str w8, [fp, #0x34] G_M000_IG144: mov x0, x19 mov x1, x20 mov w2, w4 ldr w3, [fp, #0x7C] mov w4, w14 mov w5, w13 movz x13, #0xD1FFAB1E movk x13, #0xD1FFAB1E LSL #16 movk x13, #0xD1FFAB1E LSL #32 ldr x13, [x13] blr x13 str wzr, [fp, #0x8C] ldr x0, [fp, #0x38] ldr w3, [fp, #0x84] ldr w8, [fp, #0x34] ldr w9, [fp, #0x78] ldr x11, [fp, #0x48] b G_M000_IG156 G_M000_IG145: ldr w13, [x19, #0x08] add x14, x19, #16 str x14, [fp, #0x10] mov x12, x14 ldr x15, [x12] ldr w12, [x12, #0x08] cmp w13, w12 bhs G_M000_IG146 cmp w13, w12 bhs G_M000_IG168 strh w1, [x15, w13, UXTW #2] add w1, w13, #1 str w1, [x19, #0x08] b G_M000_IG147 G_M000_IG146: str w9, [fp, #0x78] str x0, [fp, #0x38] str w8, [fp, #0x34] mov x0, x19 movz x13, #0xD1FFAB1E movk x13, #0xD1FFAB1E LSL #16 movk x13, #0xD1FFAB1E LSL #32 ldr x13, [x13] blr x13 ldr x0, [fp, #0x38] ldr w8, [fp, #0x34] ldr w9, [fp, #0x78] G_M000_IG147: ldr w5, [fp, #0x80] cmp w5, w24 str w5, [fp, #0x80] ldr w3, [fp, #0x84] ldr x11, [fp, #0x48] bge G_M000_IG156 ldr x14, [fp, #0x10] ldr w5, [fp, #0x80] ldrh w1, [x11, w5, SXTW #2] cmp w1, #43 beq G_M000_IG148 cmp w1, #45 bne G_M000_IG152 G_M000_IG148: add w5, w5, #1 str w5, [fp, #0x80] ldr w13, [x19, #0x08] str x14, [fp, #0x10] mov x12, x14 ldr x15, [x12] ldr w12, [x12, #0x08] cmp w13, w12 bhs G_M000_IG149 cmp w13, w12 bhs G_M000_IG168 strh w1, [x15, w13, UXTW #2] add w1, w13, #1 str w1, [x19, #0x08] ldr w5, [fp, #0x80] ldr x14, [fp, #0x10] b G_M000_IG152 G_M000_IG149: str w9, [fp, #0x78] str w3, [fp, #0x84] str x0, [fp, #0x38] str w8, [fp, #0x34] mov x0, x19 movz x13, #0xD1FFAB1E movk x13, #0xD1FFAB1E LSL #16 movk x13, #0xD1FFAB1E LSL #32 ldr x13, [x13] blr x13 ldr x0, [fp, #0x38] ldp w5, w3, [fp, #0x80] ldr w8, [fp, #0x34] ldr w9, [fp, #0x78] ldr x14, [fp, #0x10] b G_M000_IG152 G_M000_IG150: add w5, w5, #1 str w5, [fp, #0x80] ldr w13, [x19, #0x08] str x14, [fp, #0x10] mov x12, x14 ldr x15, [x12] ldr w12, [x12, #0x08] cmp w13, w12 bhs G_M000_IG151 cmp w13, w12 bhs G_M000_IG168 strh w1, [x15, w13, UXTW #2] add w1, w13, #1 str w1, [x19, #0x08] ldr w5, [fp, #0x80] ldr x14, [fp, #0x10] b G_M000_IG152 G_M000_IG151: str w9, [fp, #0x78] str w3, [fp, #0x84] str x0, [fp, #0x38] str w8, [fp, #0x34] mov x0, x19 movz x13, #0xD1FFAB1E movk x13, #0xD1FFAB1E LSL #16 movk x13, #0xD1FFAB1E LSL #32 ldr x13, [x13] blr x13 ldr x0, [fp, #0x38] ldp w5, w3, [fp, #0x80] ldr w8, [fp, #0x34] ldr w9, [fp, #0x78] ldr x14, [fp, #0x10] G_M000_IG152: cmp w5, w24 str w5, [fp, #0x80] ldr x11, [fp, #0x48] bge G_M000_IG156 ldr w5, [fp, #0x80] ldrh w1, [x11, w5, SXTW #2] cmp w1, #48 beq G_M000_IG150 G_M000_IG153: str w5, [fp, #0x80] ldr x11, [fp, #0x48] b G_M000_IG156 G_M000_IG154: ldr w13, [x19, #0x08] add x14, x19, #16 ldr x12, [x14] ldr w14, [x14, #0x08] cmp w13, w14 bhs G_M000_IG155 cmp w13, w14 bhs G_M000_IG168 strh w1, [x12, w13, UXTW #2] add w1, w13, #1 str w1, [x19, #0x08] ldr w3, [fp, #0x84] ldr x11, [fp, #0x48] b G_M000_IG156 G_M000_IG155: str w9, [fp, #0x78] str x0, [fp, #0x38] str w8, [fp, #0x34] mov x0, x19 movz x13, #0xD1FFAB1E movk x13, #0xD1FFAB1E LSL #16 movk x13, #0xD1FFAB1E LSL #32 ldr x13, [x13] blr x13 ldr x0, [fp, #0x38] ldr w3, [fp, #0x84] ldr w8, [fp, #0x34] ldr w9, [fp, #0x78] ldr x11, [fp, #0x48] G_M000_IG156: ldr w5, [fp, #0x80] cmp w5, w24 bge G_M000_IG158 G_M000_IG157: mov w1, w5 add w5, w1, #1 str w5, [fp, #0x80] ldrh w1, [x11, w1, SXTW #2] cbz w1, G_M000_IG158 cmp w1, #59 bne G_M000_IG67 G_M000_IG158: str xzr, [fp, #0x40] ldrb w2, [x21, #0x08] cbz w2, G_M000_IG162 G_M000_IG159: cbnz w25, G_M000_IG162 ldr w2, [x21, #0x04] cbnz w2, G_M000_IG162 ldr w2, [x19, #0x08] cmp w2, #0 ble G_M000_IG162 ldr x2, [x20, #0x28] cbz x2, G_M000_IG164 G_M000_IG160: add x3, x2, #12 ldr w0, [x2, #0x08] G_M000_IG161: mov x2, x3 mov w3, w0 mov x0, x19 mov w1, wzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG162: movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #0xB8] cmp xip0, xip1 beq G_M000_IG163 bl CORINFO_HELP_FAIL_FAST G_M000_IG163: ldp x27, x28, [sp, #0xD1FFAB1E] ldp x25, x26, [sp, #0xF0] ldp x23, x24, [sp, #0xE0] ldp x21, x22, [sp, #0xD0] ldp x19, x20, [sp, #0xC0] ldp fp, lr, [sp], #0xD1FFAB1E ret lr G_M000_IG164: mov x3, xzr mov w0, wzr b G_M000_IG161 G_M000_IG165: bl CORINFO_HELP_THROWDIVZERO G_M000_IG166: bl CORINFO_HELP_OVERFLOW G_M000_IG167: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 G_M000_IG168: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 RWD00 dd G_M000_IG22 - G_M000_IG02 dd G_M000_IG14 - G_M000_IG02 dd G_M000_IG09 - G_M000_IG02 dd G_M000_IG21 - G_M000_IG02 dd G_M000_IG09 - G_M000_IG02 dd G_M000_IG22 - G_M000_IG02 RWD24 dd G_M000_IG18 - G_M000_IG02 dd G_M000_IG11 - G_M000_IG02 dd G_M000_IG17 - G_M000_IG02 dd G_M000_IG11 - G_M000_IG02 dd G_M000_IG15 - G_M000_IG02 RWD44 dd G_M000_IG124 - G_M000_IG02 dd G_M000_IG88 - G_M000_IG02 dd G_M000_IG154 - G_M000_IG02 dd G_M000_IG117 - G_M000_IG02 dd G_M000_IG154 - G_M000_IG02 dd G_M000_IG124 - G_M000_IG02 RWD68 dd G_M000_IG85 - G_M000_IG02 dd G_M000_IG154 - G_M000_IG02 dd G_M000_IG105 - G_M000_IG02 dd G_M000_IG154 - G_M000_IG02 dd G_M000_IG88 - G_M000_IG02 ; Total bytes of code 4984 829: JIT compiled System.Number:NumberToStringFormat[ushort](byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo) [Tier-0 switched to FullOpts, IL size=2089, code size=4984] ; Assembly listing for method System.Number:FindSection(System.ReadOnlySpan`1[ushort],int):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp str xzr, [fp, #0x40] str x0, [fp, #0x60] str x1, [fp, #0x68] str w2, [fp, #0x5C] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x20] ldr w0, [fp, #0x5C] cbnz w0, G_M000_IG04 mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG04: ldr x0, [fp, #0x60] ldr x1, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x40] ldr x0, [fp, #0x40] str x0, [fp, #0x18] ldr x0, [fp, #0x18] str x0, [fp, #0x48] str wzr, [fp, #0x58] G_M000_IG05: ldr w0, [fp, #0x20] sub w0, w0, #1 str w0, [fp, #0x20] ldr w0, [fp, #0x20] cmp w0, #0 bgt G_M000_IG07 G_M000_IG06: add x0, fp, #32 mov w1, #17 bl CORINFO_HELP_PATCHPOINT G_M000_IG07: ldr w0, [fp, #0x58] ldr w1, [fp, #0x68] cmp w0, w1 blt G_M000_IG09 mov w0, wzr G_M000_IG08: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG09: ldr w0, [fp, #0x58] str w0, [fp, #0x38] ldr w0, [fp, #0x58] add w0, w0, #1 str w0, [fp, #0x58] ldr x0, [fp, #0x48] ldr w1, [fp, #0x38] sxtw x1, w1 mov w2, #2 sxtw x2, w2 mul x1, x1, x2 ldrh w0, [x0, x1] str w0, [fp, #0x34] ldr w0, [fp, #0x34] uxth w0, w0 str w0, [fp, #0x54] ldr w0, [fp, #0x34] uxth w0, w0 str w0, [fp, #0x3C] ldr w0, [fp, #0x3C] cmp w0, #34 bhi G_M000_IG10 ldr w0, [fp, #0x3C] cbz w0, G_M000_IG17 ldr w0, [fp, #0x3C] cmp w0, #34 beq G_M000_IG11 b G_M000_IG05 G_M000_IG10: ldr w0, [fp, #0x3C] cmp w0, #39 beq G_M000_IG11 ldr w0, [fp, #0x3C] cmp w0, #59 beq G_M000_IG15 ldr w0, [fp, #0x3C] cmp w0, #92 beq G_M000_IG14 b G_M000_IG05 G_M000_IG11: ldr w0, [fp, #0x20] sub w0, w0, #1 str w0, [fp, #0x20] ldr w0, [fp, #0x20] cmp w0, #0 bgt G_M000_IG13 G_M000_IG12: add x0, fp, #32 mov w1, #85 bl CORINFO_HELP_PATCHPOINT G_M000_IG13: ldr w0, [fp, #0x58] ldr w1, [fp, #0x68] cmp w0, w1 bge G_M000_IG05 ldr x0, [fp, #0x48] ldr w1, [fp, #0x58] sxtw x1, w1 mov w2, #2 sxtw x2, w2 mul x1, x1, x2 ldrh w0, [x0, x1] cbz w0, G_M000_IG05 ldr w0, [fp, #0x58] str w0, [fp, #0x30] ldr w0, [fp, #0x58] add w0, w0, #1 str w0, [fp, #0x58] ldr x0, [fp, #0x48] ldr w1, [fp, #0x30] sxtw x1, w1 mov w2, #2 sxtw x2, w2 mul x1, x1, x2 ldrh w0, [x0, x1] ldr w1, [fp, #0x54] cmp w0, w1 bne G_M000_IG11 b G_M000_IG05 G_M000_IG14: ldr w0, [fp, #0x58] ldr w1, [fp, #0x68] cmp w0, w1 bge G_M000_IG05 ldr x0, [fp, #0x48] ldr w1, [fp, #0x58] sxtw x1, w1 mov w2, #2 sxtw x2, w2 mul x1, x1, x2 ldrh w0, [x0, x1] cbz w0, G_M000_IG05 ldr w0, [fp, #0x58] add w0, w0, #1 str w0, [fp, #0x58] b G_M000_IG05 G_M000_IG15: ldr w0, [fp, #0x5C] sub w0, w0, #1 str w0, [fp, #0x2C] ldr w0, [fp, #0x5C] sub w0, w0, #1 str w0, [fp, #0x5C] ldr w0, [fp, #0x2C] cbnz w0, G_M000_IG05 ldr w0, [fp, #0x58] ldr w1, [fp, #0x68] cmp w0, w1 bge G_M000_IG17 ldr x0, [fp, #0x48] ldr w1, [fp, #0x58] sxtw x1, w1 mov w2, #2 sxtw x2, w2 mul x1, x1, x2 ldrh w0, [x0, x1] cbz w0, G_M000_IG17 ldr x0, [fp, #0x48] ldr w1, [fp, #0x58] sxtw x1, w1 mov w2, #2 sxtw x2, w2 mul x1, x1, x2 ldrh w0, [x0, x1] cmp w0, #59 beq G_M000_IG17 ldr w0, [fp, #0x58] G_M000_IG16: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG17: mov w0, wzr G_M000_IG18: ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 672 830: JIT compiled System.Number:FindSection(System.ReadOnlySpan`1[ushort],int) [Tier0, IL size=190, code size=672] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:GetAverageTime():Perfolizer.Horology.TimeInterval:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x10] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 scvtf d0, x0 ldr d16, [fp, #0x10] fdiv d0, d16, d0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 104 831: JIT compiled BenchmarkDotNet.Reports.Measurement:GetAverageTime() [Tier0, IL size=20, code size=104] ; Assembly listing for method Perfolizer.Horology.TimeInterval:FromNanoseconds(double):Perfolizer.Horology.TimeInterval ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str d0, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr d0, [x0] ldr d1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 60 832: JIT compiled Perfolizer.Horology.TimeInterval:FromNanoseconds(double) [Tier0, IL size=12, code size=60] ; Assembly listing for method Perfolizer.Horology.TimeInterval:op_Multiply(Perfolizer.Horology.TimeInterval,double):Perfolizer.Horology.TimeInterval ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str d0, [fp, #0x28] str d1, [fp, #0x20] G_M000_IG02: str xzr, [fp, #0x18] add x0, fp, #40 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0x20] fmul d0, d0, d16 str d0, [fp, #0x10] ldr d0, [fp, #0x10] add x0, fp, #24 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 833: JIT compiled Perfolizer.Horology.TimeInterval:op_Multiply(Perfolizer.Horology.TimeInterval,double) [Tier0, IL size=15, code size=96] ; Assembly listing for method BenchmarkDotNet.Helpers.AsciiHelper:ToAscii(System.String):System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] cbnz x0, G_M000_IG04 mov x0, xzr G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 88 834: JIT compiled BenchmarkDotNet.Helpers.AsciiHelper:ToAscii(System.String) [Tier0, IL size=22, code size=88] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:WriteLine(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x20] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 835: JIT compiled BenchmarkDotNet.Engines.Engine:WriteLine(System.String) [Tier0, IL size=13, code size=84] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_Host():BenchmarkDotNet.Engines.IHost:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 836: JIT compiled BenchmarkDotNet.Engines.Engine:get_Host() [Tier0, IL size=7, code size=28] ; Assembly listing for method System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:Add(BenchmarkDotNet.Reports.Measurement):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str xzr, [fp, #0x48] str xzr, [fp, #0x18] str x0, [fp, #0x58] str x1, [fp, #0x50] G_M000_IG02: ldr x0, [fp, #0x58] ldr w0, [x0, #0x14] add w0, w0, #1 ldr x1, [fp, #0x58] str w0, [x1, #0x14] ldr x0, [fp, #0x58] ldr x0, [x0, #0x08] str x0, [fp, #0x48] ldr x0, [fp, #0x58] ldr w0, [x0, #0x10] str w0, [fp, #0x44] ldr w0, [fp, #0x44] ldr x1, [fp, #0x48] ldr w1, [x1, #0x08] cmp w0, w1 bhs G_M000_IG04 ldr w0, [fp, #0x44] add w0, w0, #1 ldr x1, [fp, #0x58] str w0, [x1, #0x10] ldr x0, [fp, #0x48] ldr w1, [fp, #0x44] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG06 add x0, x0, x1, LSL #5 add x0, x0, #16 ldr x1, [fp, #0x50] ldp q16, q17, [x1] stp q16, q17, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG04: ldr x0, [fp, #0x58] str x0, [fp, #0x18] ldr x0, [fp, #0x50] ldp q16, q17, [x0] stp q16, q17, [fp, #0x20] ldr x0, [fp, #0x18] add x1, fp, #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG05: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG06: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 216 837: JIT compiled System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:Add(BenchmarkDotNet.Reports.Measurement) [Tier0, IL size=60, code size=216] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:Consume(byref):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 24 838: JIT compiled BenchmarkDotNet.Engines.Engine:Consume(byref) [Tier0, IL size=1, code size=24] ; Assembly listing for method BenchmarkDotNet.Engines.DeadCodeEliminationHelper:KeepAliveWithoutBoxing[BenchmarkDotNet.Reports.Measurement](BenchmarkDotNet.Reports.Measurement) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 20 839: JIT compiled BenchmarkDotNet.Engines.DeadCodeEliminationHelper:KeepAliveWithoutBoxing[BenchmarkDotNet.Reports.Measurement](BenchmarkDotNet.Reports.Measurement) [Tier0, IL size=1, code size=20] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_Dummy2Action():System.Action:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 840: JIT compiled BenchmarkDotNet.Engines.Engine:get_Dummy2Action() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Autogenerated.Runnable_0:Dummy2():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] G_M000_IG03: str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] G_M000_IG04: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 1300 841: JIT compiled BenchmarkDotNet.Autogenerated.Runnable_0:Dummy2() [Tier0, IL size=897, code size=1300] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_MemoryRandomization():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldrb w0, [x0, #0xBA] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 842: JIT compiled BenchmarkDotNet.Engines.Engine:get_MemoryRandomization() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_WorkloadAction():System.Action`1[long]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 843: JIT compiled BenchmarkDotNet.Engines.Engine:get_WorkloadAction() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_IterationSetupAction():System.Action:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x50] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 844: JIT compiled BenchmarkDotNet.Engines.Engine:get_IterationSetupAction() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Autogenerated.Runnable_0+<>c:<.ctor>b__3_1():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 20 845: JIT compiled BenchmarkDotNet.Autogenerated.Runnable_0+<>c:<.ctor>b__3_1() [Tier0, IL size=1, code size=20] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:WorkloadJittingStart(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x2, [fp, #0x10] mov w1, #5 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 846: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:WorkloadJittingStart(long) [Tier0, IL size=9, code size=56] ; Assembly listing for method BenchmarkDotNet.Autogenerated.Runnable_0:WorkloadActionNoUnroll(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x18] str x21, [sp, #0x28] mov fp, sp mov x20, x0 mov x19, x1 G_M000_IG02: mov x21, xzr cmp x19, #0 ble G_M000_IG04 G_M000_IG03: ldr x1, [x20, #0x30] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 add x21, x21, #1 cmp x21, x19 blt G_M000_IG03 G_M000_IG04: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 80 847: JIT compiled BenchmarkDotNet.Autogenerated.Runnable_0:WorkloadActionNoUnroll(long) [Tier1, IL size=26, code size=80] ; Assembly listing for method System.Reflection.Invoke:Property_Set_class():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str wzr, [fp, #0x24] str x0, [fp, #0x28] G_M000_IG02: str wzr, [fp, #0x24] mov w0, #0xD1FFAB1E str w0, [fp, #0x18] b G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] mov x2, xzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr w0, [fp, #0x24] add w0, w0, #1 str w0, [fp, #0x24] G_M000_IG04: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG06 G_M000_IG05: add x0, fp, #24 mov w1, #24 bl CORINFO_HELP_PATCHPOINT G_M000_IG06: ldr w0, [fp, #0x24] cmp w0, #0xD1FFAB1E blt G_M000_IG03 G_M000_IG07: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 160 848: JIT compiled System.Reflection.Invoke:Property_Set_class() [Tier0, IL size=33, code size=160] ; Assembly listing for method System.Reflection.Invoke+MyClass:set_O(System.Object):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] add x14, x14, #24 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 849: JIT compiled System.Reflection.Invoke+MyClass:set_O(System.Object) [Tier0, IL size=8, code size=40] ; Assembly listing for method (dynamicClass):InvokeStub_MyClass.set_O(System.Object,System.Object,ulong):System.Object ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp mov x0, x1 G_M000_IG02: ldr x1, [x2] ldr x1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 mov x0, xzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 56 850: JIT compiled (dynamicClass):InvokeStub_MyClass.set_O(System.Object,System.Object,ulong) [FullOpts, IL size=25, code size=56] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:WorkloadJittingStop(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x2, [fp, #0x10] mov w1, #6 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 851: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:WorkloadJittingStop(long) [Tier0, IL size=9, code size=56] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_IterationCleanupAction():System.Action:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x58] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 852: JIT compiled BenchmarkDotNet.Engines.Engine:get_IterationCleanupAction() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Autogenerated.Runnable_0+<>c:<.ctor>b__3_2():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 20 853: JIT compiled BenchmarkDotNet.Autogenerated.Runnable_0+<>c:<.ctor>b__3_2() [Tier0, IL size=1, code size=20] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_Dummy3Action():System.Action:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x28] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 854: JIT compiled BenchmarkDotNet.Engines.Engine:get_Dummy3Action() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Autogenerated.Runnable_0:Dummy3():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] G_M000_IG03: str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] ldr x0, [fp, #0x18] ldr w0, [x0, #0x3C] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x3C] G_M000_IG04: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 1300 855: JIT compiled BenchmarkDotNet.Autogenerated.Runnable_0:Dummy3() [Tier0, IL size=897, code size=1300] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:WriteLine():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x0, [fp, #0x10] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 76 856: JIT compiled BenchmarkDotNet.Engines.Engine:WriteLine() [Tier0, IL size=12, code size=76] ; Assembly listing for method BenchmarkDotNet.Engines.EngineParameters:get_IterationTime():Perfolizer.Horology.TimeInterval:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 112 857: JIT compiled BenchmarkDotNet.Engines.EngineParameters:get_IterationTime() [Tier0, IL size=22, code size=112] ; Assembly listing for method BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass2_0`1[int]:b__0(BenchmarkDotNet.Characteristics.CharacteristicObject):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x08] ldr x1, [fp, #0x20] ldr x2, [fp, #0x10] ldr x2, [x2, #0x18] blr x2 ldr x1, [fp, #0x18] str w0, [x1, #0x08] ldr x0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 100 858: JIT compiled BenchmarkDotNet.Characteristics.Resolver+<>c__DisplayClass2_0`1[int]:b__0(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=18, code size=100] ; Assembly listing for method BenchmarkDotNet.Environments.EnvironmentResolver+<>c:<.ctor>b__2_2(BenchmarkDotNet.Characteristics.CharacteristicObject):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] str xzr, [x9, #0x40] str x0, [fp, #0x68] str x1, [fp, #0x60] G_M000_IG02: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr x0, [fp, #0x60] mov w2, wzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 str w0, [fp, #0x5C] ldr w0, [fp, #0x5C] cbz w0, G_M000_IG04 ldr w0, [fp, #0x5C] sub w0, w0, #1 cmp w0, #1 bls G_M000_IG06 G_M000_IG03: b G_M000_IG08 G_M000_IG04: mov w0, #16 G_M000_IG05: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG06: mov w0, #1 G_M000_IG07: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG08: add x0, fp, #48 mov w1, #21 mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x20] ldr x1, [fp, #0x20] add x0, fp, #48 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #48 ldr w1, [fp, #0x5C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x28] bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 340 859: JIT compiled BenchmarkDotNet.Environments.EnvironmentResolver+<>c:<.ctor>b__2_2(BenchmarkDotNet.Characteristics.CharacteristicObject) [Tier0, IL size=72, code size=340] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],int):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x38] str x1, [fp, #0x30] str w2, [fp, #0x2C] G_M000_IG02: ldr x0, [fp, #0x38] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x2, [fp, #0x20] ldr w0, [fp, #0x2C] str w0, [x2, #0x08] ldr x2, [fp, #0x20] ldr x0, [fp, #0x30] ldr x1, [fp, #0x38] ldr x3, [fp, #0x30] ldr x3, [x3] ldr x3, [x3, #0x40] ldr x3, [x3, #0x20] blr x3 str x0, [fp, #0x18] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG04: ldr x0, [fp, #0x38] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG05: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 212 860: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValue[int](BenchmarkDotNet.Characteristics.Characteristic`1[int],int) [Tier0, IL size=36, code size=212] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[int]:ResolveValueCore(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Object):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] G_M000_IG02: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz x0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x38] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x20] ldr x1, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [x0] ldr x1, [fp, #0x28] str w0, [x1, #0x08] ldr x0, [fp, #0x28] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG04: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x38] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x18] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w2, [x0] str w2, [fp, #0x14] ldr w2, [fp, #0x14] ldr x1, [fp, #0x40] ldr x0, [fp, #0x30] ldr x0, [x0, #0x08] ldr x3, [fp, #0x30] ldr x3, [x3, #0x18] blr x3 ldr x1, [fp, #0x28] str w0, [x1, #0x08] ldr x0, [fp, #0x28] G_M000_IG05: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 356 861: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[int]:ResolveValueCore(BenchmarkDotNet.Characteristics.CharacteristicObject,System.Object) [Tier0, IL size=58, code size=356] ; Assembly listing for method BenchmarkDotNet.Characteristics.Characteristic`1[int]:get_Resolver():System.Func`3[BenchmarkDotNet.Characteristics.CharacteristicObject,int,int]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x30] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 862: JIT compiled BenchmarkDotNet.Characteristics.Characteristic`1[int]:get_Resolver() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EngineFactory:CreateMultiActionEngine(BenchmarkDotNet.Engines.EngineParameters):BenchmarkDotNet.Engines.Engine ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x18] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x10] ldr x3, [fp, #0x10] ldr x1, [fp, #0x20] ldr x2, [fp, #0x18] ldr x0, [fp, #0x28] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 164 863: JIT compiled BenchmarkDotNet.Engines.EngineFactory:CreateMultiActionEngine(BenchmarkDotNet.Engines.EngineParameters) [Tier0, IL size=25, code size=164] ; Assembly listing for method BenchmarkDotNet.Engines.EngineResolver+<>c:<.ctor>b__7_9():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: mov w0, #1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 24 864: JIT compiled BenchmarkDotNet.Engines.EngineResolver+<>c:<.ctor>b__7_9() [Tier0, IL size=2, code size=24] ; Assembly listing for method BenchmarkDotNet.Autogenerated.Runnable_0:OverheadActionUnroll(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x18] str x21, [sp, #0x28] mov fp, sp mov x19, x0 mov x20, x1 G_M000_IG02: mov x21, xzr cmp x20, #0 ble G_M000_IG04 G_M000_IG03: ldr x1, [x19, #0x28] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x28] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x28] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x28] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x28] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x28] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x28] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x28] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x28] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x28] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x28] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x28] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x28] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x28] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x28] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x28] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 add x21, x21, #1 cmp x21, x20 blt G_M000_IG03 G_M000_IG04: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 320 865: JIT compiled BenchmarkDotNet.Autogenerated.Runnable_0:OverheadActionUnroll(long) [Tier1, IL size=197, code size=320] ; Assembly listing for method System.Char:System.IUtfChar.CastFrom(ulong):ushort ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] uxth w0, w0 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 866: JIT compiled System.Char:System.IUtfChar.CastFrom(ulong) [Tier0, IL size=3, code size=28] ; Assembly listing for method BenchmarkDotNet.Autogenerated.Runnable_0:WorkloadActionUnroll(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x18] str x21, [sp, #0x28] mov fp, sp mov x19, x0 mov x20, x1 G_M000_IG02: mov x21, xzr cmp x20, #0 ble G_M000_IG04 G_M000_IG03: ldr x1, [x19, #0x30] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x30] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x30] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x30] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x30] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x30] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x30] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x30] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x30] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x30] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x30] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x30] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x30] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x30] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x30] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 ldr x1, [x19, #0x30] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 add x21, x21, #1 cmp x21, x20 blt G_M000_IG03 G_M000_IG04: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 320 867: JIT compiled BenchmarkDotNet.Autogenerated.Runnable_0:WorkloadActionUnroll(long) [Tier1, IL size=197, code size=320] ; Assembly listing for method System.Reflection.Invoke:Property_Set_class():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; OSR variant for entry point 0x18 ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 2 inlinees with PGO data; 0 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x18] str x21, [sp, #0x28] mov fp, sp ldr w19, [fp, #0x54] G_M000_IG02: cmp w19, #0xD1FFAB1E bge G_M000_IG06 movz x20, #0xD1FFAB1E movk x20, #0xD1FFAB1E LSL #16 movk x20, #0xD1FFAB1E LSL #32 movz x21, #0xD1FFAB1E movk x21, #0xD1FFAB1E LSL #16 movk x21, #0xD1FFAB1E LSL #32 G_M000_IG03: ldr x0, [x20] ldr x1, [x20, #-0x60] ldr x2, [x0] cmp x2, x21 bne G_M000_IG07 G_M000_IG04: mov x2, xzr mov w3, #60 mov x4, xzr mov x5, xzr mov x6, xzr movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 G_M000_IG05: add w19, w19, #1 cmp w19, #0xD1FFAB1E blt G_M000_IG03 G_M000_IG06: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 add sp, sp, #48 ret lr G_M000_IG07: mov x2, xzr mov x3, xzr ldr x4, [x0] ldr x4, [x4, #0x60] ldr x4, [x4, #0x18] blr x4 b G_M000_IG05 ; Total bytes of code 172 868: JIT compiled System.Reflection.Invoke:Property_Set_class() [Tier1-OSR @0x18, IL size=33, code size=172] ; Assembly listing for method BenchmarkDotNet.Engines.DeadCodeEliminationHelper:KeepAliveWithoutBoxing[Perfolizer.Horology.TimeInterval](Perfolizer.Horology.TimeInterval) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str d0, [fp, #0x18] G_M000_IG02: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 20 869: JIT compiled BenchmarkDotNet.Engines.DeadCodeEliminationHelper:KeepAliveWithoutBoxing[Perfolizer.Horology.TimeInterval](Perfolizer.Horology.TimeInterval) [Tier0, IL size=1, code size=20] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:Run():BenchmarkDotNet.Engines.RunResults:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: sub sp, sp, #0xD1FFAB1E stp fp, lr, [sp] mov fp, sp movi v16.16b, #0 add x9, fp, #96 add x10, fp, #0xD1FFAB1E stp q16, q16, [x9, #-0x40] stp q16, q16, [x9, #-0x20] bfm x9, xzr, #0, #5 dczva x9 add x9, x9, #64 cmp x9, x10 blo pc-16 (-4 instructions) stp q16, q16, [x10] stp q16, q16, [x10, #0x20] str x0, [fp, #0xD1FFAB1E] str x8, [fp, #0xD1FFAB1E] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0xD1FFAB1E] str x1, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr x1, [x1, #0x80] ldr x0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xF0] ldr x2, [fp, #0xF0] ldr x1, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] mov x3, #1 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] ldr wzr, [x0] blr x4 str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbz w0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xF8] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xE8] ldr x1, [fp, #0xE8] ldr x0, [fp, #0xF8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cmp w0, #1 beq G_M000_IG07 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cmp w0, #2 beq G_M000_IG06 ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0xD1FFAB1E] str x1, [fp, #0xD1FFAB1E] G_M000_IG04: add x0, fp, #0xD1FFAB1E ldp x1, x2, [fp, #0xD1FFAB1E] stp x1, x2, [x0, #0xD1FFAB1E] G_M000_IG05: add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD1FFAB1E] add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xE0] ldr x1, [fp, #0xE0] ldr x0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG06 ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x90] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xDC] ldr w2, [fp, #0xDC] ldr x1, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 str x0, [fp, #0xD0] ldr x1, [fp, #0xD0] ldr x0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x98] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xCC] ldr w2, [fp, #0xCC] ldr x1, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 str x0, [fp, #0xC0] ldr x1, [fp, #0xC0] ldr x0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG06: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x90] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xBC] ldr w3, [fp, #0xBC] ldr x1, [fp, #0xD1FFAB1E] ldr w2, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] ldr wzr, [x0] blr x4 str x0, [fp, #0xB0] ldr x1, [fp, #0xB0] ldr x0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG07: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x98] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cmp w0, #2 cset x3, eq str w3, [fp, #0xAC] ldr w3, [fp, #0xAC] ldr x1, [fp, #0xD1FFAB1E] ldr w2, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] ldr wzr, [x0] blr x4 str x0, [fp, #0xA0] ldr x1, [fp, #0xA0] ldr x0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x8, [fp, #0xD1FFAB1E] ldrb w8, [x8, #0xBB] cbnz w8, G_M000_IG11 movz x8, #0xD1FFAB1E movk x8, #0xD1FFAB1E LSL #16 movk x8, #0xD1FFAB1E LSL #32 ldp q16, q17, [x8] stp q16, q17, [fp, #0xD1FFAB1E] add x8, fp, #0xD1FFAB1E movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG08: add x0, fp, #0xD1FFAB1E ldp q16, q17, [fp, #0xD1FFAB1E] stp q16, q17, [x0, #0xD1FFAB1E] G_M000_IG09: add x0, fp, #0xD1FFAB1E add x1, fp, #0xD1FFAB1E ldp x2, xip1, [x0] stp x2, xip1, [x1] ldr x2, [x0, #0x10] str x2, [x1, #0x10] G_M000_IG10: str xzr, [fp, #0xD1FFAB1E] b G_M000_IG15 G_M000_IG11: stp xzr, xzr, [fp, #0xD1FFAB1E] stp xzr, xzr, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x9C] ldr w5, [fp, #0x9C] add x0, fp, #0xD1FFAB1E ldr x4, [fp, #0xD1FFAB1E] mov w1, #1 mov w2, #3 mov w3, wzr movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x70] ldp x0, x1, [fp, #0xD1FFAB1E] stp x0, x1, [fp, #0x78] ldp x0, x1, [fp, #0xD1FFAB1E] stp x0, x1, [fp, #0x88] ldr x0, [fp, #0x70] add x1, fp, #120 add x8, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG12: add x0, fp, #0xD1FFAB1E add x1, fp, #0xD1FFAB1E ldp q16, q17, [x0] stp q16, q17, [x1] G_M000_IG13: add x0, fp, #0xD1FFAB1E add x1, fp, #0xD1FFAB1E ldp x2, xip1, [x0] stp x2, xip1, [x1] ldr x2, [x0, #0x10] str x2, [x1, #0x10] G_M000_IG14: ldr d16, [fp, #0xD1FFAB1E] str d16, [fp, #0xD1FFAB1E] G_M000_IG15: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbz w0, G_M000_IG16 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x68] ldr x1, [fp, #0x68] ldr x0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG16: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x60] ldr x2, [fp, #0x60] ldr x1, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 str w0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] str x1, [fp, #0x20] ldr w1, [fp, #0xD1FFAB1E] str w1, [fp, #0x1C] G_M000_IG17: add x1, fp, #0xD1FFAB1E ldp q0, q16, [x1, #0x40] stp q0, q16, [fp, #0x40] G_M000_IG18: add x1, fp, #0xD1FFAB1E ldp x2, x3, [x1, #0x28] stp x2, x3, [fp, #0x28] ldr x2, [x1, #0x38] str x2, [fp, #0x38] G_M000_IG19: ldr x1, [fp, #0x20] ldr w2, [fp, #0x1C] add x3, fp, #64 add x4, fp, #40 add x0, fp, #0xD1FFAB1E ldr d0, [fp, #0xD1FFAB1E] movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 ldr x14, [fp, #0xD1FFAB1E] add x13, fp, #0xD1FFAB1E bl CORINFO_HELP_ASSIGN_BYREF ldp x12, x15, [x13], #0x10 stp x12, x15, [x14], #0x10 ldp x12, x15, [x13], #0x10 stp x12, x15, [x14], #0x10 ldp x12, x15, [x13], #0x10 stp x12, x15, [x14], #0x10 ldp x12, x15, [x13], #0x10 stp x12, x15, [x14], #0x10 ldr x12, [x13], #0x08 str x12, [x14], #0x08 G_M000_IG20: ldp fp, lr, [sp] add sp, sp, #0xD1FFAB1E ret lr ; Total bytes of code 1920 870: JIT compiled BenchmarkDotNet.Engines.Engine:Run() [Tier0, IL size=419, code size=1920] ; Assembly listing for method System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #47 bl CORINFO_HELP_CLASSINIT_SHARED_DYNAMICCLASS movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 ldr x15, [x14] ldr x14, [fp, #0x18] add x14, x14, #8 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 92 871: JIT compiled System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:.ctor() [Tier0, IL size=18, code size=92] ; Assembly listing for method System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, xzr bl CORINFO_HELP_NEWARR_1_VC movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 56 872: JIT compiled System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:.cctor() [Tier0, IL size=12, code size=56] ; Assembly listing for method System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:AddRange(System.Collections.Generic.IEnumerable`1[BenchmarkDotNet.Reports.Measurement]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x90]! mov fp, sp str xzr, [fp, #0x70] str xzr, [fp, #0x60] str xzr, [fp, #0x10] add x2, sp, #144 str x2, [fp, #0x88] str x0, [fp, #0x80] str x1, [fp, #0x78] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x38] ldr x0, [fp, #0x78] cbnz x0, G_M000_IG03 mov w0, #23 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x1, [fp, #0x78] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x70] ldr x0, [fp, #0x70] cbz x0, G_M000_IG06 ldr x0, [fp, #0x70] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str w0, [fp, #0x6C] ldr w1, [fp, #0x6C] cmp w1, #0 ble G_M000_IG14 ldr x1, [fp, #0x80] ldr x1, [x1, #0x08] ldr w1, [x1, #0x08] ldr x0, [fp, #0x80] ldr w0, [x0, #0x10] sub w1, w1, w0 ldr w0, [fp, #0x6C] cmp w1, w0 bge G_M000_IG04 ldr x1, [fp, #0x80] ldr w1, [x1, #0x10] ldr w0, [fp, #0x6C] adds w1, w1, w0 bvs G_M000_IG15 ldr x0, [fp, #0x80] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG04: ldr x1, [fp, #0x80] ldr x1, [x1, #0x08] ldr x2, [fp, #0x80] ldr w2, [x2, #0x10] ldr x0, [fp, #0x70] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x3, [x11] blr x3 ldr x0, [fp, #0x80] ldr w0, [x0, #0x10] ldr w11, [fp, #0x6C] add w0, w0, w11 ldr x11, [fp, #0x80] str w0, [x11, #0x10] ldr x0, [fp, #0x80] ldr w0, [x0, #0x14] add w0, w0, #1 ldr x11, [fp, #0x80] str w0, [x11, #0x14] G_M000_IG05: ldp fp, lr, [sp], #0x90 ret lr G_M000_IG06: ldr x0, [fp, #0x78] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x60] G_M000_IG07: b G_M000_IG09 G_M000_IG08: add x8, fp, #64 ldr x0, [fp, #0x60] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 ldr x0, [fp, #0x80] str x0, [fp, #0x10] ldp x0, x1, [fp, #0x40] stp x0, x1, [fp, #0x18] ldp x0, x1, [fp, #0x50] stp x0, x1, [fp, #0x28] ldr x0, [fp, #0x10] add x1, fp, #24 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG09: ldr w0, [fp, #0x38] sub w0, w0, #1 str w0, [fp, #0x38] ldr w0, [fp, #0x38] cmp w0, #0 bgt G_M000_IG11 G_M000_IG10: add x0, fp, #56 mov w1, #131 bl CORINFO_HELP_PATCHPOINT G_M000_IG11: ldr x0, [fp, #0x60] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG08 b G_M000_IG12 G_M000_IG12: ldr x0, [fp, #0x88] bl G_M000_IG16 G_M000_IG13: nop G_M000_IG14: ldp fp, lr, [sp], #0x90 ret lr G_M000_IG15: bl CORINFO_HELP_OVERFLOW brk_windows #0 G_M000_IG16: stp fp, lr, [sp, #-0x20]! add x3, fp, #144 str x3, [sp, #0x18] G_M000_IG17: ldr x0, [fp, #0x60] cbz x0, G_M000_IG18 ldr x0, [fp, #0x60] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG18: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 596 873: JIT compiled System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:AddRange(System.Collections.Generic.IEnumerable`1[BenchmarkDotNet.Reports.Measurement]) [Tier0, IL size=152, code size=596] ; Assembly listing for method System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:get_Count():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 874: JIT compiled System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:get_Count() [Tier0, IL size=7, code size=28] ; Assembly listing for method System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:Grow(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] ldr w0, [x0, #0x08] cbz w0, G_M000_IG03 ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] ldr w0, [x0, #0x08] lsl w0, w0, #1 str w0, [fp, #0x1C] b G_M000_IG04 G_M000_IG03: mov w0, #4 str w0, [fp, #0x1C] G_M000_IG04: ldr w0, [fp, #0x1C] str w0, [fp, #0x20] ldr w0, [fp, #0x20] movz w1, #0xD1FFAB1E movk w1, #0xD1FFAB1E LSL #16 cmp w0, w1 bls G_M000_IG05 movz w0, #0xD1FFAB1E movk w0, #0xD1FFAB1E LSL #16 str w0, [fp, #0x20] G_M000_IG05: ldr w0, [fp, #0x20] ldr w1, [fp, #0x24] cmp w0, w1 bge G_M000_IG06 ldr w0, [fp, #0x24] str w0, [fp, #0x20] G_M000_IG06: ldr x0, [fp, #0x28] ldr w1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG07: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 164 875: JIT compiled System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:Grow(int) [Tier0, IL size=53, code size=164] ; Assembly listing for method System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:set_Capacity(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: ldr w0, [fp, #0x24] ldr x1, [fp, #0x28] ldr w1, [x1, #0x10] cmp w0, w1 bge G_M000_IG03 mov w0, #7 mov w1, #15 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldr w1, [fp, #0x24] ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] ldr w0, [x0, #0x08] cmp w1, w0 beq G_M000_IG07 ldr w1, [fp, #0x24] cmp w1, #0 ble G_M000_IG06 ldr w1, [fp, #0x24] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x18] ldr x0, [fp, #0x28] ldr w0, [x0, #0x10] cmp w0, #0 ble G_M000_IG04 ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] ldr x2, [fp, #0x28] ldr w2, [x2, #0x10] ldr x1, [fp, #0x18] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG04: ldr x14, [fp, #0x28] add x14, x14, #8 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG06: movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 ldr x15, [x14] ldr x14, [fp, #0x28] add x14, x14, #8 bl CORINFO_HELP_ASSIGN_REF G_M000_IG07: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 248 876: JIT compiled System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:set_Capacity(int) [Tier0, IL size=86, code size=248] ; Assembly listing for method System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:CopyTo(BenchmarkDotNet.Reports.Measurement[],int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] G_M000_IG02: ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] ldr x4, [fp, #0x28] ldr w4, [x4, #0x10] ldr x2, [fp, #0x20] ldr w3, [fp, #0x1C] mov w1, wzr movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 76 877: JIT compiled System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:CopyTo(BenchmarkDotNet.Reports.Measurement[],int) [Tier0, IL size=21, code size=76] ; Assembly listing for method BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValue[long](BenchmarkDotNet.Characteristics.Characteristic`1[long],BenchmarkDotNet.Characteristics.IResolver,long):long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x1, [fp, #0x30] str x2, [fp, #0x28] str x3, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x18] ldr x0, [fp, #0x28] ldr x1, [fp, #0x38] ldr x2, [fp, #0x30] ldr x3, [fp, #0x20] ldr x4, [fp, #0x18] blr x4 G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 92 878: JIT compiled BenchmarkDotNet.Characteristics.CharacteristicObject:ResolveValue[long](BenchmarkDotNet.Characteristics.Characteristic`1[long],BenchmarkDotNet.Characteristics.IResolver,long) [Tier0, IL size=10, code size=92] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver:Resolve[long](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[long],long):long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] str x0, [fp, #0x58] str x1, [fp, #0x50] str x2, [fp, #0x48] str x3, [fp, #0x40] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] str x14, [fp, #0x38] ldr x14, [fp, #0x38] add x14, x14, #8 ldr x15, [fp, #0x48] bl CORINFO_HELP_ASSIGN_REF ldr x1, [fp, #0x38] ldr x1, [x1, #0x08] ldr x0, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG04 ldr x0, [fp, #0x38] ldr x0, [x0, #0x08] ldr x1, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x58] ldr x0, [x0, #0x08] str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x2, [fp, #0x20] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x30] ldr x0, [fp, #0x30] cbz x0, G_M000_IG06 ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x10] ldr x2, [fp, #0x38] ldr x2, [x2, #0x08] ldr x0, [fp, #0x30] ldr x1, [fp, #0x50] ldr x3, [fp, #0x40] ldr x4, [fp, #0x10] blr x4 G_M000_IG05: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG06: ldr x0, [fp, #0x40] G_M000_IG07: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 400 879: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver:Resolve[long](BenchmarkDotNet.Characteristics.CharacteristicObject,BenchmarkDotNet.Characteristics.Characteristic`1[long],long) [Tier0, IL size=84, code size=400] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass6_0`1[long]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 880: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass6_0`1[long]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass6_0`1[long]:b__0(BenchmarkDotNet.Characteristics.IResolver):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x1, [fp, #0x18] ldr x1, [x1, #0x08] ldr x0, [fp, #0x10] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 881: JIT compiled BenchmarkDotNet.Characteristics.CompositeResolver+<>c__DisplayClass6_0`1[long]:b__0(BenchmarkDotNet.Characteristics.IResolver) [Tier0, IL size=13, code size=56] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_BenchmarkName():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x70] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 882: JIT compiled BenchmarkDotNet.Engines.Engine:get_BenchmarkName() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:BenchmarkStart(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x2, [fp, #0x10] mov w1, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 883: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:BenchmarkStart(System.String) [Tier0, IL size=9, code size=56] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_Strategy():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0xB4] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 884: JIT compiled BenchmarkDotNet.Engines.Engine:get_Strategy() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EnginePilotStage:Run():BenchmarkDotNet.Engines.EnginePilotStage+PilotStageResult:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] str xzr, [x9, #0x40] str x0, [fp, #0x58] G_M000_IG02: ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbz w0, G_M000_IG04 ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] add x0, fp, #40 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x28] ldr x1, [fp, #0x30] G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG04: ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbnz w0, G_M000_IG06 ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x38] str x1, [fp, #0x40] ldr x0, [fp, #0x38] ldr x1, [fp, #0x40] G_M000_IG05: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG06: ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x48] str x1, [fp, #0x50] ldr x0, [fp, #0x48] ldr x1, [fp, #0x50] G_M000_IG07: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 400 885: JIT compiled BenchmarkDotNet.Engines.EnginePilotStage:Run() [Tier0, IL size=72, code size=400] ; Assembly listing for method BenchmarkDotNet.Engines.EngineStage:get_TargetJob():BenchmarkDotNet.Jobs.Job:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 48 886: JIT compiled BenchmarkDotNet.Engines.EngineStage:get_TargetJob() [Tier0, IL size=12, code size=48] ; Assembly listing for method BenchmarkDotNet.Engines.EnginePilotStage:RunSpecific():BenchmarkDotNet.Engines.EnginePilotStage+PilotStageResult:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0xC0]! mov fp, sp add x9, fp, #32 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] stp xzr, xzr, [x9, #0x80] str xzr, [x9, #0x90] str x0, [fp, #0xB8] G_M000_IG02: ldr x0, [fp, #0xB8] mov x1, #4 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0xB0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x68] ldr x0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x68] str x0, [fp, #0xA8] str wzr, [fp, #0xA4] str wzr, [fp, #0xA0] mov w0, #0xD1FFAB1E str w0, [fp, #0x48] G_M000_IG03: ldr w0, [fp, #0x48] sub w0, w0, #1 str w0, [fp, #0x48] ldr w0, [fp, #0x48] cmp w0, #0 bgt G_M000_IG05 G_M000_IG04: add x0, fp, #72 mov w1, #19 bl CORINFO_HELP_PATCHPOINT G_M000_IG05: ldr w5, [fp, #0xA4] add w5, w5, #1 str w5, [fp, #0xA4] ldr x5, [fp, #0xB8] ldr w5, [x5, #0x28] add x8, fp, #128 ldr x0, [fp, #0xB8] ldr x4, [fp, #0xB0] ldr w3, [fp, #0xA4] mov w1, #1 mov w2, #1 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x0, [fp, #0xA8] str x0, [fp, #0x20] ldp x0, x1, [fp, #0x80] stp x0, x1, [fp, #0x28] ldp x0, x1, [fp, #0x90] stp x0, x1, [fp, #0x38] ldr x0, [fp, #0x20] add x1, fp, #40 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 add x0, fp, #128 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x78] ldr x0, [fp, #0xB8] ldr w0, [x0, #0x2C] sxtw x0, w0 str x0, [fp, #0x60] ldr x0, [fp, #0xB0] scvtf d0, x0 ldr x0, [fp, #0xB8] ldr d16, [x0, #0x18] fmul d0, d0, d16 ldr d16, [fp, #0x78] fdiv d0, d0, d16 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 fcvtzs x1, d0 str x1, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x60] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0xB8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x70] ldr x0, [fp, #0x70] ldr x1, [fp, #0xB0] cmp x0, x1 bge G_M000_IG06 ldr w0, [fp, #0xA0] add w0, w0, #1 str w0, [fp, #0xA0] G_M000_IG06: ldr x0, [fp, #0x70] ldr x1, [fp, #0xB0] sub x0, x0, x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cmp x0, #1 ble G_M000_IG07 ldr w0, [fp, #0xA0] cmp w0, #3 bge G_M000_IG07 ldr x0, [fp, #0x70] str x0, [fp, #0xB0] b G_M000_IG03 G_M000_IG07: ldr x0, [fp, #0xB8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 add x0, fp, #80 ldr x1, [fp, #0xB0] ldr x2, [fp, #0xA8] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x50] ldr x1, [fp, #0x58] G_M000_IG08: ldp fp, lr, [sp], #0xC0 ret lr ; Total bytes of code 628 887: JIT compiled BenchmarkDotNet.Engines.EnginePilotStage:RunSpecific() [Tier0, IL size=141, code size=628] ; Assembly listing for method BenchmarkDotNet.Engines.EnginePilotStage:Autocorrect(long):long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] ldr w1, [x1, #0x28] sxtw x1, w1 add x0, x0, x1 sub x0, x0, #1 ldr x1, [fp, #0x18] ldr w1, [x1, #0x28] sxtw x1, w1 cmp x1, #0 beq G_M000_IG06 cmn x1, #1 bne G_M000_IG03 cmp x0, #1 bvs G_M000_IG05 G_M000_IG03: sdiv x0, x0, x1 ldr x1, [fp, #0x18] ldr w1, [x1, #0x28] sxtw x1, w1 mul x0, x0, x1 G_M000_IG04: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG05: bl CORINFO_HELP_OVERFLOW G_M000_IG06: bl CORINFO_HELP_THROWDIVZERO brk_windows #0 ; Total bytes of code 116 888: JIT compiled BenchmarkDotNet.Engines.EnginePilotStage:Autocorrect(long) [Tier0, IL size=29, code size=116] ; Assembly listing for method BenchmarkDotNet.Engines.EngineStage:RunIteration(int,int,int,long,int):BenchmarkDotNet.Reports.Measurement:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x100]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] stp q16, q16, [x9, #0x80] stp xzr, xzr, [x9, #0xA0] str xzr, [x9, #0xB0] str x0, [fp, #0xF8] str w1, [fp, #0xEC] str w2, [fp, #0xE8] str w3, [fp, #0xE4] str x4, [fp, #0xD8] str w5, [fp, #0xD4] str x8, [fp, #0xF0] G_M000_IG02: ldr x0, [fp, #0xD8] str x0, [fp, #0x70] ldr w0, [fp, #0xD4] sxtw x0, w0 str x0, [fp, #0x68] ldr x0, [fp, #0x70] ldr x1, [fp, #0x68] cmp x1, #0 beq G_M000_IG08 cmn x1, #1 bne G_M000_IG03 cmp x0, #1 bvs G_M000_IG07 G_M000_IG03: sdiv x0, x0, x1 ldr x1, [fp, #0x68] mul x0, x0, x1 ldr x1, [fp, #0x70] sub x0, x1, x0 cbz x0, G_M000_IG05 G_M000_IG04: add x0, fp, #168 mov w1, #53 mov w2, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x60] ldr x1, [fp, #0x60] add x0, fp, #168 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #168 ldr x1, [fp, #0xD8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x58] ldr x1, [fp, #0x58] add x0, fp, #168 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #168 ldr w1, [fp, #0xD4] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x50] ldr x1, [fp, #0x50] add x0, fp, #168 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x78] add x0, fp, #168 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x48] ldr x1, [fp, #0x48] ldr x0, [fp, #0x78] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x78] bl CORINFO_HELP_THROW G_M000_IG05: stp xzr, xzr, [fp, #0x88] stp xzr, xzr, [fp, #0x98] ldr x0, [fp, #0xF8] ldr x0, [x0, #0x08] str x0, [fp, #0x80] add x0, fp, #136 ldr w1, [fp, #0xEC] ldr w2, [fp, #0xE8] ldr w3, [fp, #0xE4] ldr x4, [fp, #0xD8] ldr w5, [fp, #0xD4] movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x0, [fp, #0x80] str x0, [fp, #0x20] ldr x0, [fp, #0xF0] str x0, [fp, #0x18] ldp x0, x1, [fp, #0x88] stp x0, x1, [fp, #0x28] ldp x0, x1, [fp, #0x98] stp x0, x1, [fp, #0x38] ldr x0, [fp, #0x20] add x1, fp, #40 ldr x8, [fp, #0x18] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 G_M000_IG06: ldp fp, lr, [sp], #0xD1FFAB1E ret lr G_M000_IG07: bl CORINFO_HELP_OVERFLOW G_M000_IG08: bl CORINFO_HELP_THROWDIVZERO brk_windows #0 ; Total bytes of code 624 889: JIT compiled BenchmarkDotNet.Engines.EngineStage:RunIteration(int,int,int,long,int) [Tier0, IL size=109, code size=624] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:WorkloadPilotStart(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x2, [fp, #0x10] mov w1, #7 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 890: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:WorkloadPilotStart(long) [Tier0, IL size=9, code size=56] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:WorkloadPilotStop(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x2, [fp, #0x10] mov w1, #8 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 891: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:WorkloadPilotStop(long) [Tier0, IL size=9, code size=56] ; Assembly listing for method System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:AddWithResize(BenchmarkDotNet.Reports.Measurement):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x1, [fp, #0x28] ldr w1, [x1, #0x10] str w1, [fp, #0x1C] ldr w1, [fp, #0x1C] add w1, w1, #1 ldr x0, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [fp, #0x1C] add w0, w0, #1 ldr x1, [fp, #0x28] str w0, [x1, #0x10] ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] ldr w1, [fp, #0x1C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG04 add x0, x0, x1, LSL #5 add x0, x0, #16 ldr x1, [fp, #0x20] ldp q16, q17, [x1] stp q16, q17, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 136 892: JIT compiled System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:AddWithResize(BenchmarkDotNet.Reports.Measurement) [Tier0, IL size=39, code size=136] ; Assembly listing for method System.Reflection.Associates:IncludeAccessor(System.Reflection.MethodInfo,bool):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 42912 ; 1 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! str x19, [sp, #0x18] mov fp, sp G_M000_IG02: cbz x0, G_M000_IG09 G_M000_IG03: tst w1, #255 beq G_M000_IG06 G_M000_IG04: mov w0, #1 G_M000_IG05: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG06: ldr x1, [x0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 cmp x1, x2 bne G_M000_IG11 ldr w19, [x0, #0x5C] G_M000_IG07: and w0, w19, #7 cmp w0, #6 cset x0, eq G_M000_IG08: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG09: mov w0, wzr G_M000_IG10: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG11: ldr x1, [x0] ldr x1, [x1, #0x50] ldr x1, [x1, #0x20] blr x1 mov w19, w0 b G_M000_IG07 ; Total bytes of code 132 893: JIT compiled System.Reflection.Associates:IncludeAccessor(System.Reflection.MethodInfo,bool) [Tier1 with Static PGO, IL size=22, code size=132] ; Assembly listing for method System.Reflection.RuntimeMethodInfo:InvokeOneParameter(System.Object,int,System.Reflection.Binder,System.Object,System.Globalization.CultureInfo):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 853 ; 10 inlinees with PGO data; 8 single block inlinees; 0 inlinees without PGO data G_M000_IG01: sub sp, sp, #208 stp fp, lr, [sp, #0x20] stp x19, x20, [sp, #0x88] stp x21, x22, [sp, #0x98] stp x23, x24, [sp, #0xA8] stp x25, x26, [sp, #0xB8] str x27, [sp, #0xC8] add fp, sp, #32 add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] str xzr, [x9, #0x40] str x4, [fp, #0x60] mov x19, x0 mov x21, x1 mov w20, w2 mov x22, x3 mov x23, x5 G_M000_IG02: ldr x0, [x19, #0x48] cbz x0, G_M000_IG18 G_M000_IG03: ldr x0, [x19, #0x48] ldr w24, [x0, #0x20] tbz w24, #0, G_M000_IG14 G_M000_IG04: mov w0, #0xD1FFAB1E tst w24, w0 bne G_M000_IG25 G_M000_IG05: mov x0, x19 mov x1, x21 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x1, [x19, #0x30] cbz x1, G_M000_IG13 G_M000_IG06: ldr x0, [x1, #0x08] ldr w0, [x0, #0x08] cmp w0, #1 bne G_M000_IG26 stp xzr, xzr, [fp, #0x38] stp xzr, xzr, [fp, #0x48] str xzr, [fp, #0x58] add x24, fp, #56 add x25, fp, #96 add x26, fp, #88 stp xzr, xzr, [fp, #0x18] stp xzr, xzr, [fp, #0x28] add x27, fp, #24 ldr x1, [x19, #0x30] cbz x1, G_M000_IG12 G_M000_IG07: ldr x6, [x1, #0x08] str x6, [sp] str x22, [sp, #0x08] str x23, [sp, #0x10] str w20, [sp, #0x18] mov x6, x25 mov w7, #1 mov x1, x24 mov w2, #1 mov x4, x26 mov w5, #1 mov x0, x19 mov x3, x27 movz x8, #0xD1FFAB1E movk x8, #0xD1FFAB1E LSL #16 movk x8, #0xD1FFAB1E LSL #32 ldr x8, [x8] blr x8 ldr x0, [x19, #0x48] cbz x0, G_M000_IG16 G_M000_IG08: ldr x0, [x19, #0x48] ldr x1, [x0, #0x18] cbz x1, G_M000_IG10 G_M000_IG09: tbnz w20, #25, G_M000_IG27 G_M000_IG10: mov x1, x21 mov x2, x27 mov w3, w20 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG11: ldr x27, [sp, #0xC8] ldp x25, x26, [sp, #0xB8] ldp x23, x24, [sp, #0xA8] ldp x21, x22, [sp, #0x98] ldp x19, x20, [sp, #0x88] ldp fp, lr, [sp, #0x20] add sp, sp, #208 ret lr G_M000_IG12: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x1, x0 b G_M000_IG07 G_M000_IG13: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x1, x0 b G_M000_IG06 G_M000_IG14: ldr x0, [x19, #0x48] cbz x0, G_M000_IG22 G_M000_IG15: mov x0, x19 ldr x0, [x0, #0x48] ldrsb wzr, [x0] add x1, x0, #32 mov x0, x19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 mov w24, w0 b G_M000_IG04 G_M000_IG16: ldr x24, [x19, #0x30] cbz x24, G_M000_IG21 G_M000_IG17: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x22, x0 mov x1, x19 mov x2, x24 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x14, x19, #72 mov x15, x22 bl CORINFO_HELP_ASSIGN_REF b G_M000_IG08 G_M000_IG18: ldr x24, [x19, #0x30] cbz x24, G_M000_IG20 G_M000_IG19: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x25, x0 mov x1, x19 mov x2, x24 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x14, x19, #72 mov x15, x25 bl CORINFO_HELP_ASSIGN_REF b G_M000_IG03 G_M000_IG20: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x24, x0 b G_M000_IG19 G_M000_IG21: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x24, x0 b G_M000_IG17 G_M000_IG22: ldr x27, [x19, #0x30] cbz x27, G_M000_IG24 G_M000_IG23: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x24, x0 mov x1, x19 mov x2, x27 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x14, x19, #72 mov x15, x24 bl CORINFO_HELP_ASSIGN_REF b G_M000_IG15 G_M000_IG24: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x27, x0 b G_M000_IG23 G_M000_IG25: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 b G_M000_IG05 G_M000_IG26: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x21, x0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 mov x1, x0 mov x0, x21 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 mov x0, x21 bl CORINFO_HELP_THROW G_M000_IG27: ldr x3, [x0, #0x18] ldr x0, [x3, #0x08] mov x1, x21 mov x2, x27 ldr x3, [x3, #0x18] blr x3 b G_M000_IG11 ; Total bytes of code 928 894: JIT compiled System.Reflection.RuntimeMethodInfo:InvokeOneParameter(System.Object,int,System.Reflection.Binder,System.Object,System.Globalization.CultureInfo) [Tier1 with Static PGO, IL size=156, code size=928] ; Assembly listing for method System.Reflection.MethodBase:ValidateInvokeTarget(System.Object):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 18964 ; 2 inlinees with PGO data; 5 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x10] stp x21, x22, [sp, #0x20] mov fp, sp mov x19, x0 mov x20, x1 G_M000_IG02: ldr x21, [x19] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 cmp x21, x0 bne G_M000_IG09 G_M000_IG03: ldr w22, [x19, #0x5C] G_M000_IG04: tbnz w22, #4, G_M000_IG08 G_M000_IG05: cbz x20, G_M000_IG14 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 cmp x21, x0 bne G_M000_IG11 mov x0, x19 ldr x0, [x0, #0x08] ldrb w0, [x0, #0x94] cbnz w0, G_M000_IG10 ldr x0, [x19, #0x38] G_M000_IG06: ldr x1, [x0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 cmp x1, x2 bne G_M000_IG12 mov x1, x20 bl System.RuntimeTypeHandle:IsInstanceOfType(System.RuntimeType,System.Object):bool G_M000_IG07: cbz w0, G_M000_IG13 G_M000_IG08: ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG09: mov x0, x19 ldr x1, [x21, #0x50] ldr x1, [x1, #0x20] blr x1 mov w22, w0 b G_M000_IG04 G_M000_IG10: mov x0, xzr b G_M000_IG06 G_M000_IG11: mov x0, x19 ldr x1, [x21, #0x40] ldr x1, [x1, #0x38] blr x1 G_M000_IG12: mov x1, x20 ldr x2, [x0] ldr x2, [x2, #0xA0] ldr x2, [x2, #0x08] blr x2 b G_M000_IG07 G_M000_IG13: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 mov x1, x0 mov x0, x19 mov x2, xzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x19 bl CORINFO_HELP_THROW G_M000_IG14: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 mov x1, x0 mov x0, x19 mov x2, xzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x19 bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 388 895: JIT compiled System.Reflection.MethodBase:ValidateInvokeTarget(System.Object) [Tier1 with Static PGO, IL size=48, code size=388] ; Assembly listing for method System.Reflection.MethodBase:CheckArguments(System.Span`1[System.Object],ulong,System.Span`1[ubyte],System.ReadOnlySpan`1[System.Object],System.RuntimeType[],System.Reflection.Binder,System.Globalization.CultureInfo,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 35429 ; 2 inlinees with PGO data; 6 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0xD0]! stp x19, x20, [sp, #0x80] stp x21, x22, [sp, #0x90] stp x23, x24, [sp, #0xA0] stp x25, x26, [sp, #0xB0] stp x27, x28, [sp, #0xC0] mov fp, sp str xzr, [fp, #0x60] mov x26, x0 mov x21, x1 mov w24, w2 mov x20, x3 mov x22, x4 mov w25, w5 mov x23, x6 mov w19, w7 ldr x27, [fp, #0xD0] ldr x28, [fp, #0xD8] G_M000_IG02: str xzr, [fp, #0x40] mov w4, wzr cmp w19, #0 ble G_M000_IG17 G_M000_IG03: cbz x27, G_M000_IG18 ldr w0, [x27, #0x08] cmp w0, w19 blt G_M000_IG18 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x5, [x0] G_M000_IG04: str wzr, [fp, #0x70] str w4, [fp, #0x7C] mov w6, w4 str x6, [fp, #0x48] lsl x7, x6, #3 str x7, [fp, #0x58] ldr x0, [x23, x7] str x0, [fp, #0x60] add x0, x27, #16 ldr x8, [x0, x7] ldr x0, [fp, #0x60] str x5, [fp, #0x18] cmp x0, x5 beq G_M000_IG35 G_M000_IG05: ldr x0, [fp, #0x60] cbz x0, G_M000_IG26 G_M000_IG06: str x8, [fp, #0x38] ldr x0, [fp, #0x60] bl System.Object:GetType():System.Type:this ldr x1, [fp, #0x38] cmp x0, x1 bne G_M000_IG08 G_M000_IG07: bl System.RuntimeTypeHandle:IsValueType(System.RuntimeType):bool mov w1, w0 b G_M000_IG10 G_M000_IG08: ldrsb wzr, [x1] str x1, [fp, #0x38] mov x0, x1 bl System.RuntimeTypeHandle:GetCorElementType(System.RuntimeType):ubyte cmp w0, #16 beq G_M000_IG39 G_M000_IG09: add x2, fp, #112 add x1, fp, #96 ldr x0, [fp, #0x38] mov x3, x28 ldr x4, [fp, #0xE0] ldr w5, [fp, #0xE8] movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] ldr wzr, [x0] blr x6 mov w1, w0 G_M000_IG10: ldr w2, [fp, #0x7C] cmp w2, w25 bhs G_M000_IG42 ldr w14, [fp, #0x70] ldr x3, [fp, #0x48] strb w14, [x22, x3] cmp w2, w24 bhs G_M000_IG42 ldr x4, [fp, #0x58] add x3, x21, x4 ldr x15, [fp, #0x60] mov x14, x3 bl CORINFO_HELP_CHECKED_ASSIGN_REF cbnz w1, G_M000_IG14 G_M000_IG11: str x3, [x20, w2, SXTW #3] G_M000_IG12: add w2, w2, #1 cmp w2, w19 mov w4, w2 ldr x5, [fp, #0x18] blt G_M000_IG04 G_M000_IG13: b G_M000_IG17 G_M000_IG14: ldr x4, [x21, x4] ldrsb wzr, [x4] add x5, x4, #8 str x5, [x20, w2, SXTW #3] b G_M000_IG12 G_M000_IG15: mov x3, x0 str x3, [x20, w2, SXTW #3] G_M000_IG16: add w2, w2, #1 cmp w2, w19 mov w4, w2 blt G_M000_IG18 G_M000_IG17: ldp x27, x28, [sp, #0xC0] ldp x25, x26, [sp, #0xB0] ldp x23, x24, [sp, #0xA0] ldp x21, x22, [sp, #0x90] ldp x19, x20, [sp, #0x80] ldp fp, lr, [sp], #0xD0 ret lr G_M000_IG18: str wzr, [fp, #0x70] cmp w4, w19 bhs G_M000_IG42 ubfiz x6, x4, #3, #32 str x6, [fp, #0x50] ldr x0, [x23, x6] str x0, [fp, #0x60] ldr w0, [x27, #0x08] str w4, [fp, #0x7C] cmp w4, w0 bhs G_M000_IG42 add x0, x27, #16 ldr x0, [x0, x6] mov x7, x0 ldr x0, [fp, #0x60] movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] cmp x0, x5 beq G_M000_IG30 G_M000_IG19: ldr x0, [fp, #0x60] cbz x0, G_M000_IG27 G_M000_IG20: str x7, [fp, #0x38] ldr x0, [fp, #0x60] bl System.Object:GetType():System.Type:this ldr x1, [fp, #0x38] cmp x0, x1 bne G_M000_IG22 G_M000_IG21: bl System.RuntimeTypeHandle:IsValueType(System.RuntimeType):bool mov w1, w0 b G_M000_IG24 G_M000_IG22: ldrsb wzr, [x1] str x1, [fp, #0x38] mov x0, x1 bl System.RuntimeTypeHandle:GetCorElementType(System.RuntimeType):ubyte cmp w0, #16 beq G_M000_IG40 G_M000_IG23: add x2, fp, #112 add x1, fp, #96 ldr x0, [fp, #0x38] mov x3, x28 ldr x4, [fp, #0xE0] ldr w5, [fp, #0xE8] movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] ldr wzr, [x0] blr x6 mov w1, w0 G_M000_IG24: ldr w2, [fp, #0x7C] cmp w2, w25 bhs G_M000_IG42 ldr w14, [fp, #0x70] strb w14, [x22, w2, UXTW #2] cmp w2, w24 bhs G_M000_IG42 ldr x3, [fp, #0x50] add x0, x21, x3 ldr x15, [fp, #0x60] mov x14, x0 bl CORINFO_HELP_CHECKED_ASSIGN_REF cbz w1, G_M000_IG15 G_M000_IG25: ldr x4, [x21, x3] ldrsb wzr, [x4] add x5, x4, #8 str x5, [x20, w2, SXTW #3] b G_M000_IG16 G_M000_IG26: str x8, [fp, #0x38] mov x0, x8 bl System.RuntimeTypeHandle:IsValueType(System.RuntimeType):bool mov w1, w0 str w1, [fp, #0x6C] cbnz w1, G_M000_IG09 ldr x0, [fp, #0x38] bl System.RuntimeTypeHandle:GetCorElementType(System.RuntimeType):ubyte cmp w0, #16 beq G_M000_IG09 ldr w1, [fp, #0x6C] b G_M000_IG10 G_M000_IG27: str x7, [fp, #0x38] mov x0, x7 bl System.RuntimeTypeHandle:IsValueType(System.RuntimeType):bool mov w1, w0 str w1, [fp, #0x6C] cbnz w1, G_M000_IG23 ldr x0, [fp, #0x38] bl System.RuntimeTypeHandle:GetCorElementType(System.RuntimeType):ubyte cmp w0, #16 ldr w1, [fp, #0x6C] bne G_M000_IG24 G_M000_IG28: ldr x0, [fp, #0x38] str x0, [fp, #0x38] b G_M000_IG23 G_M000_IG29: mov w0, #1 str w0, [fp, #0x70] ldr w1, [fp, #0x6C] b G_M000_IG10 G_M000_IG30: str x7, [fp, #0x38] ldr x3, [fp, #0x40] cbnz x3, G_M000_IG31 mov x0, x26 ldr x3, [x26] ldr x3, [x3, #0x50] ldr x3, [x3, #0x10] blr x3 mov x1, x0 mov x3, x1 G_M000_IG31: ldr w0, [x3, #0x08] ldr w4, [fp, #0x7C] cmp w4, w0 bhs G_M000_IG42 str x3, [fp, #0x40] add x0, x3, #16 ldr x6, [fp, #0x50] ldr x0, [x0, x6] mov x5, x0 str x5, [fp, #0x30] ldr x8, [x5] ldr x8, [x8, #0x48] ldr x8, [x8, #0x08] blr x8 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] cmp x0, x1 beq G_M000_IG34 ldr x0, [fp, #0x30] ldr x1, [x0] ldr x1, [x1, #0x48] ldr x1, [x1, #0x08] blr x1 str x0, [fp, #0x60] ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbz w0, G_M000_IG33 mov w0, #2 str w0, [fp, #0x70] ldr x0, [fp, #0x60] ldr x7, [fp, #0x38] cbz x0, G_M000_IG19 str x7, [fp, #0x38] mov x0, x7 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 ldr w1, [x0, #0x08] cmp w1, #0 bls G_M000_IG42 ldr x9, [x0, #0x10] mov x1, x9 mov x0, x1 str x1, [fp, #0x28] ldr x2, [x1] ldr x2, [x2, #0x70] ldr x2, [x2, #0x30] blr x2 cbz w0, G_M000_IG32 ldr x0, [fp, #0x28] ldr x1, [fp, #0x60] movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 str x0, [fp, #0x60] ldr x7, [fp, #0x38] b G_M000_IG19 G_M000_IG32: ldr x7, [fp, #0x38] b G_M000_IG19 G_M000_IG33: mov w0, #1 str w0, [fp, #0x70] ldr x7, [fp, #0x38] b G_M000_IG19 G_M000_IG34: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 mov x20, x0 movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov x2, x0 mov x1, x20 mov x0, x19 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x19 bl CORINFO_HELP_THROW G_M000_IG35: str x8, [fp, #0x38] ldr x3, [fp, #0x40] cbnz x3, G_M000_IG36 mov x0, x26 ldr x3, [x26] ldr x3, [x3, #0x50] ldr x3, [x3, #0x10] blr x3 mov x1, x0 mov x3, x1 G_M000_IG36: ldr w0, [x3, #0x08] ldr w4, [fp, #0x7C] cmp w4, w0 bhs G_M000_IG42 str x3, [fp, #0x40] add x0, x3, #16 ldr x7, [fp, #0x58] ldr x9, [x0, x7] mov x0, x9 str x9, [fp, #0x30] ldr x10, [x9] ldr x10, [x10, #0x48] ldr x10, [x10, #0x08] blr x10 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] cmp x0, x1 beq G_M000_IG34 ldr x0, [fp, #0x30] ldr x1, [x0] ldr x1, [x1, #0x48] ldr x1, [x1, #0x08] blr x1 str x0, [fp, #0x60] ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbz w0, G_M000_IG38 mov w0, #2 str w0, [fp, #0x70] ldr x0, [fp, #0x60] ldr x8, [fp, #0x38] cbz x0, G_M000_IG05 str x8, [fp, #0x38] mov x0, x8 movz x9, #0xD1FFAB1E movk x9, #0xD1FFAB1E LSL #16 movk x9, #0xD1FFAB1E LSL #32 ldr x9, [x9] blr x9 ldr w1, [x0, #0x08] cmp w1, #0 bls G_M000_IG42 ldr x1, [x0, #0x10] mov x0, x1 str x1, [fp, #0x28] ldr x2, [x1] ldr x2, [x2, #0x70] ldr x2, [x2, #0x30] blr x2 cbz w0, G_M000_IG37 ldr x9, [fp, #0x28] mov x0, x9 ldr x1, [fp, #0x60] movz x9, #0xD1FFAB1E movk x9, #0xD1FFAB1E LSL #16 movk x9, #0xD1FFAB1E LSL #32 ldr x9, [x9] blr x9 str x0, [fp, #0x60] ldr x8, [fp, #0x38] b G_M000_IG05 G_M000_IG37: ldr x8, [fp, #0x38] b G_M000_IG05 G_M000_IG38: mov w0, #1 str w0, [fp, #0x70] ldr x8, [fp, #0x38] b G_M000_IG05 G_M000_IG39: ldr x0, [fp, #0x38] bl System.RuntimeTypeHandle:GetElementType(System.RuntimeType):System.RuntimeType str x0, [fp, #0x20] ldr x0, [fp, #0x60] bl System.Object:GetType():System.Type:this ldr x1, [fp, #0x20] cmp x0, x1 bne G_M000_IG09 str x1, [fp, #0x20] mov x0, x1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 mov w2, w0 str w2, [fp, #0x6C] cbz w2, G_M000_IG29 ldr x0, [fp, #0x20] ldr x1, [fp, #0x60] bl System.RuntimeType:AllocateValueType(System.RuntimeType,System.Object):System.Object str x0, [fp, #0x60] b G_M000_IG29 G_M000_IG40: ldr x0, [fp, #0x38] bl System.RuntimeTypeHandle:GetElementType(System.RuntimeType):System.RuntimeType str x0, [fp, #0x20] ldr x0, [fp, #0x60] bl System.Object:GetType():System.Type:this ldr x1, [fp, #0x20] cmp x0, x1 bne G_M000_IG23 str x1, [fp, #0x20] mov x0, x1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 mov w2, w0 str w2, [fp, #0x6C] cbz w2, G_M000_IG41 ldr x0, [fp, #0x20] ldr x1, [fp, #0x60] bl System.RuntimeType:AllocateValueType(System.RuntimeType,System.Object):System.Object str x0, [fp, #0x60] G_M000_IG41: mov w0, #1 str w0, [fp, #0x70] ldr w1, [fp, #0x6C] b G_M000_IG24 G_M000_IG42: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 1840 896: JIT compiled System.Reflection.MethodBase:CheckArguments(System.Span`1[System.Object],ulong,System.Span`1[ubyte],System.ReadOnlySpan`1[System.Object],System.RuntimeType[],System.Reflection.Binder,System.Globalization.CultureInfo,int) [Tier1 with Static PGO, IL size=366, code size=1840] ; Assembly listing for method System.Reflection.MethodInvoker:Invoke(System.Object,ulong,int):System.Object:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; PGO data available, but IL did not match ; 0 inlinees with PGO data; 4 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x40]! stp x19, x20, [sp, #0x20] stp x21, x22, [sp, #0x30] mov fp, sp add x4, sp, #64 str x4, [fp, #0x18] mov x19, x0 mov x20, x1 mov x21, x2 mov w22, w3 G_M000_IG02: ldrb w0, [x19, #0x25] cbnz w0, G_M000_IG05 G_M000_IG03: ldrb w0, [x19, #0x24] cbnz w0, G_M000_IG04 mov w0, #1 strb w0, [x19, #0x24] b G_M000_IG05 G_M000_IG04: ldr x0, [x19, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 add x14, x19, #24 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF mov w0, #1 strb w0, [x19, #0x25] G_M000_IG05: tbnz w22, #25, G_M000_IG08 G_M000_IG06: ldr x22, [x19, #0x18] cbz x22, G_M000_IG07 ldr x0, [x22, #0x08] mov x1, x20 mov x2, x21 ldr x3, [x22, #0x18] blr x3 b G_M000_IG10 G_M000_IG07: ldr x2, [x19, #0x08] mov x0, x20 mov x1, x21 mov w3, wzr bl System.RuntimeMethodHandle:InvokeMethod(System.Object,ulong,System.Signature,bool):System.Object b G_M000_IG10 G_M000_IG08: ldr x22, [x19, #0x18] cbz x22, G_M000_IG09 ldr x0, [x22, #0x08] mov x1, x20 mov x2, x21 ldr x3, [x22, #0x18] blr x3 b G_M000_IG10 G_M000_IG09: ldr x2, [x19, #0x08] mov x0, x20 mov x1, x21 mov w3, wzr bl System.RuntimeMethodHandle:InvokeMethod(System.Object,ulong,System.Signature,bool):System.Object G_M000_IG10: ldp x21, x22, [sp, #0x30] ldp x19, x20, [sp, #0x20] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG11: stp fp, lr, [sp, #-0x40]! stp x19, x20, [sp, #0x20] stp x21, x22, [sp, #0x30] add x3, fp, #64 str x3, [sp, #0x18] G_M000_IG12: mov x19, x0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x20, x0 mov x1, x19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 mov x0, x20 bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 320 897: JIT compiled System.Reflection.MethodInvoker:Invoke(System.Object,ulong,int) [Tier1, IL size=143, code size=320] ; Assembly listing for method System.Reflection.Invoke+MyClass:set_O(System.Object):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: add x14, x0, #24 mov x15, x1 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 28 898: JIT compiled System.Reflection.Invoke+MyClass:set_O(System.Object) [Tier1, IL size=8, code size=28] ; Assembly listing for method System.Reflection.PropertyInfo:SetValue(System.Object,System.Object):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 13 ; 1 inlinees with PGO data; 0 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr x3, [x0] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 cmp x3, x4 bne G_M000_IG05 G_M000_IG03: mov w3, #60 mov x4, xzr mov x5, xzr mov x6, xzr movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] G_M000_IG04: ldp fp, lr, [sp], #0x10 br x7 G_M000_IG05: mov x3, xzr ldr x4, [x0] ldr x4, [x4, #0x60] ldr x4, [x4, #0x18] G_M000_IG06: ldp fp, lr, [sp], #0x10 br x4 ; Total bytes of code 96 899: JIT compiled System.Reflection.PropertyInfo:SetValue(System.Object,System.Object) [Tier1 with Static PGO, IL size=10, code size=96] ; Assembly listing for method System.Reflection.RuntimePropertyInfo:SetValue(System.Object,System.Object,int,System.Reflection.Binder,System.Object[],System.Globalization.CultureInfo):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 853 ; 3 inlinees with PGO data; 0 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x50]! stp x19, x20, [sp, #0x10] stp x21, x22, [sp, #0x20] stp x23, x24, [sp, #0x30] stp x25, x26, [sp, #0x40] mov fp, sp mov x20, x1 mov x21, x2 mov w24, w3 mov x22, x4 mov x19, x5 mov x23, x6 G_M000_IG02: ldr x25, [x0, #0x20] cbz x25, G_M000_IG05 mov x26, x25 G_M000_IG03: cbz x26, G_M000_IG10 cbnz x19, G_M000_IG06 mov x0, x26 mov x1, x20 mov w2, w24 mov x3, x22 mov x4, x21 mov x5, x23 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 G_M000_IG04: ldp x25, x26, [sp, #0x40] ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x50 ret lr G_M000_IG05: mov x26, xzr b G_M000_IG03 G_M000_IG06: ldr w1, [x19, #0x08] add w1, w1, #1 sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_OBJ mov x4, x0 mov w0, wzr b G_M000_IG08 G_M000_IG07: add x14, x19, #16 ldr x15, [x14, w0, UXTW #3] ldr w14, [x4, #0x08] cmp w0, w14 bhs G_M000_IG11 add x14, x4, #16 add x14, x14, x0, LSL #3 bl CORINFO_HELP_ASSIGN_REF add w0, w0, #1 G_M000_IG08: ldr w14, [x19, #0x08] cmp w14, w0 bgt G_M000_IG07 ldr w14, [x19, #0x08] ldr w15, [x4, #0x08] cmp w14, w15 bhs G_M000_IG11 ldr w14, [x19, #0x08] add x15, x4, #16 add x14, x15, x14, LSL #3 mov x15, x21 bl CORINFO_HELP_ASSIGN_REF mov x0, x26 mov x1, x20 mov w2, w24 mov x3, x22 mov x5, x23 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 G_M000_IG09: ldp x25, x26, [sp, #0x40] ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x50 ret lr G_M000_IG10: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 mov x1, x0 mov x0, x19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 mov x0, x19 bl CORINFO_HELP_THROW G_M000_IG11: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 416 900: JIT compiled System.Reflection.RuntimePropertyInfo:SetValue(System.Object,System.Object,int,System.Reflection.Binder,System.Object[],System.Globalization.CultureInfo) [Tier1 with Static PGO, IL size=103, code size=416] ; Assembly listing for method System.Reflection.Invoke:Property_Set_class():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 2 inlinees with PGO data; 0 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x18] str x21, [sp, #0x28] mov fp, sp G_M000_IG02: mov w19, wzr movz x20, #0xD1FFAB1E movk x20, #0xD1FFAB1E LSL #16 movk x20, #0xD1FFAB1E LSL #32 movz x21, #0xD1FFAB1E movk x21, #0xD1FFAB1E LSL #16 movk x21, #0xD1FFAB1E LSL #32 G_M000_IG03: ldr x0, [x20] ldr x1, [x20, #-0x60] ldr x2, [x0] cmp x2, x21 bne G_M000_IG07 G_M000_IG04: mov x2, xzr mov w3, #60 mov x4, xzr mov x5, xzr mov x6, xzr movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 G_M000_IG05: add w19, w19, #1 cmp w19, #0xD1FFAB1E blt G_M000_IG03 G_M000_IG06: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG07: mov x2, xzr mov x3, xzr ldr x4, [x0] ldr x4, [x4, #0x60] ldr x4, [x4, #0x18] blr x4 b G_M000_IG05 ; Total bytes of code 160 901: JIT compiled System.Reflection.Invoke:Property_Set_class() [Tier1, IL size=33, code size=160] ; Assembly listing for method System.Buffer:Memmove(byref,byref,ulong) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 1254090 ; 0 inlinees with PGO data; 2 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! stp x19, x20, [sp, #0x10] mov fp, sp G_M000_IG02: sub x3, x0, x1 sub x4, x1, x0 cmp x3, x2 ccmp x4, x2, 0, hs blo G_M000_IG21 G_M000_IG03: add x19, x1, x2 add x20, x0, x2 cmp x2, #16 bls G_M000_IG13 G_M000_IG04: cmp x2, #64 bhi G_M000_IG09 G_M000_IG05: ldr q16, [x1] str q16, [x0] cmp x2, #32 bls G_M000_IG07 G_M000_IG06: ldr q16, [x1, #0x10] str q16, [x0, #0x10] cmp x2, #48 bhi G_M000_IG20 G_M000_IG07: ldr q16, [x19, #-0x10] str q16, [x20, #-0x10] G_M000_IG08: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG09: lsr x3, x2, #6 G_M000_IG10: ldp q16, q17, [x1] stp q16, q17, [x0] ldp q16, q17, [x1, #0x20] stp q16, q17, [x0, #0x20] add x0, x0, #64 add x1, x1, #64 sub x3, x3, #1 cbnz x3, G_M000_IG10 G_M000_IG11: and x2, x2, #63 cmp x2, #16 bhi G_M000_IG05 G_M000_IG12: b G_M000_IG07 G_M000_IG13: tst w2, #24 bne G_M000_IG18 G_M000_IG14: tbnz w2, #2, G_M000_IG19 G_M000_IG15: cbz x2, G_M000_IG08 G_M000_IG16: ldrb w1, [x1] strb w1, [x0] tbz w2, #1, G_M000_IG08 G_M000_IG17: ldrsh w2, [x19, #-0x02] strh w2, [x20, #-0x02] b G_M000_IG08 G_M000_IG18: ldr x1, [x1] str x1, [x0] ldr x0, [x19, #-0x08] str x0, [x20, #-0x08] b G_M000_IG08 G_M000_IG19: ldr w1, [x1] str w1, [x0] ldr w0, [x19, #-0x04] str w0, [x20, #-0x04] b G_M000_IG08 G_M000_IG20: ldr q16, [x1, #0x20] str q16, [x0, #0x20] b G_M000_IG07 G_M000_IG21: cmp x0, x1 beq G_M000_IG08 G_M000_IG22: movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG23: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 br x3 ; Total bytes of code 288 902: JIT compiled System.Buffer:Memmove(byref,byref,ulong) [Tier1 with Static PGO, IL size=479, code size=288] ; Assembly listing for method System.Text.StringBuilder:Append(System.String):System.Text.StringBuilder:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 220968 ; 2 inlinees with PGO data; 2 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x18] str x21, [sp, #0x28] mov fp, sp mov x19, x0 G_M000_IG02: cbz x1, G_M000_IG10 ldr w20, [x1, #0x08] add x1, x1, #12 cbz w20, G_M000_IG10 G_M000_IG03: ldr x2, [x19, #0x08] ldr w21, [x19, #0x18] add w0, w21, w20 ldr w3, [x2, #0x08] cmp w0, w3 bhi G_M000_IG09 G_M000_IG04: add x2, x2, #16 sbfiz x0, x21, #1, #32 add x0, x2, x0 cmp w20, #2 ble G_M000_IG07 G_M000_IG05: sxtw x2, w20 lsl x2, x2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG06: add w0, w21, w20 str w0, [x19, #0x18] b G_M000_IG10 G_M000_IG07: ldrh w2, [x1] strh w2, [x0] cmp w20, #2 bne G_M000_IG06 G_M000_IG08: ldrh w2, [x1, #0x02] strh w2, [x0, #0x02] b G_M000_IG06 G_M000_IG09: mov x0, x19 mov w2, w20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG10: mov x0, x19 G_M000_IG11: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 196 903: JIT compiled System.Text.StringBuilder:Append(System.String) [Tier1 with Static PGO, IL size=25, code size=196] ; Assembly listing for method System.Text.StringBuilder:Append(byref,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 331347 ; 1 inlinees with PGO data; 1 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x18] str x21, [sp, #0x28] mov fp, sp mov x20, x0 mov w19, w2 G_M000_IG02: cbz w19, G_M000_IG12 G_M000_IG03: ldr x2, [x20, #0x08] ldr w21, [x20, #0x18] add w0, w21, w19 ldr w3, [x2, #0x08] cmp w0, w3 bhi G_M000_IG10 G_M000_IG04: add x2, x2, #16 sbfiz x0, x21, #1, #32 add x0, x2, x0 cmp w19, #2 ble G_M000_IG08 G_M000_IG05: sxtw x2, w19 lsl x2, x2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG06: add w0, w21, w19 str w0, [x20, #0x18] G_M000_IG07: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG08: ldrh w2, [x1] strh w2, [x0] cmp w19, #2 bne G_M000_IG06 G_M000_IG09: ldrh w2, [x1, #0x02] strh w2, [x0, #0x02] b G_M000_IG06 G_M000_IG10: mov x0, x20 mov w2, w19 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG11: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 br x3 G_M000_IG12: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 208 904: JIT compiled System.Text.StringBuilder:Append(byref,int) [Tier1 with Static PGO, IL size=96, code size=208] ; Assembly listing for method System.UInt64:CreateTruncating[uint](uint):ulong ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 0 single block inlinees; 2 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, w0 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 905: JIT compiled System.UInt64:CreateTruncating[uint](uint) [Tier1, IL size=74, code size=20] ; Assembly listing for method System.UInt64:TryConvertFromTruncating[uint](uint,byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, w0 str x0, [x1] mov w0, #1 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 28 906: JIT compiled System.UInt64:TryConvertFromTruncating[uint](uint,byref) [Tier1, IL size=371, code size=28] ; Assembly listing for method System.Runtime.CompilerServices.CastHelpers:ChkCastClass(ulong,System.Object):System.Object ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 1750548 ; 1 inlinees with PGO data; 2 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: cbz x1, G_M000_IG04 G_M000_IG03: ldr x2, [x1] cmp x2, x0 bne G_M000_IG06 G_M000_IG04: mov x0, x1 G_M000_IG05: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG06: ldr x2, [x1] G_M000_IG07: ldr x2, [x2, #0x10] cmp x2, x0 beq G_M000_IG08 cbz x2, G_M000_IG09 ldr x2, [x2, #0x10] cmp x2, x0 beq G_M000_IG08 cbz x2, G_M000_IG09 ldr x2, [x2, #0x10] cmp x2, x0 beq G_M000_IG08 cbz x2, G_M000_IG09 ldr x2, [x2, #0x10] cmp x2, x0 beq G_M000_IG08 cbnz x2, G_M000_IG07 b G_M000_IG09 G_M000_IG08: b G_M000_IG11 G_M000_IG09: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] G_M000_IG10: ldp fp, lr, [sp], #0x10 br x2 G_M000_IG11: mov x0, x1 G_M000_IG12: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 148 907: JIT compiled System.Runtime.CompilerServices.CastHelpers:ChkCastClass(ulong,System.Object) [Tier1 with Static PGO, IL size=22, code size=148] ; Assembly listing for method System.Number+BigInteger:Compare(byref,byref):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 20 G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w2, [x0] ldr w3, [x1] sub w3, w2, w3 cbnz w3, G_M000_IG11 G_M000_IG03: cbz w2, G_M000_IG09 sub w3, w2, #1 tbnz w3, #31, G_M000_IG09 G_M000_IG04: add x0, x0, #4 G_M000_IG05: sbfiz x2, x3, #2, #32 ldr w4, [x0, x2] add x5, x1, #4 ldr w2, [x5, x2] sub x2, x4, w2, UXTW cbz x2, G_M000_IG08 G_M000_IG06: mov w0, #1 movn w1, #0 cmp x2, #0 csel w0, w0, w1, gt G_M000_IG07: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG08: sub w3, w3, #1 tbz w3, #31, G_M000_IG05 G_M000_IG09: mov w0, wzr G_M000_IG10: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG11: mov w0, w3 G_M000_IG12: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 120 908: JIT compiled System.Number+BigInteger:Compare(byref,byref) [Tier1 with Static PGO, IL size=97, code size=120] ; Assembly listing for method System.Number+BigInteger:HeuristicDivide(byref,byref):uint ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 12 G_M000_IG01: stp fp, lr, [sp, #-0x40]! stp x19, x20, [sp, #0x18] stp x21, x22, [sp, #0x28] str x23, [sp, #0x38] mov fp, sp mov x19, x0 G_M000_IG02: ldr w20, [x1] ldr w0, [x19] cmp w0, w20 blt G_M000_IG18 sub w0, w20, #1 add x21, x19, #4 sbfiz x0, x0, #2, #32 ldr w2, [x21, x0] add x22, x1, #4 ldr w0, [x22, x0] add w0, w0, #1 cmp w0, #0 beq G_M000_IG17 udiv w23, w2, w0 cbz w23, G_M000_IG07 G_M000_IG03: mov w0, wzr mov x2, xzr mov x3, xzr mov w4, w23 G_M000_IG04: sbfiz x5, x0, #2, #32 ldr w6, [x22, x5] madd x6, x6, x4, x3 lsr x3, x6, #32 ldr w7, [x21, x5] sub x6, x7, w6, UXTW sub x6, x6, x2 lsr x2, x6, #32 and x2, x2, #1 str w6, [x21, x5] add w0, w0, #1 cmp w0, w20 blt G_M000_IG04 G_M000_IG05: cmp w20, #0 ble G_M000_IG06 sub w0, w20, #1 ldr w0, [x21, w0, SXTW #2] cbz w0, G_M000_IG20 G_M000_IG06: str w20, [x19] G_M000_IG07: mov x0, x19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 tbz w0, #31, G_M000_IG14 G_M000_IG08: mov w0, w23 G_M000_IG09: ldr x23, [sp, #0x38] ldp x21, x22, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG10: mov w20, w0 G_M000_IG11: cmp w20, #0 ble G_M000_IG13 G_M000_IG12: sub w0, w20, #1 ldr w1, [x21, w0, SXTW #2] cbz w1, G_M000_IG10 G_M000_IG13: str w20, [x19] b G_M000_IG08 G_M000_IG14: add w23, w23, #1 mov w0, wzr mov x1, xzr G_M000_IG15: sbfiz x2, x0, #2, #32 ldr w3, [x21, x2] ldr w4, [x22, x2] sub x3, x3, w4, UXTW sub x3, x3, x1 lsr x1, x3, #32 and x1, x1, #1 str w3, [x21, x2] add w0, w0, #1 cmp w0, w20 blt G_M000_IG15 G_M000_IG16: b G_M000_IG11 G_M000_IG17: bl CORINFO_HELP_THROWDIVZERO G_M000_IG18: mov w0, wzr G_M000_IG19: ldr x23, [sp, #0x38] ldp x21, x22, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG20: sub w20, w20, #1 b G_M000_IG05 ; Total bytes of code 356 909: JIT compiled System.Number+BigInteger:HeuristicDivide(byref,byref) [Tier1 with Static PGO, IL size=363, code size=356] ; Assembly listing for method System.Runtime.CompilerServices.ConditionalWeakTable`2+Enumerator[System.__Canon,System.__Canon]:MoveNext():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 583 ; 2 inlinees with PGO data; 2 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x50]! str x19, [sp, #0x48] mov fp, sp str xzr, [fp, #0x28] add x1, sp, #80 str x1, [fp, #0x40] str x0, [fp, #0x38] str x0, [fp, #0x20] G_M000_IG02: ldr x19, [x0, #0x08] cbz x19, G_M000_IG19 ldr x1, [x19, #0x08] str x1, [fp, #0x18] str wzr, [fp, #0x30] G_M000_IG03: ldrb w2, [fp, #0x30] cbnz w2, G_M000_IG12 add x1, fp, #48 ldr x0, [fp, #0x18] bl System.Threading.Monitor:ReliableEnter(System.Object,byref) ldr x19, [x19, #0x10] dmb ishld cbz x19, G_M000_IG17 ldr x0, [fp, #0x20] ldp w2, w1, [x0, #0x10] cmp w1, w2 bge G_M000_IG17 G_M000_IG04: ldr w1, [x0, #0x14] add w1, w1, #1 str w1, [x0, #0x14] ldr x2, [x19, #0x18] ldr w3, [x2, #0x08] cmp w3, w1 ble G_M000_IG11 ldr w3, [x2, #0x08] cmp w1, w3 bhs G_M000_IG08 ubfiz x1, x1, #4, #32 add x1, x1, #16 ldr x1, [x2, x1] mov x0, x1 add x1, fp, #40 bl System.Runtime.DependentHandle:InternalGetTargetAndDependent(long,byref):System.Object cbz x0, G_M000_IG11 G_M000_IG05: mov x15, x0 ldr x0, [fp, #0x28] mov w14, #1 G_M000_IG06: str xzr, [fp, #0x28] cbz w14, G_M000_IG09 G_M000_IG07: ldr x19, [fp, #0x20] ldr x14, [x19] ldr x14, [x14, #0x30] ldr x14, [x14] ldr x14, [x14, #0x18] cbnz x14, G_M000_IG13 b G_M000_IG13 G_M000_IG08: bl CORINFO_HELP_RNGCHKFAIL G_M000_IG09: ldr x0, [fp, #0x20] ldp w14, w15, [x0, #0x10] cmp w15, w14 blt G_M000_IG04 G_M000_IG10: b G_M000_IG17 G_M000_IG11: mov x15, xzr mov x1, xzr mov w14, wzr mov x0, x1 b G_M000_IG06 G_M000_IG12: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 brk_windows #0 G_M000_IG13: add x1, x19, #24 mov x14, x1 bl CORINFO_HELP_CHECKED_ASSIGN_REF add x14, x1, #8 mov x15, x0 bl CORINFO_HELP_CHECKED_ASSIGN_REF G_M000_IG14: ldrb w0, [fp, #0x30] cbz w0, G_M000_IG15 ldr x0, [fp, #0x18] bl System.Threading.Monitor:Exit(System.Object) G_M000_IG15: mov w0, #1 G_M000_IG16: ldr x19, [sp, #0x48] ldp fp, lr, [sp], #0x50 ret lr G_M000_IG17: ldr x0, [fp, #0x40] bl G_M000_IG21 G_M000_IG18: nop G_M000_IG19: mov w0, wzr G_M000_IG20: ldr x19, [sp, #0x48] ldp fp, lr, [sp], #0x50 ret lr G_M000_IG21: stp fp, lr, [sp, #-0x20]! str x19, [sp, #0x18] add x3, fp, #80 str x3, [sp, #0x10] G_M000_IG22: ldrb w0, [fp, #0x30] cbz w0, G_M000_IG23 ldr x0, [fp, #0x18] bl System.Threading.Monitor:Exit(System.Object) G_M000_IG23: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 412 910: JIT compiled System.Runtime.CompilerServices.ConditionalWeakTable`2+Enumerator[System.__Canon,System.__Canon]:MoveNext() [Tier1 with Static PGO, IL size=124, code size=412] ; Assembly listing for method System.Number+BigInteger:Multiply10():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 8 ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w1, [x0] cbz w1, G_M000_IG06 mov w2, wzr mov x3, xzr add x4, x0, #4 G_M000_IG03: sbfiz x5, x2, #2, #32 ldr w6, [x4, x5] lsl x7, x6, #3 add x6, x7, x6, LSL #1 add x6, x6, x3 lsr x3, x6, #32 str w6, [x4, x5] add w2, w2, #1 cmp w2, w1 blt G_M000_IG03 G_M000_IG04: cbnz x3, G_M000_IG07 G_M000_IG05: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG06: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG07: str w3, [x4, w2, SXTW #2] ldr w1, [x0] add w1, w1, #1 str w1, [x0] b G_M000_IG05 ; Total bytes of code 108 911: JIT compiled System.Number+BigInteger:Multiply10() [Tier1 with Static PGO, IL size=122, code size=108] ; Assembly listing for method System.Runtime.CompilerServices.CastHelpers:IsInstanceOfClass(ulong,System.Object):System.Object ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 5012236 ; 0 inlinees with PGO data; 2 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: cbz x1, G_M000_IG04 G_M000_IG03: ldr x2, [x1] cmp x2, x0 bne G_M000_IG06 G_M000_IG04: mov x0, x1 G_M000_IG05: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG06: ldr x2, [x1] ldr x2, [x2, #0x10] G_M000_IG07: cmp x2, x0 beq G_M000_IG16 G_M000_IG08: cbz x2, G_M000_IG15 G_M000_IG09: ldr x2, [x2, #0x10] cmp x2, x0 beq G_M000_IG16 G_M000_IG10: cbz x2, G_M000_IG15 G_M000_IG11: ldr x2, [x2, #0x10] cmp x2, x0 beq G_M000_IG16 G_M000_IG12: cbz x2, G_M000_IG15 G_M000_IG13: ldr x2, [x2, #0x10] cmp x2, x0 beq G_M000_IG16 G_M000_IG14: cbnz x2, G_M000_IG18 G_M000_IG15: mov x1, xzr G_M000_IG16: mov x0, x1 G_M000_IG17: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG18: ldr x2, [x2, #0x10] b G_M000_IG07 ; Total bytes of code 128 912: JIT compiled System.Runtime.CompilerServices.CastHelpers:IsInstanceOfClass(ulong,System.Object) [Tier1 with Static PGO, IL size=97, code size=128] ; Assembly listing for method System.Char:System.IUtfChar.CastFrom(ushort):ushort ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: uxth w0, w0 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 913: JIT compiled System.Char:System.IUtfChar.CastFrom(ushort) [Tier1, IL size=2, code size=20] ; Assembly listing for method System.ArgumentOutOfRangeException:ThrowIfNegative[int](int,System.String) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp mov w2, w0 G_M000_IG02: tbnz w2, #31, G_M000_IG04 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG04: mov x0, x1 mov w1, w2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 brk_windows #0 ; Total bytes of code 56 914: JIT compiled System.ArgumentOutOfRangeException:ThrowIfNegative[int](int,System.String) [Tier1, IL size=22, code size=56] ; Assembly listing for method System.Int32:IsNegative(int):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: lsr w0, w0, #31 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 915: JIT compiled System.Int32:IsNegative(int) [Tier1, IL size=5, code size=20] ; Assembly listing for method BenchmarkDotNet.Engines.EngineStage:WriteLine():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 48 916: JIT compiled BenchmarkDotNet.Engines.EngineStage:WriteLine() [Tier0, IL size=12, code size=48] ; Assembly listing for method BenchmarkDotNet.Engines.EnginePilotStage+PilotStageResult:.ctor(long,System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x14, [fp, #0x28] ldr x15, [fp, #0x20] str x15, [x14, #0x08] ldr x14, [fp, #0x28] ldr x15, [fp, #0x18] bl CORINFO_HELP_CHECKED_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 52 917: JIT compiled BenchmarkDotNet.Engines.EnginePilotStage+PilotStageResult:.ctor(long,System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]) [Tier0, IL size=15, code size=52] ; Assembly listing for method BenchmarkDotNet.Engines.EnginePilotStage+PilotStageResult:get_PerfectInvocationCount():long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 918: JIT compiled BenchmarkDotNet.Engines.EnginePilotStage+PilotStageResult:get_PerfectInvocationCount() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EnginePilotStage+PilotStageResult:get_Measurements():System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Reports.Measurement]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 919: JIT compiled BenchmarkDotNet.Engines.EnginePilotStage+PilotStageResult:get_Measurements() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_EvaluateOverhead():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldrb w0, [x0, #0xB9] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 920: JIT compiled BenchmarkDotNet.Engines.Engine:get_EvaluateOverhead() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_UnrollFactor():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0xB0] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 921: JIT compiled BenchmarkDotNet.Engines.Engine:get_UnrollFactor() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.EngineWarmupStage:RunOverhead(long,int):System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Reports.Measurement]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] G_M000_IG02: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] ldr w3, [fp, #0x1C] mov w2, wzr mov w4, wzr movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 68 922: JIT compiled BenchmarkDotNet.Engines.EngineWarmupStage:RunOverhead(long,int) [Tier0, IL size=11, code size=68] ; Assembly listing for method BenchmarkDotNet.Engines.EngineWarmupStage:Run(long,int,int,int):System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Reports.Measurement]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x48] str x1, [fp, #0x40] str w2, [fp, #0x3C] str w3, [fp, #0x38] str w4, [fp, #0x34] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x20] ldr x0, [fp, #0x48] ldr x0, [x0, #0x10] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x18] ldr x0, [fp, #0x48] ldr x0, [x0, #0x10] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x10] ldr x2, [fp, #0x10] ldr x1, [fp, #0x18] ldr x0, [fp, #0x20] ldr w3, [fp, #0x3C] ldr w4, [fp, #0x34] ldr x5, [fp, #0x20] ldr x5, [x5] ldr x5, [x5, #0x40] ldr x5, [x5, #0x30] blr x5 str x0, [fp, #0x28] ldr x0, [fp, #0x48] ldr x1, [fp, #0x28] ldr x2, [fp, #0x40] ldr w3, [fp, #0x3C] ldr w5, [fp, #0x38] mov w4, #2 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 244 923: JIT compiled BenchmarkDotNet.Engines.EngineWarmupStage:Run(long,int,int,int) [Tier0, IL size=48, code size=244] ; Assembly listing for method System.Diagnostics.Tracing.EventSource:WriteEventWithRelatedActivityIdCore(int,ulong,int,ulong):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 478 ; 2 inlinees with PGO data; 10 single block inlinees; 0 inlinees without PGO data ; Assembly listing for method BenchmarkDotNet.Engines.DefaultStoppingCriteriaFactory:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp G_M000_IG03:fp, lr, [sp], #0x20 ret lr stp ; Total bytes of code 84 fp, lr, [sp, #-0xD0]! stp x19, x20, [sp, #0xA0] 924: JIT compiled BenchmarkDotNet.Engines.DefaultStoppingCriteriaFactory:.cctor() [Tier0, IL size=11, code size=84] stp x21, x22, [sp, #0xB0] stp x23, x24, [sp, #0xC0] mov fp, sp add x5, sp, #208 str x5, [fp, #0x98] str x0, [fp, #0x18] str w1, [fp, #0x94] mov x19, x2 mov w21, w3 mov x20, x4 G_M000_IG02: ldrb w3, [x0, #0x9D] cbnz w3, G_M000_IG04 G_M000_IG03: ldp x23, x24, [sp, #0xC0] ldp x21, x22, [sp, #0xB0] ldp x19, x20, [sp, #0xA0] ldp fp, lr, [sp], #0xD0 ret lr G_M000_IG04: ldr x3, [x0, #0x10] dmb ishld ldr w2, [x3, #0x08] cmp w1, w2 bhs G_M000_IG05 mov w2, #96 umull x2, w1, w2 add x2, x2, #16 add x22, x3, x2 ldrb w23, [x22, #0x55] mov x24, xzr movi v16.4s, #0 str q16, [fp, #0x80] movi v16.4s, #0 str q16, [fp, #0x70] cbz w23, G_M000_IG08 cbnz x19, G_M000_IG08 ldr w3, [x22, #0x40] tbnz w3, #1, G_M000_IG08 cmp w23, #1 bne G_M000_IG06 ldrh w3, [x22, #0x56] ldr x1, [x0, #0x08] ldr x2, [x22] ldr x0, [x0, #0x68] ldr w6, [x22, #0x40] add x5, fp, #112 add x4, fp, #128 mov w7, #1 movz x8, #0xD1FFAB1E movk x8, #0xD1FFAB1E LSL #16 movk x8, #0xD1FFAB1E LSL #32 ldr x8, [x8] ldr wzr, [x0] blr x8 b G_M000_IG07 G_M000_IG05: bl CORINFO_HELP_RNGCHKFAIL G_M000_IG06: cmp w23, #2 bne G_M000_IG07 ldrh w3, [x22, #0x56] ldr x1, [x0, #0x08] ldr x2, [x22] ldr x0, [x0, #0x68] add x4, fp, #128 mov w5, #1 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] ldr wzr, [x0] blr x6 G_M000_IG07: ldr q16, [fp, #0x80] str q16, [fp, #0x30] ldr q16, [fp, #0x30] umaxp v16.4s, v16.4s, v16.4s umov x1, v16.d[0] add x0, fp, #128 cmp x1, #0 csel x24, x24, x0, eq ldr q16, [fp, #0x70] str q16, [fp, #0x20] ldr q16, [fp, #0x20] umaxp v16.4s, v16.4s, v16.4s umov x1, v16.d[0] add x0, fp, #112 cmp x1, #0 csel x19, x19, x0, eq ldr x0, [fp, #0x18] G_M000_IG08: ldr w2, [x0, #0x94] tbnz w2, #3, G_M000_IG10 ldrb w2, [x22, #0x45] cbz w2, G_M000_IG09 add x1, x22, #80 ldr x0, [x0, #0x30] dmb ishld ldr x2, [x22, #0x30] mov x3, x24 mov x4, x19 mov w5, w21 mov x6, x20 movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] ldr wzr, [x0] blr x7 cbnz w0, G_M000_IG09 ldr x1, [x22] ldr x0, [fp, #0x18] mov x2, xzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG09: ldr x0, [fp, #0x18] ldrb w2, [x22, #0x46] cbz w2, G_M000_IG12 add x1, x22, #80 ldr x0, [x0, #0x40] dmb ishld ldr x2, [x22, #0x30] mov x3, x24 mov x4, x19 mov w5, w21 mov x6, x20 movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] ldr wzr, [x0] blr x7 cbnz w0, G_M000_IG12 ldr x1, [x22] ldr x0, [fp, #0x18] mov x2, xzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG12 G_M000_IG10: ldrb w2, [x22, #0x45] cbnz w2; Assembly listing for method BenchmarkDotNet.Engines.DefaultStoppingCriteriaFactory:.ctor():this , G_M000_IG11 ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible ldrb w2, [x22, #0x46] cbz w2, G_M000_IG12 G_M000_IG11: stp xzr, xzr, [fp, #0x40] str xzr, [fp, #0x50] ldr x1, [x22, #0x58] add x0, fp, #64 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldrb w1, [x22, #0x54] add x0, fp, #64 movz x2, #0xD1FFAB1E G_M000_IG01: movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 stp fpldr x2, [x2] , lr, [sp blr x2 , #-0x20]! ldrb w1, [x22, #0x55] mov add x0, fp, #64 fp, sp movz x2, #0xD1FFAB1E str movk x2, #0xD1FFAB1E LSL #16 x0, [fp, #0x18] movk x2, #0xD1FFAB1E LSL #32 G_M000_IG02: ldr x2, [x2] ldr blr x2 x0, [fp, #0x18] ldp movz x1x0, x1, [fp, #0x40] , #0xD1FFAB1E stp x0, x1, [fp, #0x58] movk x1, #0xD1FFAB1E LSL #16 ldr movk x1, #0xD1FFAB1E LSL #32 x0, [fp, # ldr 0x50] x1, str x0, [fp, #0x68] [x1 ldr x23, [x22] ] mov x0, x22 blr movz x1, #0xD1FFAB1E x1 G_M000_IG03: movk x1, #0xD1FFAB1E LSL #16 movk ldp fp, lr, [sp x1, #0xD1FFAB1E LSL #32 ] ldr x1, [x1] , #0x20 ret lr ; Total bytes of code 44 blr x1 mov x3, x0 mov x1, x23 add x2, fp, #88 ldr x0, [fp, #0x18] mov x4, x24 mov x5, x19 mov x6, x20 movz x7, #0xD1FFAB1E 925: JIT compiled BenchmarkDotNet.Engines.DefaultStoppingCriteriaFactory:.ctor() [Tier0, IL size=7, code size=44] movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 G_M000_IG12: ldr x0, [fp, #0x18] ldr x2, [x0, #0x28] dmb ishld cbz x2, G_M000_IG03 ldr x0, [fp, #0x18] ldr w1, [fp, #0x94] ldrb w2, [x22, #0x44] cbz w2, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x22, x0 ldr x1, [fp, #0x18] ldr w2, [fp, #0x94] mov x3, x24 mov x4, x19 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 ldr x0, [fp, #0x18] mov x1, x22 mov w2, w21 mov x3, x20 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 b G_M000_IG03 G_M000_IG13: stp fp, lr, [sp, #-0x50]! stp x19, x20, [sp, #0x20] stp x21, x22, [sp, #0x30] stp x23, x24, [sp, #0x40] add x3, fp, #208 str x3, [sp, #0x18] G_M000_IG14: mov x19, x0 mov x1, x19 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz x0, G_M000_IG15 bl CORINFO_HELP_RETHROW G_M000_IG15: ldr x0, [fp, #0x18] mov x1, x0 ldr x1, [x1, #0x10] dmb ishld ldr w2, [x1, #0x08] ldr w3, [fp, #0x94] cmp w3, w2 bhs G_M000_IG17 mov w2, #96 umull x2, w3, w2 add x2, x2, #16 ldr x1, [x1, x2] mov x2, x19 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 adr x0, [G_M000_IG03] G_M000_IG16: ldp x23, x24, [sp, #0x40] ldp x21, x22, [sp, #0x30] ldp x19, x20, [sp, #0x20] ldp fp, lr, [sp], #0x50 ret lr G_M000_IG17: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 1068 ; Assembly listing for method BenchmarkDotNet.Engines.DefaultStoppingCriteriaFactory:CreateWarmup(BenchmarkDotNet.Jobs.Job,BenchmarkDotNet.Characteristics.IResolver,int,int):BenchmarkDotNet.Engines.IStoppingCriteria:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible 926: JIT compiled System.Diagnostics.Tracing.EventSource:WriteEventWithRelatedActivityIdCore(int,ulong,int,ulong) [Tier1 with Static PGO, IL size=519, code size=1068] G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] str w3, [fp, #0x34] str w4, [fp, #0x30] G_M000_IG02: ldr w0, [fp, #0x34] cbz w0, G_M000_IG04 ldr w0, [fp, #0x34] cmp w0, #1 beq G_M000_IG06 G_M000_IG03: b G_M000_IG08 G_M000_IG04: ldr x0, [fp, #0x48] ldr x1, [fp, #0x48] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x28] blr x1 G_M000_IG05: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG06: ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] ldr x2, [fp, #0x38] ldr w3, [fp, #0x30] ldr x4, [fp, #0x48] ldr x4, [x4] ldr x4, [x4, #0x40] ldr x4, [x4, #0x20] blr x4 G_M000_IG07: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG08: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr w1, [fp, #0x34] str w1, [x0, #0x08] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x2, [fp, #0x28] ldr x0, [fp, #0x20] mov x3, xzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x20] bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 264 927: JIT compiled BenchmarkDotNet.Engines.DefaultStoppingCriteriaFactory:CreateWarmup(BenchmarkDotNet.Jobs.Job,BenchmarkDotNet.Characteristics.IResolver,int,int) [Tier0, IL size=45, code size=264] ; Assembly listing for method BenchmarkDotNet.Engines.DefaultStoppingCriteriaFactory:CreateWarmupOverhead():BenchmarkDotNet.Engines.IStoppingCriteria:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] mov w1, #4 mov w2, #10 mov w3, #4 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 928: JIT compiled BenchmarkDotNet.Engines.DefaultStoppingCriteriaFactory:CreateWarmupOverhead() [Tier0, IL size=10, code size=84] ; Assembly listing for method BenchmarkDotNet.Engines.AutoWarmupStoppingCriteria:.ctor(int,int,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] str x0, [fp, #0x48] str w1, [fp, #0x44] str w2, [fp, #0x40] str w3, [fp, #0x3C] G_M000_IG02: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x48] ldr w1, [fp, #0x44] str w1, [x0, #0x30] ldr x0, [fp, #0x48] ldr w1, [fp, #0x40] str w1, [x0, #0x34] ldr x0, [fp, #0x48] ldr w1, [fp, #0x3C] str w1, [x0, #0x38] add x0, fp, #16 mov w1, #46 mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x0, fp, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #16 ldr w1, [fp, #0x40] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x48] add x14, x14, #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF add x0, fp, #16 mov w1, #89 mov w2, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x0, fp, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #16 ldr w1, [fp, #0x3C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #16 ldr w1, [fp, #0x44] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x48] add x14, x14, #40 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 552 929: JIT compiled BenchmarkDotNet.Engines.AutoWarmupStoppingCriteria:.ctor(int,int,int) [Tier0, IL size=170, code size=552] ; Assembly listing for method BenchmarkDotNet.Engines.StoppingCriteriaBase:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #40 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x0, [fp, #0x58] G_M000_IG02: ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x50] ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x20] ldr x2, [fp, #0x20] ldr x1, [fp, #0x58] ldr x0, [fp, #0x50] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] ldr x0, [fp, #0x48] ldr x1, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x58] add x14, x14, #8 ldr x15, [fp, #0x48] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x40] ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x18] ldr x2, [fp, #0x18] ldr x1, [fp, #0x58] ldr x0, [fp, #0x40] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] ldr x0, [fp, #0x38] ldr x1, [fp, #0x40] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x58] add x14, x14, #16 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] ldr x0, [fp, #0x30] ldr x1, [fp, #0x58] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x1, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x58] add x14, x14, #24 ldr x15, [fp, #0x28] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 488 930: JIT compiled BenchmarkDotNet.Engines.StoppingCriteriaBase:.ctor() [Tier0, IL size=78, code size=488] ; Assembly listing for method BenchmarkDotNet.Engines.EngineStage:Run(BenchmarkDotNet.Engines.IStoppingCriteria,long,int,int,int):System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xD0]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] stp xzr, xzr, [x9, #0x80] str x0, [fp, #0xC8] str x1, [fp, #0xC0] str x2, [fp, #0xB8] str w3, [fp, #0xB4] str w4, [fp, #0xB0] str w5, [fp, #0xAC] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x90] ldr x0, [fp, #0xC0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str w0, [fp, #0x44] ldr w1, [fp, #0x44] ldr x0, [fp, #0x90] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x90] str x0, [fp, #0xA0] ldr x0, [fp, #0xC0] ldr x1, [fp, #0xA0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 str x0, [fp, #0x80] str x1, [fp, #0x88] mov w0, #0xD1FFAB1E str w0, [fp, #0x48] ldrb w0, [fp, #0x88] cbz w0, G_M000_IG04 ldr x0, [fp, #0xC8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xA0] G_M000_IG03: ldp fp, lr, [sp], #0xD0 ret lr G_M000_IG04: str wzr, [fp, #0x9C] G_M000_IG05: ldr w0, [fp, #0x48] sub w0, w0, #1 str w0, [fp, #0x48] ldr w0, [fp, #0x48] cmp w0, #0 bgt G_M000_IG07 G_M000_IG06: add x0, fp, #72 mov w1, #36 bl CORINFO_HELP_PATCHPOINT G_M000_IG07: ldr w8, [fp, #0x9C] add w8, w8, #1 str w8, [fp, #0x9C] add x8, fp, #96 ldr x0, [fp, #0xC8] ldr w1, [fp, #0xB4] ldr w2, [fp, #0xB0] ldr w3, [fp, #0x9C] ldr x4, [fp, #0xB8] ldr w5, [fp, #0xAC] movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x0, [fp, #0xA0] str x0, [fp, #0x18] ldp q16, q17, [fp, #0x60] stp q16, q17, [fp, #0x20] ldr x0, [fp, #0x18] add x1, fp, #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xC0] ldr x1, [fp, #0xA0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 str x0, [fp, #0x50] str x1, [fp, #0x58] ldrb w0, [fp, #0x58] cbz w0, G_M000_IG05 ldr x0, [fp, #0xC8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xA0] G_M000_IG08: ldp fp, lr, [sp], #0xD0 ret lr ; Total bytes of code 460 931: JIT compiled BenchmarkDotNet.Engines.EngineStage:Run(BenchmarkDotNet.Engines.IStoppingCriteria,long,int,int,int) [Tier0, IL size=81, code size=460] ; Assembly listing for method BenchmarkDotNet.Engines.StoppingCriteriaBase:get_MaxIterationCount():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 52 932: JIT compiled BenchmarkDotNet.Engines.StoppingCriteriaBase:get_MaxIterationCount() [Tier0, IL size=12, code size=52] ; Assembly listing for method System.Lazy`1[int]:get_Value():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] dmb ishld cbz x0, G_M000_IG04 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: ldr x0, [fp, #0x18] ldr w0, [x0, #0x18] G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 76 933: JIT compiled System.Lazy`1[int]:get_Value() [Tier0, IL size=24, code size=76] ; Assembly listing for method System.Lazy`1[int]:CreateValue():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] dmb ishld str x0, [fp, #0x20] ldr x0, [fp, #0x20] cbz x0, G_M000_IG12 ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str w0, [fp, #0x1C] ldr w0, [fp, #0x1C] cmp w0, #8 bhi G_M000_IG03 ldr w0, [fp, #0x1C] mov w0, w0 adr x1, [@RWD00] ldr w1, [x1, x0, LSL #2] adr x2, [G_M000_IG02] add x1, x1, x2 br x1 G_M000_IG03: b G_M000_IG11 G_M000_IG04: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 b G_M000_IG12 G_M000_IG05: ldr x0, [fp, #0x28] mov w1, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG12 G_M000_IG06: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG12 G_M000_IG07: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG12 G_M000_IG08: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 b G_M000_IG12 G_M000_IG09: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG12 G_M000_IG10: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] mov w2, wzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG12 G_M000_IG11: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 G_M000_IG12: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG13: ldp fp, lr, [sp], #0x30 ret lr RWD00 dd G_M000_IG04 - G_M000_IG02 dd G_M000_IG05 - G_M000_IG02 dd G_M000_IG11 - G_M000_IG02 dd G_M000_IG06 - G_M000_IG02 dd G_M000_IG07 - G_M000_IG02 dd G_M000_IG08 - G_M000_IG02 dd G_M000_IG11 - G_M000_IG02 dd G_M000_IG09 - G_M000_IG02 dd G_M000_IG10 - G_M000_IG02 ; Total bytes of code 400 934: JIT compiled System.Lazy`1[int]:CreateValue() [Tier0, IL size=139, code size=400] ; Assembly listing for method System.Lazy`1[int]:ExecutionAndPublication(System.LazyHelper,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x18] add x3, sp, #64 str x3, [fp, #0x38] str x0, [fp, #0x30] str x1, [fp, #0x28] str w2, [fp, #0x24] G_M000_IG02: ldr x1, [fp, #0x28] str x1, [fp, #0x18] str wzr, [fp, #0x10] G_M000_IG03: add x1, fp, #16 ldr x0, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x30] ldr x0, [x0, #0x08] dmb ishld ldr x1, [fp, #0x28] cmp x0, x1 bne G_M000_IG05 ldr w0, [fp, #0x24] uxtb w0, w0 cbz w0, G_M000_IG04 ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 b G_M000_IG06 G_M000_IG04: ldr x0, [fp, #0x30] mov w1, #2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG05: b G_M000_IG08 G_M000_IG06: ldr x0, [fp, #0x38] bl G_M000_IG11 G_M000_IG07: b G_M000_IG10 G_M000_IG08: ldr x0, [fp, #0x38] bl G_M000_IG11 G_M000_IG09: nop G_M000_IG10: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG11: stp fp, lr, [sp, #-0x20]! add x3, fp, #64 str x3, [sp, #0x18] G_M000_IG12: ldr w0, [fp, #0x10] uxtb w0, w0 cbz w0, G_M000_IG13 ldr x0, [fp, #0x18] bl System.Threading.Monitor:Exit(System.Object) G_M000_IG13: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 240 935: JIT compiled System.Lazy`1[int]:ExecutionAndPublication(System.LazyHelper,bool) [Tier0, IL size=54, code size=240] ; Assembly listing for method System.Lazy`1[int]:ViaFactory(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] add x2, sp, #96 str x2, [fp, #0x58] str x0, [fp, #0x50] str w1, [fp, #0x4C] G_M000_IG02: ldr x0, [fp, #0x50] ldr x0, [x0, #0x10] str x0, [fp, #0x40] ldr x0, [fp, #0x40] cbnz x0, G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x30] bl CORINFO_HELP_THROW G_M000_IG04: ldr x0, [fp, #0x50] str xzr, [x0, #0x10] ldr x0, [fp, #0x40] ldr x0, [x0, #0x08] ldr x1, [fp, #0x40] ldr x1, [x1, #0x18] blr x1 ldr x1, [fp, #0x50] str w0, [x1, #0x18] ldr x0, [fp, #0x50] dmb ish str xzr, [x0, #0x08] b G_M000_IG05 G_M000_IG05: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG06: stp fp, lr, [sp, #-0x20]! add x3, fp, #96 str x3, [sp, #0x18] G_M000_IG07: str x0, [fp, #0x28] ldr x0, [fp, #0x28] str x0, [fp, #0x38] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr w1, [fp, #0x4C] ldr x2, [fp, #0x38] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x14, [fp, #0x50] add x14, x14, #8 ldr x15, [fp, #0x20] bl CORINFO_HELP_ASSIGN_REF bl CORINFO_HELP_RETHROW brk_windows #0 ; Total bytes of code 300 936: JIT compiled System.Lazy`1[int]:ViaFactory(int) [Tier0, IL size=70, code size=300] ; Assembly listing for method BenchmarkDotNet.Engines.AutoWarmupStoppingCriteria:GetMaxIterationCount():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x34] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 937: JIT compiled BenchmarkDotNet.Engines.AutoWarmupStoppingCriteria:GetMaxIterationCount() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.AutoWarmupStoppingCriteria:Evaluate(System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Reports.Measurement]):BenchmarkDotNet.Engines.StoppingResult:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xB0]! mov fp, sp add x9, fp, #32 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] str x0, [fp, #0xA8] str x1, [fp, #0xA0] G_M000_IG02: ldr x0, [fp, #0xA0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str w0, [fp, #0x9C] mov w0, #0xD1FFAB1E str w0, [fp, #0x18] ldr w0, [fp, #0x9C] ldr x1, [fp, #0xA8] ldr w1, [x1, #0x34] cmp w0, w1 blt G_M000_IG04 ldr x0, [fp, #0xA8] ldr x0, [x0, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x20] str x1, [fp, #0x28] ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] G_M000_IG03: ldp fp, lr, [sp], #0xB0 ret lr G_M000_IG04: ldr w0, [fp, #0x9C] ldr x1, [fp, #0xA8] ldr w1, [x1, #0x30] cmp w0, w1 bge G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] G_M000_IG05: ldp x1, x2, [x0, #0x08] stp x1, x2, [fp, #0x30] G_M000_IG06: ldr x0, [fp, #0x30] ldr x1, [fp, #0x38] G_M000_IG07: ldp fp, lr, [sp], #0xB0 ret lr G_M000_IG08: movn w0, #0 str w0, [fp, #0x98] str wzr, [fp, #0x94] mov w0, #1 str w0, [fp, #0x90] b G_M000_IG12 G_M000_IG09: add x8, fp, #104 ldr x0, [fp, #0xA0] ldr w1, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 add x0, fp, #104 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x60] ldr w1, [fp, #0x90] sub w1, w1, #1 add x8, fp, #104 ldr x0, [fp, #0xA0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 add x0, fp, #104 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0x60] fsub d0, d16, d0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0x8C] ldr w0, [fp, #0x8C] ldr w1, [fp, #0x98] cmp w0, w1 bne G_M000_IG10 ldr w0, [fp, #0x8C] cbnz w0, G_M000_IG11 G_M000_IG10: ldr w0, [fp, #0x8C] str w0, [fp, #0x98] ldr w0, [fp, #0x94] add w0, w0, #1 str w0, [fp, #0x94] G_M000_IG11: ldr w0, [fp, #0x90] add w0, w0, #1 str w0, [fp, #0x90] G_M000_IG12: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG14 G_M000_IG13: add x0, fp, #24 mov w1, #113 bl CORINFO_HELP_PATCHPOINT G_M000_IG14: ldr w8, [fp, #0x90] ldr w0, [fp, #0x9C] cmp w8, w0 blt G_M000_IG09 ldr w0, [fp, #0x94] ldr x1, [fp, #0xA8] ldr w1, [x1, #0x38] cmp w0, w1 bge G_M000_IG18 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] G_M000_IG15: ldp x1, x2, [x0, #0x08] stp x1, x2, [fp, #0x40] G_M000_IG16: ldr x0, [fp, #0x40] ldr x1, [fp, #0x48] G_M000_IG17: ldp fp, lr, [sp], #0xB0 ret lr G_M000_IG18: ldr x0, [fp, #0xA8] ldr x0, [x0, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x50] str x1, [fp, #0x58] ldr x0, [fp, #0x50] ldr x1, [fp, #0x58] G_M000_IG19: ldp fp, lr, [sp], #0xB0 ret lr ; Total bytes of code 644 938: JIT compiled BenchmarkDotNet.Engines.AutoWarmupStoppingCriteria:Evaluate(System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Reports.Measurement]) [Tier0, IL size=144, code size=644] ; Assembly listing for method BenchmarkDotNet.Engines.StoppingResult:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] G_M000_IG02: stp xzr, xzr, [fp, #0x10] add x0, fp, #16 mov w1, wzr mov x2, xzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 ldr x14, [x14] add x14, x14, #8 add x13, fp, #16 bl CORINFO_HELP_ASSIGN_BYREF ldr x12, [x13], #0x08 str x12, [x14], #0x08 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 92 939: JIT compiled BenchmarkDotNet.Engines.StoppingResult:.cctor() [Tier0, IL size=13, code size=92] ; Assembly listing for method BenchmarkDotNet.Engines.StoppingResult:.ctor(bool,System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str w1, [fp, #0x24] str x2, [fp, #0x18] G_M000_IG02: ldr x14, [fp, #0x28] ldr w15, [fp, #0x24] strb w15, [x14, #0x08] ldr x14, [fp, #0x28] ldr x15, [fp, #0x18] bl CORINFO_HELP_CHECKED_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 52 940: JIT compiled BenchmarkDotNet.Engines.StoppingResult:.ctor(bool,System.String) [Tier0, IL size=15, code size=52] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:OverheadWarmupStart(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x2, [fp, #0x10] mov w1, #9 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 941: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:OverheadWarmupStart(long) [Tier0, IL size=10, code size=56] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:OverheadWarmupStop(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x2, [fp, #0x10] mov w1, #10 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 942: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:OverheadWarmupStop(long) [Tier0, IL size=10, code size=56] ; Assembly listing for method System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:get_Item(int):BenchmarkDotNet.Reports.Measurement:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str w1, [fp, #0x1C] str x8, [fp, #0x20] G_M000_IG02: ldr w0, [fp, #0x1C] ldr x1, [fp, #0x28] ldr w1, [x1, #0x10] cmp w0, w1 blo G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG03: ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] ldr w1, [fp, #0x1C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG05 add x0, x0, x1, LSL #5 add x0, x0, #16 ldr x1, [fp, #0x20] ldp q16, q17, [x0] stp q16, q17, [x1] G_M000_IG04: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG05: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 120 943: JIT compiled System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:get_Item(int) [Tier0, IL size=27, code size=120] ; Assembly listing for method BenchmarkDotNet.Engines.StoppingResult:CreateFinished(System.String):BenchmarkDotNet.Engines.StoppingResult ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: stp xzr, xzr, [fp, #0x18] add x0, fp, #24 ldr x2, [fp, #0x28] mov w1, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] ldr x1, [fp, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 68 944: JIT compiled BenchmarkDotNet.Engines.StoppingResult:CreateFinished(System.String) [Tier0, IL size=8, code size=68] ; Assembly listing for method BenchmarkDotNet.Engines.EngineActualStage:RunOverhead(long,int):System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Reports.Measurement]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] G_M000_IG02: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] ldr w3, [fp, #0x1C] mov w2, wzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 64 945: JIT compiled BenchmarkDotNet.Engines.EngineActualStage:RunOverhead(long,int) [Tier0, IL size=10, code size=64] ; Assembly listing for method BenchmarkDotNet.Engines.EngineActualStage:RunAuto(long,int,int):System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! mov fp, sp movi v16.16b, #0 add x9, fp, #88 add x10, fp, #0xD1FFAB1E stp q16, q16, [x9, #-0x40] stp q16, q16, [x9, #-0x20] bfm x9, xzr, #0, #5 dczva x9 add x9, x9, #64 cmp x9, x10 blo pc-16 (-4 instructions) stp q16, q16, [x10] stp q16, q16, [x10, #0x20] str x0, [fp, #0xD1FFAB1E] str x1, [fp, #0xD1FFAB1E] str w2, [fp, #0xD1FFAB1E] str w3, [fp, #0xD1FFAB1E] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xB0] ldr x1, [fp, #0xD1FFAB1E] ldr w1, [x1, #0x20] ldr x0, [fp, #0xB0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xB0] str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xA8] ldr x1, [fp, #0xD1FFAB1E] ldr w1, [x1, #0x20] ldr x0, [fp, #0xA8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xA8] str x0, [fp, #0xD1FFAB1E] str wzr, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] cmp w0, #0 cset x0, eq str w0, [fp, #0xD1FFAB1E] mov w0, #0xD1FFAB1E str w0, [fp, #0x68] ldr w0, [fp, #0xD1FFAB1E] cbnz w0, G_M000_IG03 ldr x0, [fp, #0xD1FFAB1E] ldr d16, [x0, #0x10] str d16, [fp, #0xA0] b G_M000_IG04 G_M000_IG03: ldr d16, [@RWD00] str d16, [fp, #0xA0] G_M000_IG04: ldr d16, [fp, #0xA0] str d16, [fp, #0xD1FFAB1E] G_M000_IG05: ldr w0, [fp, #0x68] sub w0, w0, #1 str w0, [fp, #0x68] ldr w0, [fp, #0x68] cmp w0, #0 bgt G_M000_IG07 G_M000_IG06: add x0, fp, #104 mov w1, #53 bl CORINFO_HELP_PATCHPOINT G_M000_IG07: ldr w8, [fp, #0xD1FFAB1E] add w8, w8, #1 str w8, [fp, #0xD1FFAB1E] add x8, fp, #0xD1FFAB1E ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xD1FFAB1E] ldr w5, [fp, #0xD1FFAB1E] ldr w3, [fp, #0xD1FFAB1E] ldr x4, [fp, #0xD1FFAB1E] mov w2, #3 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x40] ldp x0, x1, [fp, #0xD1FFAB1E] stp x0, x1, [fp, #0x48] ldp x0, x1, [fp, #0xD1FFAB1E] stp x0, x1, [fp, #0x58] ldr x0, [fp, #0x40] add x1, fp, #72 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x18] G_M000_IG08: add x0, fp, #0xD1FFAB1E ldp q16, q17, [x0, #0x20] stp q16, q17, [fp, #0x20] G_M000_IG09: ldr x0, [fp, #0x18] add x1, fp, #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x1, [fp, #0xD1FFAB1E] ldr w1, [x1, #0x18] add x8, fp, #0xD1FFAB1E ldr x0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #0xD1FFAB1E add x8, fp, #192 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 add x0, fp, #192 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0xD1FFAB1E] add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0xD1FFAB1E] fmul d16, d0, d16 str d16, [fp, #0x90] ldr x0, [fp, #0xD1FFAB1E] ldrsb wzr, [x0] ldr x0, [fp, #0xD1FFAB1E] add x0, x0, #48 str x0, [fp, #0x98] ldr d16, [fp, #0x90] str d16, [fp, #0x88] ldr x0, [fp, #0x98] str x0, [fp, #0x80] ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG10 ldr d16, [fp, #0x88] str d16, [fp, #0x78] ldr d16, [@RWD08] str d16, [fp, #0x70] b G_M000_IG11 G_M000_IG10: ldr x0, [fp, #0x80] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0xB8] ldr d16, [fp, #0x88] str d16, [fp, #0x78] add x0, fp, #184 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x70] G_M000_IG11: ldr d0, [fp, #0x70] str d0, [fp, #0xD1FFAB1E] ldr d0, [fp, #0x78] ldr d1, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0xF8] ldr w0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr w1, [x1, #0x1C] cmp w0, w1 blt G_M000_IG12 ldr d16, [fp, #0xD1FFAB1E] ldr d17, [fp, #0xF8] fcmp d16, d17 blo G_M000_IG13 G_M000_IG12: ldr w0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr w1, [x1, #0x20] cmp w0, w1 bge G_M000_IG13 ldr w0, [fp, #0xD1FFAB1E] cbz w0, G_M000_IG05 ldr w0, [fp, #0xD1FFAB1E] cmp w0, #20 blt G_M000_IG05 G_M000_IG13: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] G_M000_IG14: ldp fp, lr, [sp], #0xD1FFAB1E ret lr RWD00 dq 3FA999999999999Ah ; 0.05 RWD08 dq 7FEFFFFFFFFFFFFFh ; 1.79769313e+308 ; Total bytes of code 892 946: JIT compiled BenchmarkDotNet.Engines.EngineActualStage:RunAuto(long,int,int) [Tier0, IL size=225, code size=892] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:OverheadActualStart(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x2, [fp, #0x10] mov w1, #11 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 947: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:OverheadActualStart(long) [Tier0, IL size=10, code size=56] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:OverheadActualStop(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x2, [fp, #0x10] mov w1, #12 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 948: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:OverheadActualStop(long) [Tier0, IL size=10, code size=56] ; Assembly listing for method BenchmarkDotNet.Mathematics.MeasurementsStatistics:Calculate(System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement],int):BenchmarkDotNet.Mathematics.MeasurementsStatistics ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: sub sp, sp, #0xD1FFAB1E stp fp, lr, [sp] mov fp, sp movi v16.16b, #0 add x9, fp, #0xD1FFAB1E add x10, fp, #0xD1FFAB1E stp q16, q16, [x9, #-0x40] stp q16, q16, [x9, #-0x20] bfm x9, xzr, #0, #5 dczva x9 add x9, x9, #64 cmp x9, x10 blo pc-16 (-4 instructions) stp q16, q16, [x10] stp q16, q16, [x10, #0x20] str x0, [fp, #0xD1FFAB1E] str w1, [fp, #0xD1FFAB1E] str x8, [fp, #0xD1FFAB1E] G_M000_IG02: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str w0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] cbnz w0, G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xC8] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0xC0] ldr x1, [fp, #0xC0] ldr x0, [fp, #0xC8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xC8] bl CORINFO_HELP_THROW G_M000_IG04: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0xD1FFAB1E] ldr d0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] scvtf d16, w0 fdiv d0, d0, d16 str d0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xD1FFAB1E] ldr d0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str d0, [fp, #0xB8] ldr d0, [fp, #0xB8] bl System.Math:Sqrt(double):double str d0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] scvtf d0, w0 bl System.Math:Sqrt(double):double ldr d1, [fp, #0xD1FFAB1E] fdiv d0, d1, d0 str d0, [fp, #0xD1FFAB1E] add x0, fp, #0xD1FFAB1E ldr d0, [fp, #0xD1FFAB1E] ldr d1, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xD1FFAB1E] mov w2, #12 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr w1, [fp, #0xD1FFAB1E] cbnz w1, G_M000_IG06 movi v0.16b, #0 stp q0, q0, [fp, #0xD0] stp q0, q0, [fp, #0xF0] str xzr, [fp, #0xD1FFAB1E] ldr d0, [fp, #0xD1FFAB1E] str d0, [fp, #0x78] ldr d0, [fp, #0xD1FFAB1E] str d0, [fp, #0x70] ldp q0, q1, [fp, #0xD1FFAB1E] stp q0, q1, [fp, #0x80] ldr q0, [fp, #0xD1FFAB1E] str q0, [fp, #0xA0] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xB0] ldr d0, [fp, #0x78] ldr d1, [fp, #0x70] add x1, fp, #128 add x0, fp, #208 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xD1FFAB1E] ldp q16, q17, [fp, #0xD0] stp q16, q17, [x0] ldp q16, q17, [fp, #0xF0] stp q16, q17, [x0, #0x20] ldr x1, [fp, #0xD1FFAB1E] str x1, [x0, #0x40] G_M000_IG05: ldp fp, lr, [sp] add sp, sp, #0xD1FFAB1E ret lr G_M000_IG06: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 ldr w8, [fp, #0xD1FFAB1E] cmp w8, #1 bne G_M000_IG07 add x8, fp, #0xD1FFAB1E ldr x0, [fp, #0xD1FFAB1E] mov w1, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0xD1FFAB1E] ldr d16, [fp, #0xD1FFAB1E] str d16, [fp, #0xD1FFAB1E] ldr d16, [fp, #0xD1FFAB1E] str d16, [fp, #0xD1FFAB1E] b G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str w0, [fp, #0x14] ldr w1, [fp, #0x14] lsr w1, w1, #31 ldr w0, [fp, #0x14] add w1, w1, w0 asr w1, w1, #1 str w1, [fp, #0x6C] ldr w1, [fp, #0x6C] ldr x0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str d0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 mov w1, #3 mul w1, w0, w1 str w1, [fp, #0x10] ldr w1, [fp, #0x10] lsr w1, w1, #31 ldr w0, [fp, #0x10] add w1, w1, w0 asr w1, w1, #1 str w1, [fp, #0x68] ldr w1, [fp, #0x68] ldr x0, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str d0, [fp, #0xD1FFAB1E] G_M000_IG08: ldr d0, [fp, #0xD1FFAB1E] ldr d1, [fp, #0xD1FFAB1E] fsub d0, d0, d1 str d0, [fp, #0xD1FFAB1E] ldr d0, [fp, #0xD1FFAB1E] ldr d1, [fp, #0xD1FFAB1E] fmov d16, #1.5000 fmul d1, d1, d16 fsub d0, d0, d1 str d0, [fp, #0xD1FFAB1E] ldr d0, [fp, #0xD1FFAB1E] ldr d1, [fp, #0xD1FFAB1E] fmov d16, #1.5000 fmul d1, d1, d16 fadd d0, d0, d1 str d0, [fp, #0xD1FFAB1E] add x2, fp, #0xD1FFAB1E add x3, fp, #0xD1FFAB1E ldr w0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr d0, [fp, #0xD1FFAB1E] ldr d1, [fp, #0xD1FFAB1E] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr d0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] scvtf d1, w0 fdiv d0, d0, d1 str d0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] ldr w2, [fp, #0xD1FFAB1E] ldr d0, [fp, #0xD1FFAB1E] ldr d1, [fp, #0xD1FFAB1E] ldr d2, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str d0, [fp, #0x60] ldr d0, [fp, #0x60] bl System.Math:Sqrt(double):double str d0, [fp, #0xD1FFAB1E] ldr w0, [fp, #0xD1FFAB1E] scvtf d0, w0 bl System.Math:Sqrt(double):double ldr d1, [fp, #0xD1FFAB1E] fdiv d0, d1, d0 str d0, [fp, #0xD1FFAB1E] add x0, fp, #0xD1FFAB1E ldr d0, [fp, #0xD1FFAB1E] ldr d1, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xD1FFAB1E] mov w2, #12 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movi v0.16b, #0 stp q0, q0, [fp, #0xD1FFAB1E] stp q0, q0, [fp, #0xD1FFAB1E] str xzr, [fp, #0xD1FFAB1E] ldr d0, [fp, #0xD1FFAB1E] str d0, [fp, #0x20] ldr d0, [fp, #0xD1FFAB1E] str d0, [fp, #0x18] G_M000_IG09: add x0, fp, #0xD1FFAB1E ldr x1, [x0, #0x28] str x1, [fp, #0x28] ldp q0, q1, [x0, #0x30] stp q0, q1, [fp, #0x30] ldr q0, [x0, #0x50] str q0, [fp, #0x50] G_M000_IG10: ldr d0, [fp, #0x20] ldr d1, [fp, #0x18] add x1, fp, #40 add x0, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xD1FFAB1E] ldp q16, q17, [fp, #0xD1FFAB1E] stp q16, q17, [x0] ldp q16, q17, [fp, #0xD1FFAB1E] stp q16, q17, [x0, #0x20] ldr x1, [fp, #0xD1FFAB1E] str x1, [x0, #0x40] G_M000_IG11: ldp fp, lr, [sp] add sp, sp, #0xD1FFAB1E ret lr ; Total bytes of code 1188 949: JIT compiled BenchmarkDotNet.Mathematics.MeasurementsStatistics:Calculate(System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement],int) [Tier0, IL size=257, code size=1188] ; Assembly listing for method BenchmarkDotNet.Mathematics.MeasurementsStatistics:Sum(System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str xzr, [x9, #0x50] add x1, sp, #128 str x1, [fp, #0x78] str x0, [fp, #0x70] G_M000_IG02: str xzr, [fp, #0x68] add x8, fp, #56 ldr x0, [fp, #0x70] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 mov w0, #0xD1FFAB1E str w0, [fp, #0x10] G_M000_IG03: b G_M000_IG05 G_M000_IG04: add x0, fp, #56 add x8, fp, #24 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 add x0, fp, #24 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0x68] fadd d16, d0, d16 str d16, [fp, #0x68] G_M000_IG05: ldr w0, [fp, #0x10] sub w0, w0, #1 str w0, [fp, #0x10] ldr w0, [fp, #0x10] cmp w0, #0 bgt G_M000_IG07 G_M000_IG06: add x0, fp, #16 mov w1, #37 bl CORINFO_HELP_PATCHPOINT G_M000_IG07: add x0, fp, #56 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG04 b G_M000_IG08 G_M000_IG08: ldr x0, [fp, #0x78] bl G_M000_IG12 G_M000_IG09: nop G_M000_IG10: ldr d0, [fp, #0x68] G_M000_IG11: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG12: stp fp, lr, [sp, #-0x20]! add x3, fp, #128 str x3, [sp, #0x18] G_M000_IG13: add x0, fp, #56 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG14: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 292 950: JIT compiled BenchmarkDotNet.Mathematics.MeasurementsStatistics:Sum(System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]) [Tier0, IL size=64, code size=292] ; Assembly listing for method System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:GetEnumerator():System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x0, [fp, #0x48] str x8, [fp, #0x40] G_M000_IG02: add x0, fp, #16 ldr x1, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x40] add x13, fp, #16 bl CORINFO_HELP_ASSIGN_BYREF ldp x12, x15, [x13], #0x10 stp x12, x15, [x14], #0x10 ldp x12, x15, [x13], #0x10 stp x12, x15, [x14], #0x10 ldr x12, [x13], #0x08 str x12, [x14], #0x08 G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 104 951: JIT compiled System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:GetEnumerator() [Tier0, IL size=7, code size=104] ; Assembly listing for method System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:.ctor(System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] ldr x15, [fp, #0x10] bl CORINFO_HELP_CHECKED_ASSIGN_REF ldr x0, [fp, #0x18] str wzr, [x0, #0x08] ldr x0, [fp, #0x10] ldr w0, [x0, #0x14] ldr x1, [fp, #0x18] str w0, [x1, #0x0C] ldr x0, [fp, #0x18] stp xzr, xzr, [x0, #0x10] stp xzr, xzr, [x0, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 72 952: JIT compiled System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:.ctor(System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]) [Tier0, IL size=39, code size=72] ; Assembly listing for method System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:MoveNext():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0] str x0, [fp, #0x10] ldr x0, [fp, #0x18] ldr w0, [x0, #0x0C] ldr x1, [fp, #0x10] ldr w1, [x1, #0x14] cmp w0, w1 bne G_M000_IG04 ldr x0, [fp, #0x18] ldr w0, [x0, #0x08] ldr x1, [fp, #0x10] ldr w1, [x1, #0x10] cmp w0, w1 bhs G_M000_IG04 ldr x0, [fp, #0x10] ldr x0, [x0, #0x08] ldr x1, [fp, #0x18] ldr w1, [x1, #0x08] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG06 add x0, x0, x1, LSL #5 add x0, x0, #16 ldr x1, [fp, #0x18] ldp q16, q17, [x0] stp q16, q17, [x1, #0x10] ldr x0, [fp, #0x18] ldr w0, [x0, #0x08] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x08] mov w0, #1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG06: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 196 953: JIT compiled System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:MoveNext() [Tier0, IL size=81, code size=196] ; Assembly listing for method System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:get_Current():BenchmarkDotNet.Reports.Measurement:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x8, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] ldp q16, q17, [x0, #0x10] stp q16, q17, [x1] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 954: JIT compiled System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:get_Current() [Tier0, IL size=7, code size=40] ; Assembly listing for method System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:MoveNextRare():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x0C] ldr x1, [fp, #0x18] ldr x1, [x1] ldr w1, [x1, #0x14] cmp w0, w1 beq G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG03: ldr x0, [fp, #0x18] ldr x0, [x0] ldr w0, [x0, #0x10] add w0, w0, #1 ldr x1, [fp, #0x18] str w0, [x1, #0x08] ldr x0, [fp, #0x18] stp xzr, xzr, [x0, #0x10] stp xzr, xzr, [x0, #0x20] mov w0, wzr G_M000_IG04: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 108 955: JIT compiled System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:MoveNextRare() [Tier0, IL size=57, code size=108] ; Assembly listing for method System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:Dispose():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 20 956: JIT compiled System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:Dispose() [Tier0, IL size=1, code size=20] ; Assembly listing for method BenchmarkDotNet.Mathematics.MeasurementsStatistics:Variance(System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement],int,double):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! mov fp, sp add x9, fp, #40 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str xzr, [x9, #0x50] add x2, sp, #160 str x2, [fp, #0x98] str x0, [fp, #0x90] str w1, [fp, #0x8C] str d0, [fp, #0x80] G_M000_IG02: mov w8, #0xD1FFAB1E str w8, [fp, #0x18] ldr w8, [fp, #0x8C] cmp w8, #1 bne G_M000_IG04 movi v0.16b, #0 G_M000_IG03: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG04: str xzr, [fp, #0x78] add x8, fp, #72 ldr x0, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 G_M000_IG05: b G_M000_IG07 G_M000_IG06: add x0, fp, #72 add x8, fp, #40 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 add x0, fp, #40 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0x80] fsub d16, d0, d16 str d16, [fp, #0x20] add x0, fp, #40 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0x80] fsub d16, d0, d16 ldr d17, [fp, #0x20] fmul d16, d16, d17 ldr w0, [fp, #0x8C] sub w0, w0, #1 scvtf d17, w0 fdiv d16, d16, d17 ldr d17, [fp, #0x78] fadd d16, d16, d17 str d16, [fp, #0x78] G_M000_IG07: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG09 G_M000_IG08: add x0, fp, #24 mov w1, #68 bl CORINFO_HELP_PATCHPOINT G_M000_IG09: add x0, fp, #72 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG06 b G_M000_IG10 G_M000_IG10: ldr x0, [fp, #0x98] bl G_M000_IG14 G_M000_IG11: nop G_M000_IG12: ldr d0, [fp, #0x78] G_M000_IG13: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG14: stp fp, lr, [sp, #-0x20]! add x3, fp, #160 str x3, [sp, #0x18] G_M000_IG15: add x0, fp, #72 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG16: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 392 957: JIT compiled BenchmarkDotNet.Mathematics.MeasurementsStatistics:Variance(System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement],int,double) [Tier0, IL size=95, code size=392] ; Assembly listing for method Perfolizer.Mathematics.Common.ConfidenceInterval:.ctor(double,double,int,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str w1, [fp, #0x34] str w2, [fp, #0x30] str d0, [fp, #0x40] str d1, [fp, #0x38] G_M000_IG02: ldr x0, [fp, #0x48] ldr w1, [fp, #0x34] str w1, [x0] ldr x0, [fp, #0x48] ldr d16, [fp, #0x40] str d16, [x0, #0x08] ldr x0, [fp, #0x48] ldr d16, [fp, #0x38] str d16, [x0, #0x10] ldr x0, [fp, #0x48] ldr w1, [fp, #0x30] str w1, [x0, #0x18] ldr x0, [fp, #0x48] str x0, [fp, #0x28] ldr w0, [fp, #0x34] cmp w0, #2 ble G_M000_IG03 ldr x0, [fp, #0x28] str x0, [fp, #0x20] ldr w0, [fp, #0x30] ldr w1, [fp, #0x34] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr d16, [fp, #0x38] fmul d16, d0, d16 str d16, [fp, #0x18] b G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x28] str x0, [fp, #0x20] ldr d16, [@RWD00] str d16, [fp, #0x18] G_M000_IG04: ldr x0, [fp, #0x20] ldr d16, [fp, #0x18] str d16, [x0, #0x20] ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0x40] fsub d16, d16, d0 ldr x0, [fp, #0x48] str d16, [x0, #0x28] ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0x40] fadd d16, d0, d16 ldr x0, [fp, #0x48] str d16, [x0, #0x30] G_M000_IG05: ldp fp, lr, [sp], #0x50 ret lr RWD00 dq FFF8000000000000h ; -nan(ind) ; Total bytes of code 276 958: JIT compiled Perfolizer.Mathematics.Common.ConfidenceInterval:.ctor(double,double,int,int) [Tier0, IL size=89, code size=276] ; Assembly listing for method Perfolizer.Mathematics.Common.ConfidenceInterval:get_Margin():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 959: JIT compiled Perfolizer.Mathematics.Common.ConfidenceInterval:get_Margin() [Tier0, IL size=7, code size=28] ; Assembly listing for method System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:Sort():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x14] ldr w2, [fp, #0x14] ldr x0, [fp, #0x18] mov w1, wzr mov x3, xzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 960: JIT compiled System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:Sort() [Tier0, IL size=15, code size=84] ; Assembly listing for method System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:Sort(int,int,System.Collections.Generic.IComparer`1[BenchmarkDotNet.Reports.Measurement]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str w1, [fp, #0x24] str w2, [fp, #0x20] str x3, [fp, #0x18] G_M000_IG02: ldr w0, [fp, #0x24] tbz w0, #31, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG03: ldr w0, [fp, #0x20] tbz w0, #31, G_M000_IG04 mov w0, #27 mov w1, #13 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG04: ldr x0, [fp, #0x28] ldr w0, [x0, #0x10] ldr w1, [fp, #0x24] sub w0, w0, w1 ldr w1, [fp, #0x20] cmp w0, w1 bge G_M000_IG05 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG05: ldr w0, [fp, #0x20] cmp w0, #1 ble G_M000_IG06 ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] ldr w1, [fp, #0x24] ldr w2, [fp, #0x20] ldr x3, [fp, #0x18] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG06: ldr x0, [fp, #0x28] ldr w0, [x0, #0x14] add w0, w0, #1 ldr x1, [fp, #0x28] str w0, [x1, #0x14] G_M000_IG07: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 220 961: JIT compiled System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:Sort(int,int,System.Collections.Generic.IComparer`1[BenchmarkDotNet.Reports.Measurement]) [Tier0, IL size=73, code size=220] ; Assembly listing for method BenchmarkDotNet.Mathematics.MeasurementsStatistics:SumWithoutOutliers(int,System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement],double,double,byref,byref) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0xB0]! mov fp, sp add x9, fp, #40 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] add x4, sp, #176 str x4, [fp, #0xA8] str w0, [fp, #0xA4] str x1, [fp, #0x98] str x2, [fp, #0x80] str x3, [fp, #0x78] str d0, [fp, #0x90] str d1, [fp, #0x88] G_M000_IG02: ldr x8, [fp, #0x80] str xzr, [x8] ldr x8, [fp, #0x78] str wzr, [x8] add x8, fp, #72 ldr x0, [fp, #0x98] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 mov w0, #0xD1FFAB1E str w0, [fp, #0x18] G_M000_IG03: b G_M000_IG05 G_M000_IG04: add x0, fp, #72 add x8, fp, #40 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 add x0, fp, #40 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x10] ldr d0, [fp, #0x10] ldr w0, [fp, #0xA4] ldr d1, [fp, #0x90] ldr d2, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG05 ldr x0, [fp, #0x80] ldr d16, [x0] str d16, [fp, #0x20] add x0, fp, #40 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0x20] fadd d16, d0, d16 ldr x0, [fp, #0x80] str d16, [x0] ldr x0, [fp, #0x78] ldr w0, [x0] add w0, w0, #1 ldr x1, [fp, #0x78] str w0, [x1] G_M000_IG05: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG07 G_M000_IG06: add x0, fp, #24 mov w1, #72 bl CORINFO_HELP_PATCHPOINT G_M000_IG07: add x0, fp, #72 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG04 b G_M000_IG08 G_M000_IG08: ldr x0, [fp, #0xA8] bl G_M000_IG11 G_M000_IG09: nop G_M000_IG10: ldp fp, lr, [sp], #0xB0 ret lr G_M000_IG11: stp fp, lr, [sp, #-0x20]! add x3, fp, #176 str x3, [sp, #0x18] G_M000_IG12: add x0, fp, #72 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG13: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 420 962: JIT compiled BenchmarkDotNet.Mathematics.MeasurementsStatistics:SumWithoutOutliers(int,System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement],double,double,byref,byref) [Tier0, IL size=98, code size=420] ; Assembly listing for method BenchmarkDotNet.Mathematics.MeasurementsStatistics:IsOutlier(int,double,double,double):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x10] str w0, [fp, #0x4C] str d0, [fp, #0x40] str d1, [fp, #0x38] str d2, [fp, #0x30] G_M000_IG02: ldr w0, [fp, #0x4C] cmp w0, #3 bhi G_M000_IG03 ldr w0, [fp, #0x4C] mov w0, w0 adr x1, [@RWD00] ldr w1, [x1, x0, LSL #2] adr x2, [G_M000_IG02] add x1, x1, x2 br x1 G_M000_IG03: b G_M000_IG13 G_M000_IG04: b G_M000_IG05 G_M000_IG05: mov w0, wzr G_M000_IG06: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG07: ldr d16, [fp, #0x40] ldr d17, [fp, #0x30] fcmp d16, d17 cset x0, gt str w0, [fp, #0x1C] b G_M000_IG14 G_M000_IG08: ldr d16, [fp, #0x40] ldr d17, [fp, #0x38] fcmp d16, d17 cset x0, lo str w0, [fp, #0x1C] b G_M000_IG14 G_M000_IG09: ldr d16, [fp, #0x40] ldr d17, [fp, #0x38] fcmp d16, d17 blo G_M000_IG10 ldr d16, [fp, #0x40] ldr d17, [fp, #0x30] fcmp d16, d17 cset x0, gt str w0, [fp, #0x1C] b G_M000_IG14 G_M000_IG10: b G_M000_IG11 G_M000_IG11: mov w0, #1 G_M000_IG12: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG13: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr w1, [fp, #0x4C] str w1, [x0, #0x08] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x10] ldr x1, [fp, #0x10] ldr x2, [fp, #0x28] ldr x0, [fp, #0x20] mov x3, xzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x20] bl CORINFO_HELP_THROW G_M000_IG14: ldr w0, [fp, #0x1C] uxtb w0, w0 G_M000_IG15: ldp fp, lr, [sp], #0x50 ret lr RWD00 dd G_M000_IG04 - G_M000_IG02 dd G_M000_IG07 - G_M000_IG02 dd G_M000_IG08 - G_M000_IG02 dd G_M000_IG09 - G_M000_IG02 ; Total bytes of code 336 963: JIT compiled BenchmarkDotNet.Mathematics.MeasurementsStatistics:IsOutlier(int,double,double,double) [Tier0, IL size=65, code size=336] ; Assembly listing for method BenchmarkDotNet.Mathematics.MeasurementsStatistics:VarianceWithoutOutliers(int,System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement],int,double,double,double):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0xC0]! mov fp, sp add x9, fp, #48 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str xzr, [x9, #0x50] add x3, sp, #192 str x3, [fp, #0xB8] str w0, [fp, #0xB4] str x1, [fp, #0xA8] str w2, [fp, #0xA4] str d0, [fp, #0x98] str d1, [fp, #0x90] str d2, [fp, #0x88] G_M000_IG02: mov w8, #0xD1FFAB1E str w8, [fp, #0x20] ldr w8, [fp, #0xA4] cmp w8, #1 bne G_M000_IG04 movi v0.16b, #0 G_M000_IG03: ldp fp, lr, [sp], #0xC0 ret lr G_M000_IG04: str xzr, [fp, #0x80] add x8, fp, #80 ldr x0, [fp, #0xA8] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 G_M000_IG05: b G_M000_IG07 G_M000_IG06: add x0, fp, #80 add x8, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x18] ldr d0, [fp, #0x18] ldr w0, [fp, #0xB4] ldr d1, [fp, #0x90] ldr d2, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG07 add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0x98] fsub d16, d0, d16 str d16, [fp, #0x28] add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0x98] fsub d16, d0, d16 ldr d17, [fp, #0x28] fmul d16, d16, d17 ldr w0, [fp, #0xA4] sub w0, w0, #1 scvtf d17, w0 fdiv d16, d16, d17 ldr d17, [fp, #0x80] fadd d16, d16, d17 str d16, [fp, #0x80] G_M000_IG07: ldr w0, [fp, #0x20] sub w0, w0, #1 str w0, [fp, #0x20] ldr w0, [fp, #0x20] cmp w0, #0 bgt G_M000_IG09 G_M000_IG08: add x0, fp, #32 mov w1, #87 bl CORINFO_HELP_PATCHPOINT G_M000_IG09: add x0, fp, #80 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG06 b G_M000_IG10 G_M000_IG10: ldr x0, [fp, #0xB8] bl G_M000_IG14 G_M000_IG11: nop G_M000_IG12: ldr d0, [fp, #0x80] G_M000_IG13: ldp fp, lr, [sp], #0xC0 ret lr G_M000_IG14: stp fp, lr, [sp, #-0x20]! add x3, fp, #192 str x3, [sp, #0x18] G_M000_IG15: add x0, fp, #80 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG16: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 472 964: JIT compiled BenchmarkDotNet.Mathematics.MeasurementsStatistics:VarianceWithoutOutliers(int,System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement],int,double,double,double) [Tier0, IL size=114, code size=472] ; Assembly listing for method BenchmarkDotNet.Mathematics.MeasurementsStatistics:.ctor(double,double,Perfolizer.Mathematics.Common.ConfidenceInterval):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x10] str d0, [fp, #0x20] str d1, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x28] ldr d16, [fp, #0x20] str d16, [x0] ldr x0, [fp, #0x28] ldr d16, [fp, #0x18] str d16, [x0, #0x08] ldr x0, [fp, #0x10] ldr x1, [fp, #0x28] ldp q16, q17, [x0] stp q16, q17, [x1, #0x10] ldr q16, [x0, #0x20] str q16, [x1, #0x30] ldr x2, [x0, #0x30] str x2, [x1, #0x40] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 88 965: JIT compiled BenchmarkDotNet.Mathematics.MeasurementsStatistics:.ctor(double,double,Perfolizer.Mathematics.Common.ConfidenceInterval) [Tier0, IL size=22, code size=88] ; Assembly listing for method BenchmarkDotNet.Mathematics.MeasurementsStatistics:get_ConfidenceInterval():Perfolizer.Mathematics.Common.ConfidenceInterval:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x8, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] ldp q16, q17, [x0, #0x10] stp q16, q17, [x1] ldr q16, [x0, #0x30] str q16, [x1, #0x20] ldr x2, [x0, #0x40] str x2, [x1, #0x30] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 966: JIT compiled BenchmarkDotNet.Mathematics.MeasurementsStatistics:get_ConfidenceInterval() [Tier0, IL size=7, code size=56] ; Assembly listing for method BenchmarkDotNet.Mathematics.MeasurementsStatistics:get_Mean():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 967: JIT compiled BenchmarkDotNet.Mathematics.MeasurementsStatistics:get_Mean() [Tier0, IL size=7, code size=28] ; Assembly listing for method System.Nullable`1[Perfolizer.Horology.TimeInterval]:get_HasValue():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldrb w0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 968: JIT compiled System.Nullable`1[Perfolizer.Horology.TimeInterval]:get_HasValue() [Tier0, IL size=7, code size=28] ; Assembly listing for method System.Array:Sort[BenchmarkDotNet.Reports.Measurement](BenchmarkDotNet.Reports.Measurement[],int,int,System.Collections.Generic.IComparer`1[BenchmarkDotNet.Reports.Measurement]) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x0, [fp, #0x58] str w1, [fp, #0x54] str w2, [fp, #0x50] str x3, [fp, #0x48] G_M000_IG02: ldr x0, [fp, #0x58] cbnz x0, G_M000_IG03 mov w0, #2 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr w0, [fp, #0x54] tbz w0, #31, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG04: ldr w0, [fp, #0x50] tbz w0, #31, G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG05: ldr x0, [fp, #0x58] ldr w0, [x0, #0x08] ldr w1, [fp, #0x54] sub w0, w0, w1 ldr w1, [fp, #0x50] cmp w0, w1 bge G_M000_IG06 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG06: ldr w0, [fp, #0x50] cmp w0, #1 ble G_M000_IG09 stp xzr, xzr, [fp, #0x28] ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w1, [fp, #0x54] sxtw x1, w1 lsl x1, x1, #5 add x1, x0, x1 str x1, [fp, #0x20] ldr x1, [fp, #0x20] add x0, fp, #40 ldr w2, [fp, #0x50] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG07: ldp x0, x1, [fp, #0x28] stp x0, x1, [fp, #0x38] G_M000_IG08: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x38] ldr x2, [fp, #0x40] ldr x3, [fp, #0x48] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x4, [x11] blr x4 G_M000_IG09: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 348 969: JIT compiled System.Array:Sort[BenchmarkDotNet.Reports.Measurement](BenchmarkDotNet.Reports.Measurement[],int,int,System.Collections.Generic.IComparer`1[BenchmarkDotNet.Reports.Measurement]) [Tier0, IL size=78, code size=348] ; Assembly listing for method System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[BenchmarkDotNet.Reports.Measurement](BenchmarkDotNet.Reports.Measurement[]):byref ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldrsb wzr, [x0] ldr x0, [fp, #0x18] mov x1, xzr add x0, x0, x1, LSL #5 add x0, x0, #16 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 970: JIT compiled System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[BenchmarkDotNet.Reports.Measurement](BenchmarkDotNet.Reports.Measurement[]) [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Span`1[BenchmarkDotNet.Reports.Measurement]:.ctor(byref,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] G_M000_IG02: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] str x1, [x0] ldr x0, [fp, #0x28] ldr w1, [fp, #0x1C] str w1, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 52 971: JIT compiled System.Span`1[BenchmarkDotNet.Reports.Measurement]:.ctor(byref,int) [Tier0, IL size=15, code size=52] ; Assembly listing for method System.Collections.Generic.ArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:get_Default():System.Collections.Generic.IArraySortHelper`1[BenchmarkDotNet.Reports.Measurement] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #49 bl CORINFO_HELP_CLASSINIT_SHARED_DYNAMICCLASS movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 52 972: JIT compiled System.Collections.Generic.ArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:get_Default() [Tier0, IL size=6, code size=52] ; Assembly listing for method System.Collections.Generic.ArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 56 973: JIT compiled System.Collections.Generic.ArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:.cctor() [Tier0, IL size=11, code size=56] ; Assembly listing for method System.Collections.Generic.ArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:CreateArraySortHelper():System.Collections.Generic.IArraySortHelper`1[BenchmarkDotNet.Reports.Measurement] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x10] ldr x1, [fp, #0x10] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x28] b G_M000_IG03 G_M000_IG03: ldr x0, [fp, #0x28] G_M000_IG04: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 208 974: JIT compiled System.Collections.Generic.ArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:CreateArraySortHelper() [Tier0, IL size=78, code size=208] ; Assembly listing for method System.Collections.Generic.GenericArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 975: JIT compiled System.Collections.Generic.GenericArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Collections.Generic.GenericArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:Sort(System.Span`1[BenchmarkDotNet.Reports.Measurement],System.Collections.Generic.IComparer`1[BenchmarkDotNet.Reports.Measurement]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! mov fp, sp add x9, fp, #32 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] add x4, sp, #160 str x4, [fp, #0x98] str x0, [fp, #0x90] str x1, [fp, #0x80] str x2, [fp, #0x88] str x3, [fp, #0x78] G_M000_IG02: ldr x0, [fp, #0x78] cbz x0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr x1, [fp, #0x78] cmp x0, x1 bne G_M000_IG06 G_M000_IG03: ldr w0, [fp, #0x88] cmp w0, #1 ble G_M000_IG09 b G_M000_IG04 G_M000_IG04: ldp x0, x1, [fp, #0x80] stp x0, x1, [fp, #0x48] G_M000_IG05: ldr w0, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 lsl w2, w0, #1 add w2, w2, #2 str w2, [fp, #0x1C] ldr w2, [fp, #0x1C] ldr x0, [fp, #0x48] ldr x1, [fp, #0x50] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG09 G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x40] G_M000_IG07: ldp x0, x1, [fp, #0x80] stp x0, x1, [fp, #0x30] G_M000_IG08: ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x10] ldr x2, [fp, #0x10] ldr x1, [fp, #0x78] ldr x0, [fp, #0x40] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x30] ldr x1, [fp, #0x38] ldr x2, [fp, #0x40] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG09: b G_M000_IG10 G_M000_IG10: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG11: stp fp, lr, [sp, #-0x20]! add x3, fp, #160 str x3, [sp, #0x18] G_M000_IG12: str x0, [fp, #0x20] ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 adr x0, [G_M000_IG10] G_M000_IG13: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG14: stp fp, lr, [sp, #-0x20]! add x3, fp, #160 str x3, [sp, #0x18] G_M000_IG15: str x0, [fp, #0x28] ldr x1, [fp, #0x28] str x1, [fp, #0x58] ldr x1, [fp, #0x58] mov w0, #64 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 adr x0, [G_M000_IG10] G_M000_IG16: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 444 976: JIT compiled System.Collections.Generic.GenericArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:Sort(System.Span`1[BenchmarkDotNet.Reports.Measurement],System.Collections.Generic.IComparer`1[BenchmarkDotNet.Reports.Measurement]) [Tier0, IL size=212, code size=444] ; Assembly listing for method System.Collections.Generic.GenericArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:IntroSort(System.Span`1[BenchmarkDotNet.Reports.Measurement],int) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! mov fp, sp add x9, fp, #32 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] str x0, [fp, #0x90] str x1, [fp, #0x98] str w2, [fp, #0x8C] G_M000_IG02: ldr w0, [fp, #0x98] str w0, [fp, #0x88] mov w0, #0xD1FFAB1E str w0, [fp, #0x18] b G_M000_IG08 G_M000_IG03: ldr w1, [fp, #0x88] cmp w1, #16 bgt G_M000_IG06 ldr w1, [fp, #0x88] cmp w1, #2 bne G_M000_IG04 ldr w1, [fp, #0x98] cmp w1, #1 bls G_M000_IG12 ldr x1, [fp, #0x90] add x1, x1, #32 ldr w0, [fp, #0x98] cmp w0, #0 bls G_M000_IG12 ldr x0, [fp, #0x90] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG11 G_M000_IG04: ldr w0, [fp, #0x88] cmp w0, #3 bne G_M000_IG05 ldr w0, [fp, #0x98] cmp w0, #2 bls G_M000_IG12 ldr x0, [fp, #0x90] mov x1, #32 lsl x1, x1, #1 add x0, x0, x1 str x0, [fp, #0x78] ldr w0, [fp, #0x98] cmp w0, #1 bls G_M000_IG12 ldr x0, [fp, #0x90] add x0, x0, #32 str x0, [fp, #0x70] ldr w0, [fp, #0x98] cmp w0, #0 bls G_M000_IG12 ldr x0, [fp, #0x90] str x0, [fp, #0x68] ldr x0, [fp, #0x68] ldr x1, [fp, #0x70] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x68] ldr x1, [fp, #0x78] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x70] ldr x1, [fp, #0x78] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG11 G_M000_IG05: add x0, fp, #144 ldr w2, [fp, #0x88] mov w1, wzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x20] str x1, [fp, #0x28] ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG11 G_M000_IG06: ldr w0, [fp, #0x8C] cbnz w0, G_M000_IG07 add x0, fp, #144 ldr w2, [fp, #0x88] mov w1, wzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x30] str x1, [fp, #0x38] ldr x0, [fp, #0x30] ldr x1, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG11 G_M000_IG07: ldr w0, [fp, #0x8C] sub w0, w0, #1 str w0, [fp, #0x8C] add x0, fp, #144 ldr w2, [fp, #0x88] mov w1, wzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x50] str x1, [fp, #0x58] ldr x0, [fp, #0x50] ldr x1, [fp, #0x58] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x84] ldr w2, [fp, #0x84] add w2, w2, #1 str w2, [fp, #0x64] ldr w2, [fp, #0x88] ldr w0, [fp, #0x64] sub w2, w2, w0 add x0, fp, #144 ldr w1, [fp, #0x64] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x40] str x1, [fp, #0x48] ldr x0, [fp, #0x40] ldr x1, [fp, #0x48] ldr w2, [fp, #0x8C] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr w0, [fp, #0x84] str w0, [fp, #0x88] G_M000_IG08: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG10 G_M000_IG09: add x0, fp, #24 mov w1, #179 bl CORINFO_HELP_PATCHPOINT G_M000_IG10: ldr w1, [fp, #0x88] cmp w1, #1 bgt G_M000_IG03 b G_M000_IG11 G_M000_IG11: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG12: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 724 977: JIT compiled System.Collections.Generic.GenericArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:IntroSort(System.Span`1[BenchmarkDotNet.Reports.Measurement],int) [Tier0, IL size=187, code size=724] ; Assembly listing for method System.Collections.Generic.GenericArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:SwapIfGreater(byref,byref) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldrsb wzr, [x0] mov w0, #1 cbz w0, G_M000_IG03 ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG03 ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 100 978: JIT compiled System.Collections.Generic.GenericArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:SwapIfGreater(byref,byref) [Tier0, IL size=30, code size=100] ; Assembly listing for method System.Collections.Generic.GenericArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:GreaterThan(byref,byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] G_M000_IG02: b G_M000_IG03 G_M000_IG03: b G_M000_IG04 G_M000_IG04: b G_M000_IG05 G_M000_IG05: b G_M000_IG06 G_M000_IG06: b G_M000_IG07 G_M000_IG07: b G_M000_IG08 G_M000_IG08: b G_M000_IG09 G_M000_IG09: b G_M000_IG10 G_M000_IG10: b G_M000_IG11 G_M000_IG11: b G_M000_IG12 G_M000_IG12: b G_M000_IG13 G_M000_IG13: b G_M000_IG14 G_M000_IG14: b G_M000_IG15 G_M000_IG15: ldr x0, [fp, #0x48] str x0, [fp, #0x18] ldr x0, [fp, #0x40] ldp q16, q17, [x0] stp q16, q17, [fp, #0x20] ldr x0, [fp, #0x18] add x1, fp, #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cmp w0, #0 bgt G_M000_IG17 mov w0, wzr G_M000_IG16: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG17: mov w0, #1 G_M000_IG18: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 152 979: JIT compiled System.Collections.Generic.GenericArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:GreaterThan(byref,byref) [Tier0, IL size=834, code size=152] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:CompareTo(BenchmarkDotNet.Reports.Measurement):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x18] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x10] ldr d0, [fp, #0x10] add x0, fp, #24 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 112 980: JIT compiled BenchmarkDotNet.Reports.Measurement:CompareTo(BenchmarkDotNet.Reports.Measurement) [Tier0, IL size=22, code size=112] ; Assembly listing for method System.Collections.Generic.GenericArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:Swap(byref,byref) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x1, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x38] ldp q16, q17, [x0] stp q16, q17, [fp, #0x10] ldr x0, [fp, #0x30] ldr x1, [fp, #0x38] ldp q16, q17, [x0] stp q16, q17, [x1] ldr x0, [fp, #0x30] ldp q16, q17, [fp, #0x10] stp q16, q17, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 64 981: JIT compiled System.Collections.Generic.GenericArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:Swap(byref,byref) [Tier0, IL size=27, code size=64] ; Assembly listing for method BenchmarkDotNet.Mathematics.MeasurementsStatistics:GetQuartile(System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement],int):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x28] str xzr, [fp, #0x30] str xzr, [fp, #0x38] str x0, [fp, #0x48] str w1, [fp, #0x44] G_M000_IG02: ldr w1, [fp, #0x44] lsr w1, w1, #31 ldr w8, [fp, #0x44] add w1, w1, w8 asr w1, w1, #1 lsl w1, w1, #1 ldr w8, [fp, #0x44] sub w1, w8, w1 cbnz w1, G_M000_IG04 ldr w1, [fp, #0x44] lsr w1, w1, #31 ldr w8, [fp, #0x44] add w1, w1, w8 asr w1, w1, #1 sub w1, w1, #1 add x8, fp, #32 ldr x0, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 add x0, fp, #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x18] ldr w1, [fp, #0x44] lsr w1, w1, #31 ldr w8, [fp, #0x44] add w1, w1, w8 asr w1, w1, #1 add x8, fp, #32 ldr x0, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 add x0, fp, #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0x18] fadd d0, d0, d16 fmov d16, #0.5000 fmul d0, d0, d16 G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG04: ldr w1, [fp, #0x44] lsr w1, w1, #31 ldr w8, [fp, #0x44] add w1, w1, w8 asr w1, w1, #1 add x8, fp, #32 ldr x0, [fp, #0x48] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 add x0, fp, #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG05: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 336 982: JIT compiled BenchmarkDotNet.Mathematics.MeasurementsStatistics:GetQuartile(System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement],int) [Tier0, IL size=71, code size=336] ; Assembly listing for method Perfolizer.Mathematics.Common.ConfidenceLevelExtensions:GetZValue(int,int):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x30] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str w0, [fp, #0x3C] str w1, [fp, #0x38] G_M000_IG02: ldr w0, [fp, #0x38] cmp w0, #1 bgt G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x20] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] ldr x0, [fp, #0x30] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x30] bl CORINFO_HELP_THROW G_M000_IG04: ldr w0, [fp, #0x3C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 fmov d1, #1.0000 fsub d0, d1, d0 str d0, [fp, #0x18] ldr d0, [fp, #0x18] ldr w0, [fp, #0x38] sub w0, w0, #1 scvtf d1, w0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG05: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 228 983: JIT compiled Perfolizer.Mathematics.Common.ConfidenceLevelExtensions:GetZValue(int,int) [Tier0, IL size=46, code size=228] ; Assembly listing for method Perfolizer.Mathematics.Common.ConfidenceLevelExtensions:ToPercent(int):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str wzr, [fp, #0x28] str wzr, [fp, #0x24] str xzr, [fp, #0x10] str w0, [fp, #0x2C] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #66 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr w1, [fp, #0x2C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 str x0, [fp, #0x18] ldr w0, [fp, #0x18] str w0, [fp, #0x28] ldr w0, [fp, #0x1C] str w0, [fp, #0x24] ldr w0, [fp, #0x24] scvtf d1, w0 fmov d0, #10.0000 bl System.Math:Pow(double,double):double ldr w0, [fp, #0x28] scvtf d16, w0 fdiv d0, d16, d0 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 152 984: JIT compiled Perfolizer.Mathematics.Common.ConfidenceLevelExtensions:ToPercent(int) [Tier0, IL size=44, code size=152] ; Assembly listing for method Perfolizer.Mathematics.Common.ConfidenceLevelExtensions:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 56 985: JIT compiled Perfolizer.Mathematics.Common.ConfidenceLevelExtensions:.cctor() [Tier0, IL size=11, code size=56] ; Assembly listing for method Perfolizer.Mathematics.Common.ConfidenceLevelExtensions:CreateConfidenceLevelMapping():System.Collections.Generic.Dictionary`2[int,System.ValueTuple`2[int,int]] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x60] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #114 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x68] ldr x0, [fp, #0x60] str x0, [fp, #0x58] ldr x0, [fp, #0x68] str x0, [fp, #0x50] ldr x0, [fp, #0x68] cbnz x0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #114 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #114 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x20] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x20] str x0, [fp, #0x50] G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #114 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x48] ldr x0, [fp, #0x58] str x0, [fp, #0x40] ldr x0, [fp, #0x50] str x0, [fp, #0x38] ldr x0, [fp, #0x48] str x0, [fp, #0x30] ldr x0, [fp, #0x48] cbnz x0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #114 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #114 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x28] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x28] str x0, [fp, #0x30] G_M000_IG04: ldr x0, [fp, #0x40] ldr x1, [fp, #0x38] ldr x2, [fp, #0x30] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG05: ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 556 986: JIT compiled Perfolizer.Mathematics.Common.ConfidenceLevelExtensions:CreateConfidenceLevelMapping() [Tier0, IL size=88, code size=556] ; Assembly listing for method System.Linq.Enumerable:Cast[int](System.Collections.IEnumerable):System.Collections.Generic.IEnumerable`1[int] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x10] ldr x0, [fp, #0x10] cbz x0, G_M000_IG04 ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: ldr x0, [fp, #0x18] cbnz x0, G_M000_IG05 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG05: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG06: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 140 987: JIT compiled System.Linq.Enumerable:Cast[int](System.Collections.IEnumerable) [Tier0, IL size=29, code size=140] ; Assembly listing for method Perfolizer.Mathematics.Common.ConfidenceLevelExtensions+<>c:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 988: JIT compiled Perfolizer.Mathematics.Common.ConfidenceLevelExtensions+<>c:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method Perfolizer.Mathematics.Common.ConfidenceLevelExtensions+<>c:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 989: JIT compiled Perfolizer.Mathematics.Common.ConfidenceLevelExtensions+<>c:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Linq.Enumerable:ToDictionary[int,int,System.ValueTuple`2[int,int]](System.Collections.Generic.IEnumerable`1[int],System.Func`2[int,int],System.Func`2[int,System.ValueTuple`2[int,int]]):System.Collections.Generic.Dictionary`2[int,System.ValueTuple`2[int,int]] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] ldr x2, [fp, #0x18] mov x3, xzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 64 990: JIT compiled System.Linq.Enumerable:ToDictionary[int,int,System.ValueTuple`2[int,int]](System.Collections.Generic.IEnumerable`1[int],System.Func`2[int,int],System.Func`2[int,System.ValueTuple`2[int,int]]) [Tier0, IL size=10, code size=64] ; Assembly listing for method System.Linq.Enumerable:ToDictionary[int,int,System.ValueTuple`2[int,int]](System.Collections.Generic.IEnumerable`1[int],System.Func`2[int,int],System.Func`2[int,System.ValueTuple`2[int,int]],System.Collections.Generic.IEqualityComparer`1[int]):System.Collections.Generic.Dictionary`2[int,System.ValueTuple`2[int,int]] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! mov fp, sp add x9, fp, #32 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] add x4, sp, #160 str x4, [fp, #0x98] str x0, [fp, #0x90] str x1, [fp, #0x88] str x2, [fp, #0x80] str x3, [fp, #0x78] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x18] ldr x0, [fp, #0x90] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x88] cbnz x0, G_M000_IG04 mov w0, #9 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldr x0, [fp, #0x80] cbnz x0, G_M000_IG05 mov w0, #2 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG05: str wzr, [fp, #0x74] ldr x1, [fp, #0x90] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x68] ldr x0, [fp, #0x68] cbz x0, G_M000_IG11 ldr x0, [fp, #0x68] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str w0, [fp, #0x74] ldr w0, [fp, #0x74] cbnz w0, G_M000_IG07 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x78] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x20] G_M000_IG06: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG07: ldr x1, [fp, #0x68] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x58] ldr x0, [fp, #0x58] cbz x0, G_M000_IG09 ldr x0, [fp, #0x58] ldr x1, [fp, #0x88] ldr x2, [fp, #0x80] ldr x3, [fp, #0x78] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG08: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG09: ldr x1, [fp, #0x68] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x50] ldr x0, [fp, #0x50] cbz x0, G_M000_IG11 ldr x0, [fp, #0x50] ldr x1, [fp, #0x88] ldr x2, [fp, #0x80] ldr x3, [fp, #0x78] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG10: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG11: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] ldr x0, [fp, #0x38] ldr w1, [fp, #0x74] ldr x2, [fp, #0x78] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x38] str x0, [fp, #0x60] ldr x0, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x48] G_M000_IG12: b G_M000_IG14 G_M000_IG13: ldr x0, [fp, #0x48] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str w0, [fp, #0x44] ldr x0, [fp, #0x88] ldr x0, [x0, #0x08] ldr w1, [fp, #0x44] ldr x2, [fp, #0x88] ldr x2, [x2, #0x18] blr x2 str w0, [fp, #0x34] ldr x0, [fp, #0x80] ldr x0, [x0, #0x08] ldr w1, [fp, #0x44] ldr x2, [fp, #0x80] ldr x2, [x2, #0x18] blr x2 str x0, [fp, #0x28] ldr x0, [fp, #0x60] ldr w1, [fp, #0x34] ldr x2, [fp, #0x28] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG14: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG16 G_M000_IG15: add x0, fp, #24 mov w1, #150 bl CORINFO_HELP_PATCHPOINT G_M000_IG16: ldr x0, [fp, #0x48] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG13 b G_M000_IG17 G_M000_IG17: ldr x0, [fp, #0x98] bl G_M000_IG21 G_M000_IG18: nop G_M000_IG19: ldr x0, [fp, #0x60] G_M000_IG20: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG21: stp fp, lr, [sp, #-0x20]! add x3, fp, #160 str x3, [sp, #0x18] G_M000_IG22: ldr x0, [fp, #0x48] cbz x0, G_M000_IG23 ldr x0, [fp, #0x48] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG23: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 844 991: JIT compiled System.Linq.Enumerable:ToDictionary[int,int,System.ValueTuple`2[int,int]](System.Collections.Generic.IEnumerable`1[int],System.Func`2[int,int],System.Func`2[int,System.ValueTuple`2[int,int]],System.Collections.Generic.IEqualityComparer`1[int]) [Tier0, IL size=175, code size=844] ; Assembly listing for method System.SZArrayHelper:get_Count[int]():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr w0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 992: JIT compiled System.SZArrayHelper:get_Count[int]() [Tier0, IL size=11, code size=40] ; Assembly listing for method System.Linq.Enumerable:ToDictionary[int,int,System.ValueTuple`2[int,int]](int[],System.Func`2[int,int],System.Func`2[int,System.ValueTuple`2[int,int]],System.Collections.Generic.IEqualityComparer`1[int]):System.Collections.Generic.Dictionary`2[int,System.ValueTuple`2[int,int]] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str xzr, [fp, #0x38] str xzr, [fp, #0x28] str x0, [fp, #0x58] str x1, [fp, #0x50] str x2, [fp, #0x48] str x3, [fp, #0x40] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x1, [fp, #0x58] ldr w1, [x1, #0x08] ldr x0, [fp, #0x28] ldr x2, [fp, #0x40] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x28] str x0, [fp, #0x38] str wzr, [fp, #0x34] mov w0, #0xD1FFAB1E str w0, [fp, #0x10] b G_M000_IG04 G_M000_IG03: ldr x1, [fp, #0x58] ldr w0, [fp, #0x34] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG08 add x1, x1, x0, LSL #2 add x1, x1, #16 ldr w1, [x1] ldr x0, [fp, #0x50] ldr x0, [x0, #0x08] ldr x2, [fp, #0x50] ldr x2, [x2, #0x18] blr x2 str w0, [fp, #0x24] ldr x1, [fp, #0x58] ldr w0, [fp, #0x34] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG08 add x1, x1, x0, LSL #2 add x1, x1, #16 ldr w1, [x1] ldr x0, [fp, #0x48] ldr x0, [x0, #0x08] ldr x2, [fp, #0x48] ldr x2, [x2, #0x18] blr x2 str x0, [fp, #0x18] ldr x0, [fp, #0x38] ldr w1, [fp, #0x24] ldr x2, [fp, #0x18] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 ldr w0, [fp, #0x34] add w0, w0, #1 str w0, [fp, #0x34] G_M000_IG04: ldr w0, [fp, #0x10] sub w0, w0, #1 str w0, [fp, #0x10] ldr w0, [fp, #0x10] cmp w0, #0 bgt G_M000_IG06 G_M000_IG05: add x0, fp, #16 mov w1, #50 bl CORINFO_HELP_PATCHPOINT G_M000_IG06: ldr w1, [fp, #0x34] ldr x0, [fp, #0x58] ldr w0, [x0, #0x08] cmp w1, w0 blt G_M000_IG03 ldr x0, [fp, #0x38] G_M000_IG07: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG08: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 348 993: JIT compiled System.Linq.Enumerable:ToDictionary[int,int,System.ValueTuple`2[int,int]](int[],System.Func`2[int,int],System.Func`2[int,System.ValueTuple`2[int,int]],System.Collections.Generic.IEqualityComparer`1[int]) [Tier0, IL size=58, code size=348] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.ValueTuple`2[int,int]]:.ctor(int,System.Collections.Generic.IEqualityComparer`1[int]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str w1, [fp, #0x24] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w0, [fp, #0x24] tbz w0, #31, G_M000_IG03 mov w0, #22 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr w0, [fp, #0x24] cmp w0, #0 ble G_M000_IG04 ldr x0, [fp, #0x28] ldr w1, [fp, #0x24] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG04: b G_M000_IG05 G_M000_IG05: ldr x0, [fp, #0x18] cbz x0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr x14, [fp, #0x18] cmp x0, x14 beq G_M000_IG06 ldr x14, [fp, #0x28] add x14, x14, #24 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 188 994: JIT compiled System.Collections.Generic.Dictionary`2[int,System.ValueTuple`2[int,int]]:.ctor(int,System.Collections.Generic.IEqualityComparer`1[int]) [Tier0, IL size=136, code size=188] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.ValueTuple`2[int,int]]:Initialize(int):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: ldr w0, [fp, #0x24] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x20] ldr w1, [fp, #0x20] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x18] ldr w1, [fp, #0x20] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x10] ldr x0, [fp, #0x28] movn w1, #0 str w1, [x0, #0x3C] ldr w0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] str x0, [x14, #0x30] ldr x14, [fp, #0x28] add x14, x14, #8 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x28] add x14, x14, #16 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF ldr w0, [fp, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 196 995: JIT compiled System.Collections.Generic.Dictionary`2[int,System.ValueTuple`2[int,int]]:Initialize(int) [Tier0, IL size=56, code size=196] ; Assembly listing for method Perfolizer.Mathematics.Common.ConfidenceLevelExtensions+<>c:b__4_0(int):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr w0, [fp, #0x14] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 996: JIT compiled Perfolizer.Mathematics.Common.ConfidenceLevelExtensions+<>c:b__4_0(int) [Tier0, IL size=2, code size=28] ; Assembly listing for method Perfolizer.Mathematics.Common.ConfidenceLevelExtensions+<>c:b__4_1(int):System.ValueTuple`2[int,int]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x38] str xzr, [fp, #0x30] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x48] str w1, [fp, #0x44] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] ldr x0, [fp, #0x30] ldr w1, [fp, #0x44] str w1, [x0, #0x08] ldr x0, [fp, #0x30] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x20] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x08] blr x1 str x0, [fp, #0x18] ldr x0, [fp, #0x18] mov w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 str x0, [fp, #0x38] str xzr, [fp, #0x28] ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x14] ldr w1, [fp, #0x14] ldr x2, [fp, #0x38] ldr w2, [x2, #0x08] add x0, fp, #40 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x28] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 216 997: JIT compiled Perfolizer.Mathematics.Common.ConfidenceLevelExtensions+<>c:b__4_1(int) [Tier0, IL size=38, code size=216] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.ValueTuple`2[int,int]]:Add(int,System.ValueTuple`2[int,int]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str w1, [fp, #0x24] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x28] ldr w1, [fp, #0x24] ldr x2, [fp, #0x18] mov w3, #2 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 str w0, [fp, #0x14] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 68 998: JIT compiled System.Collections.Generic.Dictionary`2[int,System.ValueTuple`2[int,int]]:Add(int,System.ValueTuple`2[int,int]) [Tier0, IL size=11, code size=68] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.ValueTuple`2[int,int]]:TryInsert(int,System.ValueTuple`2[int,int],ubyte):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] str xzr, [x9, #0x40] str x0, [fp, #0x78] str w1, [fp, #0x74] str x2, [fp, #0x68] str w3, [fp, #0x64] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x20] b G_M000_IG03 G_M000_IG03: ldr x0, [fp, #0x78] ldr x0, [x0, #0x08] cbnz x0, G_M000_IG04 ldr x0, [fp, #0x78] mov w1, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG04: ldr x0, [fp, #0x78] ldr x0, [x0, #0x10] str x0, [fp, #0x58] ldr x0, [fp, #0x78] ldr x0, [x0, #0x18] str x0, [fp, #0x50] ldr x0, [fp, #0x50] cbz x0, G_M000_IG05 ldr x0, [fp, #0x50] ldr w1, [fp, #0x74] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 str w0, [fp, #0x28] b G_M000_IG06 G_M000_IG05: add x0, fp, #116 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x28] G_M000_IG06: ldr w0, [fp, #0x28] str w0, [fp, #0x4C] str wzr, [fp, #0x48] ldr x0, [fp, #0x78] ldr w1, [fp, #0x4C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x40] ldr x0, [fp, #0x40] ldr w0, [x0] sub w0, w0, #1 str w0, [fp, #0x3C] ldr x0, [fp, #0x50] cbnz x0, G_M000_IG13 G_M000_IG07: ldr w0, [fp, #0x20] sub w0, w0, #1 str w0, [fp, #0x20] ldr w0, [fp, #0x20] cmp w0, #0 bgt G_M000_IG09 G_M000_IG08: add x0, fp, #32 mov w1, #125 bl CORINFO_HELP_PATCHPOINT G_M000_IG09: ldr w0, [fp, #0x3C] ldr x1, [fp, #0x58] ldr w1, [x1, #0x08] cmp w0, w1 bhs G_M000_IG21 ldr x0, [fp, #0x58] ldr w1, [fp, #0x3C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG28 mov w2, #24 madd x0, x1, x2, x0 add x0, x0, #16 ldr w0, [x0] ldr w1, [fp, #0x4C] cmp w0, w1 bne G_M000_IG12 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x58] ldr w2, [fp, #0x3C] ldr w3, [x1, #0x08] cmp w2, w3 bhs G_M000_IG28 mov w3, #24 madd x1, x2, x3, x1 add x1, x1, #16 ldr w1, [x1, #0x08] ldr w2, [fp, #0x74] ldr x3, [fp, #0x18] ldr x3, [x3] ldr x3, [x3, #0x40] ldr x3, [x3, #0x20] blr x3 cbz w0, G_M000_IG12 ldr w0, [fp, #0x64] uxtb w0, w0 cmp w0, #1 bne G_M000_IG10 ldr x0, [fp, #0x58] ldr w1, [fp, #0x3C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG28 mov w2, #24 madd x0, x1, x2, x0 add x0, x0, #16 ldr x1, [fp, #0x68] str x1, [x0, #0x10] b G_M000_IG26 G_M000_IG10: ldr w0, [fp, #0x64] uxtb w0, w0 cmp w0, #2 bne G_M000_IG11 ldr w0, [fp, #0x74] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG11: b G_M000_IG18 G_M000_IG12: ldr x0, [fp, #0x58] ldr w1, [fp, #0x3C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG28 mov w2, #24 madd x0, x1, x2, x0 add x0, x0, #16 ldr w0, [x0, #0x04] str w0, [fp, #0x3C] ldr w0, [fp, #0x48] add w0, w0, #1 str w0, [fp, #0x48] ldr w0, [fp, #0x48] ldr x1, [fp, #0x58] ldr w1, [x1, #0x08] cmp w0, w1 bls G_M000_IG07 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 b G_M000_IG07 G_M000_IG13: ldr w0, [fp, #0x20] sub w0, w0, #1 str w0, [fp, #0x20] ldr w0, [fp, #0x20] cmp w0, #0 bgt G_M000_IG15 G_M000_IG14: add x0, fp, #32 mov w1, #241 bl CORINFO_HELP_PATCHPOINT G_M000_IG15: ldr w1, [fp, #0x3C] ldr x0, [fp, #0x58] ldr w0, [x0, #0x08] cmp w1, w0 bhs G_M000_IG21 ldr x1, [fp, #0x58] ldr w0, [fp, #0x3C] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG28 mov w2, #24 madd x1, x0, x2, x1 add x1, x1, #16 ldr w1, [x1] ldr w0, [fp, #0x4C] cmp w1, w0 bne G_M000_IG20 ldr x1, [fp, #0x58] ldr w0, [fp, #0x3C] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG28 mov w2, #24 madd x1, x0, x2, x1 add x1, x1, #16 ldr w1, [x1, #0x08] ldr x0, [fp, #0x50] ldr w2, [fp, #0x74] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x3, [x11] blr x3 cbz w0, G_M000_IG20 ldr w0, [fp, #0x64] uxtb w0, w0 cmp w0, #1 bne G_M000_IG16 ldr x0, [fp, #0x58] ldr w1, [fp, #0x3C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG28 mov w2, #24 madd x0, x1, x2, x0 add x0, x0, #16 ldr x1, [fp, #0x68] str x1, [x0, #0x10] b G_M000_IG26 G_M000_IG16: ldr w0, [fp, #0x64] uxtb w0, w0 cmp w0, #2 bne G_M000_IG17 ldr w0, [fp, #0x74] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG17: b G_M000_IG18 G_M000_IG18: mov w0, wzr G_M000_IG19: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG20: ldr x0, [fp, #0x58] ldr w1, [fp, #0x3C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG28 mov w2, #24 madd x0, x1, x2, x0 add x0, x0, #16 ldr w0, [x0, #0x04] str w0, [fp, #0x3C] ldr w0, [fp, #0x48] add w0, w0, #1 str w0, [fp, #0x48] ldr w0, [fp, #0x48] ldr x1, [fp, #0x58] ldr w1, [x1, #0x08] cmp w0, w1 bls G_M000_IG13 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 b G_M000_IG13 G_M000_IG21: ldr x0, [fp, #0x78] ldr w0, [x0, #0x40] cmp w0, #0 ble G_M000_IG22 ldr x0, [fp, #0x78] ldr w0, [x0, #0x3C] str w0, [fp, #0x38] ldr x0, [fp, #0x58] ldr x1, [fp, #0x78] ldr w1, [x1, #0x3C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG28 mov w2, #24 madd x0, x1, x2, x0 add x0, x0, #16 ldr w0, [x0, #0x04] neg w0, w0 sub w0, w0, #3 ldr x1, [fp, #0x78] str w0, [x1, #0x3C] ldr x0, [fp, #0x78] ldr w0, [x0, #0x40] sub w0, w0, #1 ldr x1, [fp, #0x78] str w0, [x1, #0x40] b G_M000_IG24 G_M000_IG22: ldr x0, [fp, #0x78] ldr w0, [x0, #0x38] str w0, [fp, #0x2C] ldr w0, [fp, #0x2C] ldr x1, [fp, #0x58] ldr w1, [x1, #0x08] cmp w0, w1 bne G_M000_IG23 ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x78] ldr w1, [fp, #0x4C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x40] G_M000_IG23: ldr w0, [fp, #0x2C] str w0, [fp, #0x38] ldr w0, [fp, #0x2C] add w0, w0, #1 ldr x1, [fp, #0x78] str w0, [x1, #0x38] ldr x0, [fp, #0x78] ldr x0, [x0, #0x10] str x0, [fp, #0x58] G_M000_IG24: ldr x0, [fp, #0x58] ldr w1, [fp, #0x38] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG28 mov w2, #24 madd x0, x1, x2, x0 add x0, x0, #16 str x0, [fp, #0x30] ldr x0, [fp, #0x30] ldr w1, [fp, #0x4C] str w1, [x0] ldr x0, [fp, #0x40] ldr w0, [x0] sub w0, w0, #1 ldr x1, [fp, #0x30] str w0, [x1, #0x04] ldr x0, [fp, #0x30] ldr w1, [fp, #0x74] str w1, [x0, #0x08] ldr x0, [fp, #0x30] ldr x1, [fp, #0x68] str x1, [x0, #0x10] ldr w0, [fp, #0x38] add w0, w0, #1 ldr x1, [fp, #0x40] str w0, [x1] ldr x0, [fp, #0x78] ldr w0, [x0, #0x44] add w0, w0, #1 ldr x1, [fp, #0x78] str w0, [x1, #0x44] b G_M000_IG25 G_M000_IG25: b G_M000_IG26 G_M000_IG26: mov w0, #1 G_M000_IG27: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG28: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 1428 999: JIT compiled System.Collections.Generic.Dictionary`2[int,System.ValueTuple`2[int,int]]:TryInsert(int,System.ValueTuple`2[int,int],ubyte) [Tier0, IL size=569, code size=1428] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.ValueTuple`2[int,int]]:GetBucket(uint):byref:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: ldr x2, [fp, #0x28] ldr x2, [x2, #0x08] str x2, [fp, #0x18] ldr x2, [fp, #0x28] ldr x2, [x2, #0x30] ldr x1, [fp, #0x18] ldr w1, [x1, #0x08] ldr w0, [fp, #0x24] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x1, [fp, #0x18] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG04 add x0, x1, x0, LSL #2 add x0, x0, #16 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 112 1000: JIT compiled System.Collections.Generic.Dictionary`2[int,System.ValueTuple`2[int,int]]:GetBucket(uint) [Tier0, IL size=29, code size=112] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.ValueTuple`2[int,int]]:get_Item(int):System.ValueTuple`2[int,int]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: ldr x0, [fp, #0x28] ldr w1, [fp, #0x24] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x0, [fp, #0x18] cbz x0, G_M000_IG04 ldr x0, [fp, #0x18] ldr x0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: ldr w0, [fp, #0x24] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str xzr, [fp, #0x10] ldr x0, [fp, #0x10] G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 116 1001: JIT compiled System.Collections.Generic.Dictionary`2[int,System.ValueTuple`2[int,int]]:get_Item(int) [Tier0, IL size=39, code size=116] ; Assembly listing for method System.Collections.Generic.Dictionary`2[int,System.ValueTuple`2[int,int]]:FindValue(int):byref:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str xzr, [x9, #0x50] str x0, [fp, #0x78] str w1, [fp, #0x74] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x20] b G_M000_IG03 G_M000_IG03: str xzr, [fp, #0x68] ldr x0, [fp, #0x78] ldr x0, [x0, #0x08] cbz x0, G_M000_IG19 ldr x0, [fp, #0x78] ldr x0, [x0, #0x18] str x0, [fp, #0x58] ldr x0, [fp, #0x58] cbnz x0, G_M000_IG08 add x0, fp, #116 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x54] ldr x0, [fp, #0x78] ldr w1, [fp, #0x54] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [x0] str w0, [fp, #0x50] ldr x0, [fp, #0x78] ldr x0, [x0, #0x10] str x0, [fp, #0x48] str wzr, [fp, #0x44] ldr w0, [fp, #0x50] sub w0, w0, #1 str w0, [fp, #0x50] G_M000_IG04: ldr w0, [fp, #0x20] sub w0, w0, #1 str w0, [fp, #0x20] ldr w0, [fp, #0x20] cmp w0, #0 bgt G_M000_IG06 G_M000_IG05: add x0, fp, #32 mov w1, #99 bl CORINFO_HELP_PATCHPOINT G_M000_IG06: ldr w0, [fp, #0x50] ldr x1, [fp, #0x48] ldr w1, [x1, #0x08] cmp w0, w1 bhs G_M000_IG19 ldr x0, [fp, #0x48] ldr w1, [fp, #0x50] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG20 mov w2, #24 madd x0, x1, x2, x0 add x0, x0, #16 str x0, [fp, #0x68] ldr x0, [fp, #0x68] ldr w0, [x0] ldr w1, [fp, #0x54] cmp w0, w1 bne G_M000_IG07 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x68] ldr w1, [x1, #0x08] ldr w2, [fp, #0x74] ldr x3, [fp, #0x18] ldr x3, [x3] ldr x3, [x3, #0x40] ldr x3, [x3, #0x20] blr x3 cbnz w0, G_M000_IG14 G_M000_IG07: ldr x0, [fp, #0x68] ldr w0, [x0, #0x04] str w0, [fp, #0x50] ldr w0, [fp, #0x44] add w0, w0, #1 str w0, [fp, #0x44] ldr w0, [fp, #0x44] ldr x1, [fp, #0x48] ldr w1, [x1, #0x08] cmp w0, w1 bls G_M000_IG04 b G_M000_IG13 G_M000_IG08: ldr x0, [fp, #0x58] ldr w1, [fp, #0x74] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 str w0, [fp, #0x40] ldr x0, [fp, #0x78] ldr w1, [fp, #0x40] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [x0] str w0, [fp, #0x3C] ldr x0, [fp, #0x78] ldr x0, [x0, #0x10] str x0, [fp, #0x30] str wzr, [fp, #0x2C] ldr w0, [fp, #0x3C] sub w0, w0, #1 str w0, [fp, #0x3C] G_M000_IG09: ldr w0, [fp, #0x20] sub w0, w0, #1 str w0, [fp, #0x20] ldr w0, [fp, #0x20] cmp w0, #0 bgt G_M000_IG11 G_M000_IG10: add x0, fp, #32 mov w1, #212 bl CORINFO_HELP_PATCHPOINT G_M000_IG11: ldr w1, [fp, #0x3C] ldr x0, [fp, #0x30] ldr w0, [x0, #0x08] cmp w1, w0 bhs G_M000_IG19 ldr x1, [fp, #0x30] ldr w0, [fp, #0x3C] ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG20 mov w2, #24 madd x1, x0, x2, x1 add x1, x1, #16 str x1, [fp, #0x68] ldr x1, [fp, #0x68] ldr w1, [x1] ldr w0, [fp, #0x40] cmp w1, w0 bne G_M000_IG12 ldr x1, [fp, #0x68] ldr w1, [x1, #0x08] ldr x0, [fp, #0x58] ldr w2, [fp, #0x74] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x3, [x11] blr x3 cbnz w0, G_M000_IG14 G_M000_IG12: ldr x0, [fp, #0x68] ldr w0, [x0, #0x04] str w0, [fp, #0x3C] ldr w0, [fp, #0x2C] add w0, w0, #1 str w0, [fp, #0x2C] ldr w0, [fp, #0x2C] ldr x1, [fp, #0x30] ldr w1, [x1, #0x08] cmp w0, w1 bls G_M000_IG09 G_M000_IG13: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG14: ldr x0, [fp, #0x68] ldrsb wzr, [x0] ldr x0, [fp, #0x68] add x0, x0, #16 str x0, [fp, #0x60] G_M000_IG15: ldr w0, [fp, #0x20] sub w0, w0, #1 str w0, [fp, #0x20] ldr w0, [fp, #0x20] cmp w0, #0 bgt G_M000_IG17 G_M000_IG16: add x0, fp, #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG17: ldr x0, [fp, #0x60] G_M000_IG18: ldp fp, lr, [sp], #0x80 ret lr G_M000_IG19: str xzr, [fp, #0x60] b G_M000_IG15 G_M000_IG20: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 800 1002: JIT compiled System.Collections.Generic.Dictionary`2[int,System.ValueTuple`2[int,int]]:FindValue(int) [Tier0, IL size=299, code size=800] ; Assembly listing for method System.Collections.Generic.EqualityComparer`1[int]:get_Default():System.Collections.Generic.EqualityComparer`1[int] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #52 bl CORINFO_HELP_CLASSINIT_SHARED_DYNAMICCLASS movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 52 1003: JIT compiled System.Collections.Generic.EqualityComparer`1[int]:get_Default() [Tier0, IL size=6, code size=52] ; Assembly listing for method System.Collections.Generic.EqualityComparer`1[int]:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 112 1004: JIT compiled System.Collections.Generic.EqualityComparer`1[int]:.cctor() [Tier0, IL size=26, code size=112] ; Assembly listing for method System.Collections.Generic.EnumEqualityComparer`1[int]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 1005: JIT compiled System.Collections.Generic.EnumEqualityComparer`1[int]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Collections.Generic.EqualityComparer`1[int]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 1006: JIT compiled System.Collections.Generic.EqualityComparer`1[int]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Collections.Generic.EnumEqualityComparer`1[int]:Equals(int,int):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] str w2, [fp, #0x10] G_M000_IG02: ldr w0, [fp, #0x14] ldr w1, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 1007: JIT compiled System.Collections.Generic.EnumEqualityComparer`1[int]:Equals(int,int) [Tier0, IL size=8, code size=56] ; Assembly listing for method System.Runtime.CompilerServices.RuntimeHelpers:EnumEquals[int](int,int):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str w0, [fp, #0x1C] str w1, [fp, #0x18] G_M000_IG02: ldr w0, [fp, #0x1C] ldr w1, [fp, #0x18] cmp w0, w1 cset x0, eq G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 1008: JIT compiled System.Runtime.CompilerServices.RuntimeHelpers:EnumEquals[int](int,int) [Tier0, IL size=5, code size=40] ; Assembly listing for method Perfolizer.Mathematics.Distributions.StudentDistribution:InverseTwoTailStudent(double,double):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str d0, [fp, #0x38] str d1, [fp, #0x30] G_M000_IG02: str xzr, [fp, #0x28] ldr d16, [@RWD00] str d16, [fp, #0x20] mov w0, #0xD1FFAB1E str w0, [fp, #0x10] b G_M000_IG05 G_M000_IG03: ldr d0, [fp, #0x28] ldr d1, [fp, #0x20] fadd d0, d0, d1 fmov d1, #0.5000 fmul d0, d0, d1 str d0, [fp, #0x18] ldr d0, [fp, #0x18] ldr d1, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr d16, [fp, #0x38] fcmp d0, d16 bhs G_M000_IG04 ldr d0, [fp, #0x18] str d0, [fp, #0x20] b G_M000_IG05 G_M000_IG04: ldr d0, [fp, #0x18] str d0, [fp, #0x28] G_M000_IG05: ldr w0, [fp, #0x10] sub w0, w0, #1 str w0, [fp, #0x10] ldr w0, [fp, #0x10] cmp w0, #0 bgt G_M000_IG07 G_M000_IG06: add x0, fp, #16 mov w1, #52 bl CORINFO_HELP_PATCHPOINT G_M000_IG07: ldr d0, [fp, #0x20] ldr d1, [fp, #0x28] fsub d0, d0, d1 ldr d1, [@RWD08] fcmp d0, d1 bgt G_M000_IG03 ldr d0, [fp, #0x28] ldr d16, [fp, #0x20] fadd d0, d0, d16 fmov d16, #0.5000 fmul d0, d0, d16 G_M000_IG08: ldp fp, lr, [sp], #0x40 ret lr RWD00 dq 408F400000000000h ; 1000 RWD08 dq 3E112E0BE826D695h ; 1e-09 ; Total bytes of code 224 1009: JIT compiled Perfolizer.Mathematics.Distributions.StudentDistribution:InverseTwoTailStudent(double,double) [Tier0, IL size=80, code size=224] ; Assembly listing for method Perfolizer.Mathematics.Distributions.StudentDistribution:StudentTwoTail(double,double):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] str d0, [fp, #0x98] str d1, [fp, #0x90] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x30] ldr d0, [fp, #0x98] fcmp d0, #0.0 bhs G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x20] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] ldr x0, [fp, #0x38] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x38] bl CORINFO_HELP_THROW G_M000_IG04: ldr d0, [fp, #0x90] fmov d16, #1.0000 fcmp d0, d16 bhs G_M000_IG06 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x40] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x18] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x10] ldr x1, [fp, #0x18] ldr x2, [fp, #0x10] ldr x0, [fp, #0x40] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x40] bl CORINFO_HELP_THROW G_M000_IG06: ldr d0, [fp, #0x98] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x98] ldr d0, [fp, #0x98] ldr d16, [fp, #0x90] fdiv d0, d0, d16 str d0, [fp, #0x88] ldr d0, [fp, #0x88] fmov d16, #1.0000 fadd d0, d0, d16 str d0, [fp, #0x80] ldr d0, [fp, #0x90] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 fcvtzs w0, d0 str w0, [fp, #0x7C] ldr d0, [fp, #0x90] ldr w0, [fp, #0x7C] scvtf d16, w0 fsub d0, d0, d16 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr d16, [@RWD00] fcmp d0, d16 bgt G_M000_IG07 ldr d0, [fp, #0x90] fmov d16, #20.0000 fcmp d0, d16 bge G_M000_IG07 ldr d0, [fp, #0x98] ldr d16, [fp, #0x90] fcmp d0, d16 bhs G_M000_IG10 ldr d0, [fp, #0x90] ldr d16, [@RWD08] fcmp d0, d16 ble G_M000_IG10 G_M000_IG07: ldr d0, [fp, #0x88] ldr d16, [@RWD16] fcmp d0, d16 ble G_M000_IG08 ldr d0, [fp, #0x80] bl System.Math:Log(double):double str d0, [fp, #0x88] G_M000_IG08: ldr d0, [fp, #0x90] fmov d16, #0.5000 fsub d0, d0, d16 str d0, [fp, #0x70] ldr d0, [fp, #0x70] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr d16, [@RWD24] fmul d0, d0, d16 str d0, [fp, #0x80] ldr d0, [fp, #0x70] ldr d16, [fp, #0x88] fmul d0, d0, d16 str d0, [fp, #0x88] ldr d0, [fp, #0x88] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr d16, [@RWD32] fmul d0, d0, d16 ldr d16, [@RWD40] fadd d0, d0, d16 ldr d16, [fp, #0x80] fadd d0, d0, d16 ldr d16, [fp, #0x88] ldr d17, [@RWD48] fmul d16, d16, d17 ldr d17, [@RWD56] fsub d16, d16, d17 ldr d17, [fp, #0x88] fmul d16, d16, d17 fmov d17, #24.0000 fsub d16, d16, d17 ldr d17, [fp, #0x88] fmul d16, d16, d17 ldr d17, [@RWD64] fsub d16, d16, d17 fdiv d0, d16, d0 ldr d16, [fp, #0x88] fadd d0, d0, d16 fmov d16, #3.0000 fadd d0, d0, d16 ldr d16, [fp, #0x80] fdiv d0, d0, d16 fmov d16, #1.0000 fadd d0, d0, d16 str d0, [fp, #0x50] ldr d0, [fp, #0x88] bl System.Math:Sqrt(double):double ldr d16, [fp, #0x50] fmul d0, d0, d16 str d0, [fp, #0x88] ldr d0, [fp, #0x88] fneg d0, d0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 fmov d16, #2.0000 fmul d0, d0, d16 G_M000_IG09: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG10: fmov d0, #1.0000 str d0, [fp, #0x68] ldr d0, [fp, #0x90] fmov d16, #20.0000 fcmp d0, d16 bhs G_M000_IG11 ldr d0, [fp, #0x98] fmov d16, #4.0000 fcmp d0, d16 bhs G_M000_IG11 ldr d0, [fp, #0x88] bl System.Math:Sqrt(double):double str d0, [fp, #0x88] ldr d0, [fp, #0x88] str d0, [fp, #0x60] ldr w0, [fp, #0x7C] cmp w0, #1 bne G_M000_IG16 str xzr, [fp, #0x60] b G_M000_IG16 G_M000_IG11: ldr d0, [fp, #0x80] bl System.Math:Sqrt(double):double str d0, [fp, #0x60] ldr d16, [fp, #0x60] ldr w0, [fp, #0x7C] scvtf d17, w0 fmul d16, d16, d17 str d16, [fp, #0x88] str wzr, [fp, #0x5C] b G_M000_IG13 G_M000_IG12: ldr w0, [fp, #0x5C] add w0, w0, #2 str w0, [fp, #0x5C] ldr d16, [fp, #0x60] str d16, [fp, #0x68] ldr d16, [fp, #0x80] ldr w0, [fp, #0x5C] scvtf d17, w0 fmul d16, d16, d17 ldr w0, [fp, #0x5C] sub w0, w0, #1 scvtf d17, w0 fdiv d16, d17, d16 ldr d17, [fp, #0x88] fmul d16, d16, d17 str d16, [fp, #0x88] ldr w0, [fp, #0x7C] ldr w1, [fp, #0x5C] add w0, w0, w1 scvtf d16, w0 ldr d17, [fp, #0x88] fdiv d16, d17, d16 ldr d17, [fp, #0x60] fadd d16, d16, d17 str d16, [fp, #0x60] G_M000_IG13: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG15 G_M000_IG14: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG15: ldr d0, [fp, #0x60] ldr d16, [fp, #0x68] fsub d0, d0, d16 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 fcmp d0, #0.0 bgt G_M000_IG12 ldr w0, [fp, #0x7C] add w0, w0, #2 str w0, [fp, #0x7C] str xzr, [fp, #0x68] str xzr, [fp, #0x88] ldr d16, [fp, #0x60] fneg d16, d16 str d16, [fp, #0x60] G_M000_IG16: ldr w0, [fp, #0x30] sub w0, w0, #1 str w0, [fp, #0x30] ldr w0, [fp, #0x30] cmp w0, #0 bgt G_M000_IG18 G_M000_IG17: add x0, fp, #48 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG18: ldr w0, [fp, #0x7C] sub w0, w0, #2 str w0, [fp, #0x7C] ldr w0, [fp, #0x7C] cmp w0, #1 ble G_M000_IG19 ldr d0, [fp, #0x80] ldr w0, [fp, #0x7C] scvtf d16, w0 fmul d0, d0, d16 ldr w0, [fp, #0x7C] sub w0, w0, #1 scvtf d16, w0 fdiv d0, d16, d0 ldr d16, [fp, #0x60] fmul d0, d0, d16 ldr d16, [fp, #0x88] fadd d0, d0, d16 str d0, [fp, #0x60] b G_M000_IG16 G_M000_IG19: ldr w0, [fp, #0x7C] cbz w0, G_M000_IG20 ldr d0, [fp, #0x88] bl System.Math:Atan(double):double ldr d16, [fp, #0x60] ldr d17, [fp, #0x80] fdiv d16, d16, d17 fadd d0, d0, d16 fmov d16, #2.0000 fmul d0, d0, d16 ldr d16, [@RWD72] fdiv d0, d0, d16 str d0, [fp, #0x48] b G_M000_IG21 G_M000_IG20: ldr d0, [fp, #0x80] bl System.Math:Sqrt(double):double ldr d16, [fp, #0x60] fdiv d0, d16, d0 str d0, [fp, #0x48] G_M000_IG21: ldr d0, [fp, #0x48] str d0, [fp, #0x60] ldr d0, [fp, #0x68] ldr d16, [fp, #0x60] fsub d0, d0, d16 G_M000_IG22: ldp fp, lr, [sp], #0xA0 ret lr RWD00 dq 3E112E0BE826D695h ; 1e-09 RWD08 dq 4069000000000000h ; 200 RWD16 dq 3EB0C6F7A0B5ED8Dh ; 1e-06 RWD24 dq 4048000000000000h ; 48 RWD32 dq 3FE999999999999Ah ; 0.8 RWD40 dq 4059000000000000h ; 100 RWD48 dq BFD999999999999Ah ; -0.4 RWD56 dq 400A666666666666h ; 3.3 RWD64 dq 4055600000000000h ; 85.5 RWD72 dq 400921FB54442D18h ; 3.14159265 ; Total bytes of code 1328 1010: JIT compiled Perfolizer.Mathematics.Distributions.StudentDistribution:StudentTwoTail(double,double) [Tier0, IL size=565, code size=1328] ; Assembly listing for method Perfolizer.Mathematics.Common.MathExtensions:Sqr(double):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str d0, [fp, #0x18] G_M000_IG02: ldr d0, [fp, #0x18] ldr d16, [fp, #0x18] fmul d0, d0, d16 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 32 1011: JIT compiled Perfolizer.Mathematics.Common.MathExtensions:Sqr(double) [Tier0, IL size=4, code size=32] ; Assembly listing for method System.Span`1[BenchmarkDotNet.Reports.Measurement]:Slice(int,int):System.Span`1[BenchmarkDotNet.Reports.Measurement]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str w1, [fp, #0x24] str w2, [fp, #0x20] G_M000_IG02: ldr w0, [fp, #0x24] mov w0, w0 ldr w1, [fp, #0x20] mov w1, w1 add x0, x0, x1 ldr x1, [fp, #0x28] ldr w1, [x1, #0x08] mov w1, w1 cmp x0, x1 bls G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG03: stp xzr, xzr, [fp, #0x10] ldr x1, [fp, #0x28] ldr x1, [x1] ldr w0, [fp, #0x24] mov w0, w0 lsl x0, x0, #5 add x1, x1, x0 add x0, fp, #16 ldr w2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] G_M000_IG04: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 156 1012: JIT compiled System.Span`1[BenchmarkDotNet.Reports.Measurement]:Slice(int,int) [Tier0, IL size=39, code size=156] ; Assembly listing for method System.Collections.Generic.GenericArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:InsertionSort(System.Span`1[BenchmarkDotNet.Reports.Measurement]) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x18] str x0, [fp, #0x60] str x1, [fp, #0x68] G_M000_IG02: str wzr, [fp, #0x5C] mov w0, #0xD1FFAB1E str w0, [fp, #0x20] b G_M000_IG11 G_M000_IG03: ldr x0, [fp, #0x60] ldr x1, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w1, [fp, #0x5C] add w1, w1, #1 sxtw x1, w1 lsl x1, x1, #5 add x0, x0, x1 ldp x1, x2, [x0] stp x1, x2, [fp, #0x38] ldp x1, x2, [x0, #0x10] stp x1, x2, [fp, #0x48] ldr w0, [fp, #0x5C] str w0, [fp, #0x34] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x60] ldr x1, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w1, [fp, #0x34] add w1, w1, #1 sxtw x1, w1 lsl x1, x1, #5 add x0, x0, x1 str x0, [fp, #0x28] ldr x0, [fp, #0x60] ldr x1, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w1, [fp, #0x34] sxtw x1, w1 lsl x1, x1, #5 add x0, x0, x1 ldr x1, [fp, #0x28] ldp q16, q17, [x0] stp q16, q17, [x1] ldr w0, [fp, #0x34] sub w0, w0, #1 str w0, [fp, #0x34] G_M000_IG05: ldr w0, [fp, #0x34] tbnz w0, #31, G_M000_IG08 ldr w0, [fp, #0x20] sub w0, w0, #1 str w0, [fp, #0x20] ldr w0, [fp, #0x20] cmp w0, #0 bgt G_M000_IG07 G_M000_IG06: add x0, fp, #32 mov w1, #80 bl CORINFO_HELP_PATCHPOINT G_M000_IG07: ldr x0, [fp, #0x60] ldr x1, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w1, [fp, #0x34] sxtw x1, w1 lsl x1, x1, #5 add x1, x0, x1 str x1, [fp, #0x18] ldr x1, [fp, #0x18] add x0, fp, #56 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG04 G_M000_IG08: ldr x0, [fp, #0x60] ldr x1, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w1, [fp, #0x34] add w1, w1, #1 sxtw x1, w1 lsl x1, x1, #5 add x0, x0, x1 G_M000_IG09: add x1, fp, #56 ldp q16, q17, [x1] stp q16, q17, [x0] G_M000_IG10: ldr w0, [fp, #0x5C] add w0, w0, #1 str w0, [fp, #0x5C] G_M000_IG11: ldr w0, [fp, #0x20] sub w0, w0, #1 str w0, [fp, #0x20] ldr w0, [fp, #0x20] cmp w0, #0 bgt G_M000_IG13 G_M000_IG12: add x0, fp, #32 mov w1, #125 bl CORINFO_HELP_PATCHPOINT G_M000_IG13: ldr w0, [fp, #0x5C] ldr w1, [fp, #0x68] sub w1, w1, #1 cmp w0, w1 blt G_M000_IG03 G_M000_IG14: ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 496 1013: JIT compiled System.Collections.Generic.GenericArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:InsertionSort(System.Span`1[BenchmarkDotNet.Reports.Measurement]) [Tier0, IL size=141, code size=496] ; Assembly listing for method System.Runtime.InteropServices.MemoryMarshal:GetReference[BenchmarkDotNet.Reports.Measurement](System.Span`1[BenchmarkDotNet.Reports.Measurement]):byref ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x10] str x1, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1014: JIT compiled System.Runtime.InteropServices.MemoryMarshal:GetReference[BenchmarkDotNet.Reports.Measurement](System.Span`1[BenchmarkDotNet.Reports.Measurement]) [Tier0, IL size=8, code size=28] ; Assembly listing for method System.Collections.Generic.GenericArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:LessThan(byref,byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] G_M000_IG02: b G_M000_IG03 G_M000_IG03: b G_M000_IG04 G_M000_IG04: b G_M000_IG05 G_M000_IG05: b G_M000_IG06 G_M000_IG06: b G_M000_IG07 G_M000_IG07: b G_M000_IG08 G_M000_IG08: b G_M000_IG09 G_M000_IG09: b G_M000_IG10 G_M000_IG10: b G_M000_IG11 G_M000_IG11: b G_M000_IG12 G_M000_IG12: b G_M000_IG13 G_M000_IG13: b G_M000_IG14 G_M000_IG14: b G_M000_IG15 G_M000_IG15: ldr x0, [fp, #0x48] str x0, [fp, #0x18] ldr x0, [fp, #0x40] ldp q16, q17, [x0] stp q16, q17, [fp, #0x20] ldr x0, [fp, #0x18] add x1, fp, #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 tbnz w0, #31, G_M000_IG17 mov w0, wzr G_M000_IG16: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG17: mov w0, #1 G_M000_IG18: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 148 1015: JIT compiled System.Collections.Generic.GenericArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:LessThan(byref,byref) [Tier0, IL size=834, code size=148] ; Assembly listing for method BenchmarkDotNet.Engines.EngineWarmupStage:RunWorkload(long,int,int):System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Reports.Measurement]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] str w3, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] ldr w4, [fp, #0x18] ldr w3, [fp, #0x1C] mov w2, #1 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 72 1016: JIT compiled BenchmarkDotNet.Engines.EngineWarmupStage:RunWorkload(long,int,int) [Tier0, IL size=11, code size=72] ; Assembly listing for method BenchmarkDotNet.Engines.DefaultStoppingCriteriaFactory:CreateWarmupWorkload(BenchmarkDotNet.Jobs.Job,BenchmarkDotNet.Characteristics.IResolver,int):BenchmarkDotNet.Engines.IStoppingCriteria:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str xzr, [fp, #0x38] str wzr, [fp, #0x34] str xzr, [fp, #0x28] str xzr, [fp, #0x20] str x0, [fp, #0x58] str x1, [fp, #0x50] str x2, [fp, #0x48] str w3, [fp, #0x44] G_M000_IG02: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr x0, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 str x0, [fp, #0x38] add x0, fp, #56 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG03 add x0, fp, #56 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cmn w0, #1 bne G_M000_IG04 G_M000_IG03: ldr w0, [fp, #0x44] cmp w0, #2 bne G_M000_IG06 G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] add x0, fp, #56 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x1C] ldr w1, [fp, #0x1C] ldr x0, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x20] G_M000_IG05: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG06: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr x0, [fp, #0x50] ldr x2, [fp, #0x48] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 str w0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr x0, [fp, #0x50] ldr x2, [fp, #0x48] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 str w0, [fp, #0x34] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr w1, [fp, #0x30] ldr w2, [fp, #0x34] mov w3, #4 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x28] G_M000_IG07: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 420 1017: JIT compiled BenchmarkDotNet.Engines.DefaultStoppingCriteriaFactory:CreateWarmupWorkload(BenchmarkDotNet.Jobs.Job,BenchmarkDotNet.Characteristics.IResolver,int) [Tier0, IL size=81, code size=420] ; Assembly listing for method BenchmarkDotNet.Engines.FixedStoppingCriteria:.ctor(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] str x0, [fp, #0x48] str w1, [fp, #0x44] G_M000_IG02: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x48] ldr w1, [fp, #0x44] str w1, [x0, #0x28] add x0, fp, #24 mov w1, #47 mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x0, fp, #24 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #24 ldr w1, [fp, #0x44] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #24 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #24 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x48] add x14, x14, #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 248 1018: JIT compiled BenchmarkDotNet.Engines.FixedStoppingCriteria:.ctor(int) [Tier0, IL size=69, code size=248] ; Assembly listing for method BenchmarkDotNet.Engines.FixedStoppingCriteria:GetMaxIterationCount():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x28] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1019: JIT compiled BenchmarkDotNet.Engines.FixedStoppingCriteria:GetMaxIterationCount() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.FixedStoppingCriteria:Evaluate(System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Reports.Measurement]):BenchmarkDotNet.Engines.StoppingResult:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x18] str x0, [fp, #0x48] str x1, [fp, #0x40] G_M000_IG02: ldr x0, [fp, #0x40] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str w0, [fp, #0x3C] ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w1, [fp, #0x3C] cmp w0, w1 ble G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] G_M000_IG03: ldp x1, x2, [x0, #0x08] stp x1, x2, [fp, #0x18] G_M000_IG04: ldr x0, [fp, #0x18] ldr x1, [fp, #0x20] G_M000_IG05: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG06: ldr x0, [fp, #0x48] ldr x0, [x0, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x28] str x1, [fp, #0x30] ldr x0, [fp, #0x28] ldr x1, [fp, #0x30] G_M000_IG07: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 180 1020: JIT compiled BenchmarkDotNet.Engines.FixedStoppingCriteria:Evaluate(System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Reports.Measurement]) [Tier0, IL size=32, code size=180] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:WorkloadWarmupStart(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x2, [fp, #0x10] mov w1, #13 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 1021: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:WorkloadWarmupStart(long) [Tier0, IL size=10, code size=56] ; Assembly listing for method System.Diagnostics.Tracing.EventProvider:WriteEvent(byref,long,ulong,ulong,int,long):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! str x19, [sp, #0x18] mov fp, sp G_M000_IG02: ldr x0, [x0, #0x08] ldr x7, [x0] ldr x7, [x7, #0x48] ldr x7, [x7] blr x7 mov w19, w0 cbz w19, G_M000_IG06 G_M000_IG03: ldr x0, [xpr, #0x58] ldr x0, [x0, #0x20] ldr w1, [x0, #0xD1FFAB1E] cmp w1, #2 blt G_M000_IG08 ldr x0, [x0, #0xD1FFAB1E] ldr x1, [x0, #0x10] cbz x1, G_M000_IG08 G_M000_IG04: str w19, [x1, #0xD1FFAB1E] mov w0, wzr G_M000_IG05: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG06: mov w0, #1 G_M000_IG07: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG08: mov w0, #2 bl CORINFO_HELP_GETSHARED_NONGCTHREADSTATIC_BASE_NOCTOR_OPTIMIZED mov x1, x0 b G_M000_IG04 ; Total bytes of code 124 1022: JIT compiled System.Diagnostics.Tracing.EventProvider:WriteEvent(byref,long,ulong,ulong,int,long) [Tier1, IL size=40, code size=124] ; Assembly listing for method System.Diagnostics.Tracing.EtwEventProvider:EventWriteTransfer(byref,long,ulong,ulong,int,ulong):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr x0, [x0, #0x30] mov x2, x3 mov x3, x4 mov w4, w5 mov x5, x6 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 cmp w0, #8 beq G_M000_IG05 G_M000_IG03: mov w1, #0xD1FFAB1E mov w2, #2 cmp w0, #234 ccmp w0, w1, z, ne csel w0, wzr, w2, ne G_M000_IG04: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG05: mov w0, #1 G_M000_IG06: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 96 1023: JIT compiled System.Diagnostics.Tracing.EtwEventProvider:EventWriteTransfer(byref,long,ulong,ulong,int,ulong) [Tier1, IL size=46, code size=96] ; Assembly listing for method Interop+Advapi32:EventWriteTransfer(long,byref,ulong,ulong,int,ulong):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 2 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0xD0]! stp x19, x20, [sp, #0x80] stp x21, x22, [sp, #0x90] stp x23, x24, [sp, #0xA0] stp x25, x26, [sp, #0xB0] stp x27, x28, [sp, #0xC0] mov fp, sp str xzr, [fp, #0x68] str xzr, [fp, #0x60] mov x20, x0 mov x19, x1 mov x21, x2 mov x22, x3 mov w23, w4 mov x24, x5 G_M000_IG02: add x0, fp, #24 mov x1, x12 bl CORINFO_HELP_INIT_PINVOKE_FRAME mov x25, x0 mov x0, sp str x0, [fp, #0x38] mov x0, fp str x0, [fp, #0x48] str x19, [fp, #0x68] str x19, [fp, #0x58] mov x1, x19 mov x0, x20 mov x2, x21 mov x3, x22 mov w4, w23 mov x5, x24 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 str x6, [fp, #0x28] adr x6, [G_M000_IG05] str x6, [fp, #0x40] add x6, fp, #24 str x6, [x25, #0x10] strb wzr, [x25, #0x0C] G_M000_IG03: movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 G_M000_IG04: blr x6 G_M000_IG05: mov w19, w0 mov w0, #1 strb w0, [x25, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG06 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG06: ldr x0, [fp, #0x20] str x0, [x25, #0x10] str xzr, [fp, #0x68] mov w0, w19 cmp w0, #87 bne G_M000_IG12 G_M000_IG07: cbnz x22, G_M000_IG12 movi v16.4s, #0 str q16, [fp, #0x70] ldr x19, [fp, #0x58] str x19, [fp, #0x60] mov x0, x20 mov x1, x19 add x3, fp, #112 mov x2, x21 mov w4, w23 mov x5, x24 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 str x6, [fp, #0x28] adr x6, [G_M000_IG10] str x6, [fp, #0x40] add x6, fp, #24 str x6, [x25, #0x10] strb wzr, [x25, #0x0C] G_M000_IG08: movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 G_M000_IG09: blr x6 G_M000_IG10: mov w19, w0 mov w0, #1 strb w0, [x25, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG11 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG11: ldr x0, [fp, #0x20] str x0, [x25, #0x10] mov w0, w19 str xzr, [fp, #0x60] G_M000_IG12: ldp x27, x28, [sp, #0xC0] ldp x25, x26, [sp, #0xB0] ldp x23, x24, [sp, #0xA0] ldp x21, x22, [sp, #0x90] ldp x19, x20, [sp, #0x80] ldp fp, lr, [sp], #0xD0 ret lr ; Total bytes of code 420 1024: JIT compiled Interop+Advapi32:EventWriteTransfer(long,byref,ulong,ulong,int,ulong) [Tier1, IL size=48, code size=420] ; Assembly listing for method System.String:FillStringChecked(System.String,int,System.String) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 234382 ; 1 inlinees with PGO data; 1 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! str x19, [sp, #0x18] mov fp, sp G_M000_IG02: ldr w3, [x2, #0x08] ldr w4, [x0, #0x08] sub w4, w4, w1 cmp w3, w4 bgt G_M000_IG05 G_M000_IG03: add x0, x0, #12 sbfiz x1, x1, #1, #32 add x0, x0, x1 add x1, x2, #12 mov w2, w3 lsl x2, x2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG04: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x0, x19 bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 140 1025: JIT compiled System.String:FillStringChecked(System.String,int,System.String) [Tier1 with Static PGO, IL size=53, code size=140] ; Assembly listing for method BenchmarkDotNet.Autogenerated.Runnable_0:__Overhead():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 16 1026: JIT compiled BenchmarkDotNet.Autogenerated.Runnable_0:__Overhead() [Tier1, IL size=1, code size=16] ; Assembly listing for method System.GC:Collect() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0xB0]! stp x19, x20, [sp, #0x60] stp x21, x22, [sp, #0x70] stp x23, x24, [sp, #0x80] stp x25, x26, [sp, #0x90] stp x27, x28, [sp, #0xA0] mov fp, sp G_M000_IG02: add x0, fp, #32 mov x1, x12 bl CORINFO_HELP_INIT_PINVOKE_FRAME mov x19, x0 mov x0, sp str x0, [fp, #0x40] mov x0, fp str x0, [fp, #0x50] movn w0, #0 mov w1, #2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 str x2, [fp, #0x30] adr x2, [G_M000_IG05] str x2, [fp, #0x48] add x2, fp, #32 str x2, [x19, #0x10] strb wzr, [x19, #0x0C] G_M000_IG03: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 G_M000_IG04: blr x2 G_M000_IG05: mov w0, #1 strb w0, [x19, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG06 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG06: ldr x0, [fp, #0x28] str x0, [x19, #0x10] G_M000_IG07: ldp x27, x28, [sp, #0xA0] ldp x25, x26, [sp, #0x90] ldp x23, x24, [sp, #0x80] ldp x21, x22, [sp, #0x70] ldp x19, x20, [sp, #0x60] ldp fp, lr, [sp], #0xB0 ret lr ; Total bytes of code 192 1027: JIT compiled System.GC:Collect() [Tier1, IL size=8, code size=192] ; Assembly listing for method BenchmarkDotNet.Engines.IterationData:get_IterationMode():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1028: JIT compiled BenchmarkDotNet.Engines.IterationData:get_IterationMode() [Tier1, IL size=7, code size=20] ; Assembly listing for method Perfolizer.Horology.TimeUnit:get_NanosecondAmount():long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr x0, [x0, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1029: JIT compiled Perfolizer.Horology.TimeUnit:get_NanosecondAmount() [Tier1, IL size=7, code size=20] ; Assembly listing for method System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[ushort]():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1030: JIT compiled System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[ushort]() [Tier1, IL size=2, code size=20] ; Assembly listing for method System.Collections.Generic.ValueListBuilder`1[ushort]:Append(ushort):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w2, [x0, #0x08] add x3, x0, #16 ldr x4, [x3] ldr w3, [x3, #0x08] cmp w2, w3 bhs G_M000_IG05 G_M000_IG03: strh w1, [x4, w2, UXTW #2] add w1, w2, #1 str w1, [x0, #0x08] G_M000_IG04: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG05: uxth w1, w1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG06: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 84 1031: JIT compiled System.Collections.Generic.ValueListBuilder`1[ushort]:Append(ushort) [Tier1, IL size=56, code size=84] ; Assembly listing for method System.Gen2GcCallback:Finalize():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 93 ; 1 inlinees with PGO data; 5 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp add x1, sp, #32 str x1, [fp, #0x18] str x0, [fp, #0x10] G_M000_IG02: ldr x1, [x0, #0x18] cbz x1, G_M000_IG07 G_M000_IG03: and x1, x1, #-2 ldr x1, [x1] cbz x1, G_M000_IG06 G_M000_IG04: ldr x2, [x0, #0x10] ldr x0, [x2, #0x08] ldr x2, [x2, #0x18] blr x2 cbnz w0, G_M000_IG09 G_M000_IG05: ldr x0, [fp, #0x10] add x0, x0, #24 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 b G_M000_IG10 G_M000_IG06: add x0, x0, #24 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 b G_M000_IG10 G_M000_IG07: ldr x1, [x0, #0x08] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 cbnz w0, G_M000_IG09 G_M000_IG08: b G_M000_IG10 G_M000_IG09: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG10: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG11: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG12: stp fp, lr, [sp, #-0x20]! add x3, fp, #32 str x3, [sp, #0x18] G_M000_IG13: adr x0, [G_M000_IG09] G_M000_IG14: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG15: stp fp, lr, [sp, #-0x20]! add x3, fp, #32 str x3, [sp, #0x18] G_M000_IG16: adr x0, [G_M000_IG09] G_M000_IG17: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG18: stp fp, lr, [sp, #-0x20]! add x3, fp, #32 str x3, [sp, #0x18] G_M000_IG19: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG20: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 292 1032: JIT compiled System.Gen2GcCallback:Finalize() [Tier1 with Static PGO, IL size=111, code size=292] ; Assembly listing for method System.Buffers.TlsOverPerCoreLockedStacksArrayPool`1+<>c[ushort]:b__13_0(System.Object):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov x0, x1 cbz x0, G_M000_IG04 G_M000_IG03: ldr x2, [x0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 cmp x2, x3 bne G_M000_IG06 G_M000_IG04: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] G_M000_IG05: ldp fp, lr, [sp], #0x10 br x1 G_M000_IG06: mov x0, x3 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 brk_windows #0 ; Total bytes of code 96 1033: JIT compiled System.Buffers.TlsOverPerCoreLockedStacksArrayPool`1+<>c[ushort]:b__13_0(System.Object) [Tier1, IL size=12, code size=96] ; Assembly listing for method System.Buffers.TlsOverPerCoreLockedStacksArrayPool`1[ushort]:Trim():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 22 ; 5 inlinees with PGO data; 17 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x90]! stp x19, x20, [sp, #0x40] stp x21, x22, [sp, #0x50] stp x23, x24, [sp, #0x60] stp x25, x26, [sp, #0x70] stp x27, x28, [sp, #0x80] mov fp, sp add x1, sp, #144 str x1, [fp, #0x38] mov x19, x0 G_M000_IG02: bl System.Environment:get_TickCount():int mov w20, w0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 mov w21, w0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x22, [x0] ldrb w0, [x22, #0x9D] cbnz w0, G_M000_IG40 G_M000_IG03: ldr x23, [x19, #0x10] mov w24, wzr ldr w25, [x23, #0x08] cmp w25, #0 ble G_M000_IG06 G_M000_IG04: add x0, x23, #16 ldr x26, [x0, w24, UXTW #3] cbnz x26, G_M000_IG12 G_M000_IG05: add w24, w24, #1 cmp w25, w24 bgt G_M000_IG04 G_M000_IG06: cmp w21, #2 beq G_M000_IG41 mov w0, #0xD1FFAB1E mov w1, #0xD1FFAB1E cmp w21, #1 csel w26, w0, w1, ne ldr x0, [x19, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x18] b G_M000_IG23 G_M000_IG07: b G_M000_IG09 G_M000_IG08: ldr x0, [fp, #0x28] add x11, x27, #8 ldr x1, [x11] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG09: ldr x0, [fp, #0x28] movz x27, #0xD1FFAB1E movk x27, #0xD1FFAB1E LSL #16 movk x27, #0xD1FFAB1E LSL #32 mov x11, x27 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG08 G_M000_IG10: ldr x0, [fp, #0x38] bl G_M000_IG43 G_M000_IG11: b G_M000_IG38 G_M000_IG12: mov x0, x19 bl System.Runtime.CompilerServices.RuntimeHelpers:GetHashCode(System.Object):int mov w27, w0 mov w0, #16 lsl w28, w0, w24 ldr x0, [x26, #0x08] mov w26, wzr ldr w5, [x0, #0x08] str w5, [fp, #0x34] cmp w5, #0 ble G_M000_IG05 G_M000_IG13: add x6, x0, #16 str x6, [fp, #0x10] G_M000_IG14: ldr x0, [x6, w26, UXTW #3] mov w1, w20 mov w2, w27 mov w3, w21 mov w4, w28 movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] ldr wzr, [x0] blr x7 add w26, w26, #1 ldr w0, [fp, #0x34] cmp w0, w26 ldr x6, [fp, #0x10] bgt G_M000_IG14 b G_M000_IG05 G_M000_IG15: b G_M000_IG20 G_M000_IG16: ldr x0, [fp, #0x20] sub x11, x27, #24 ldr x1, [x11] blr x1 mov x27, x0 mov w28, wzr b G_M000_IG19 G_M000_IG17: ubfiz x0, x28, #4, #32 add x0, x0, #16 add x0, x27, x0 mov x1, xzr swpal x1, x20, [x0] cbz x20, G_M000_IG18 mov x0, x20 bl System.Runtime.CompilerServices.RuntimeHelpers:GetHashCode(System.Object):int mov w23, w0 ldr w26, [x20, #0x08] mov x0, x19 bl System.Runtime.CompilerServices.RuntimeHelpers:GetHashCode(System.Object):int mov w4, w0 mov x0, x22 mov w2, w23 mov w3, w26 mov w1, #4 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 G_M000_IG18: add w28, w28, #1 G_M000_IG19: ldr w0, [x27, #0x08] cmp w0, w28 bgt G_M000_IG17 G_M000_IG20: ldr x0, [fp, #0x20] movz x27, #0xD1FFAB1E movk x27, #0xD1FFAB1E LSL #16 movk x27, #0xD1FFAB1E LSL #32 sub x11, x27, #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG16 G_M000_IG21: ldr x0, [fp, #0x38] bl G_M000_IG46 G_M000_IG22: b G_M000_IG38 G_M000_IG23: movz x27, #0xD1FFAB1E movk x27, #0xD1FFAB1E LSL #16 movk x27, #0xD1FFAB1E LSL #32 sub x11, x27, #64 ldr x1, [x11] blr x1 cbz w0, G_M000_IG37 G_M000_IG24: ldr x0, [fp, #0x18] ldr x11, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 cmp x11, x1 bne G_M000_IG36 G_M000_IG25: mov x11, x0 ldr w1, [x11, #0x14] tbnz w1, #31, G_M000_IG32 add x11, x11, #24 ldr x28, [x11] G_M000_IG26: mov w21, wzr ldr w23, [x28, #0x08] cmp w23, #0 ble G_M000_IG29 G_M000_IG27: ubfiz x11, x21, #4, #32 add x11, x11, #16 ldr x11, [x28, x11] cbnz x11, G_M000_IG33 G_M000_IG28: add w21, w21, #1 cmp w23, w21 bgt G_M000_IG27 G_M000_IG29: sub x11, x27, #64 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG24 G_M000_IG30: b G_M000_IG37 G_M000_IG31: ubfiz x1, x21, #4, #32 add x1, x1, #16 add x1, x28, x1 mov x2, xzr swpal x2, x24, [x1] cbz x24, G_M000_IG28 ldrb w1, [x22, #0x9D] cbz w1, G_M000_IG28 mov x0, x24 bl System.Runtime.CompilerServices.RuntimeHelpers:GetHashCode(System.Object):int mov w25, w0 ldr w24, [x24, #0x08] mov x0, x19 bl System.Runtime.CompilerServices.RuntimeHelpers:GetHashCode(System.Object):int mov w4, w0 mov x0, x22 mov w2, w25 mov w3, w24 mov w1, #4 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 ldr x0, [fp, #0x18] b G_M000_IG28 G_M000_IG32: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 brk_windows #0 G_M000_IG33: ubfiz x11, x21, #4, #32 add x11, x11, #16 add x11, x28, x11 ldr w11, [x11, #0x08] cbnz w11, G_M000_IG35 G_M000_IG34: ubfiz x11, x21, #4, #32 add x11, x11, #16 add x11, x28, x11 str w20, [x11, #0x08] b G_M000_IG28 G_M000_IG35: sub w11, w20, w11 sxtw x11, w11 mov w1, w26 cmp x11, x1 bge G_M000_IG31 b G_M000_IG28 G_M000_IG36: sub x11, x27, #56 ldr x1, [x11] blr x1 mov x28, x0 ldr x0, [fp, #0x18] b G_M000_IG26 G_M000_IG37: ldr x0, [fp, #0x18] sub x11, x27, #48 ldr x1, [x11] blr x1 G_M000_IG38: mov w0, #1 G_M000_IG39: ldp x27, x28, [sp, #0x80] ldp x25, x26, [sp, #0x70] ldp x23, x24, [sp, #0x60] ldp x21, x22, [sp, #0x50] ldp x19, x20, [sp, #0x40] ldp fp, lr, [sp], #0x90 ret lr G_M000_IG40: mov x0, x22 mov w3, w21 mov w2, w20 mov w1, #5 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 b G_M000_IG03 G_M000_IG41: ldrb w0, [x22, #0x9D] cbnz w0, G_M000_IG42 ldr x0, [x19, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x28] b G_M000_IG07 G_M000_IG42: ldr x0, [x19, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] b G_M000_IG15 G_M000_IG43: stp fp, lr, [sp, #-0x70]! stp x19, x20, [sp, #0x20] stp x21, x22, [sp, #0x30] stp x23, x24, [sp, #0x40] stp x25, x26, [sp, #0x50] stp x27, x28, [sp, #0x60] add x3, fp, #144 str x3, [sp, #0x18] G_M000_IG44: ldr x0, [fp, #0x28] cbz x0, G_M000_IG45 movz x27, #0xD1FFAB1E movk x27, #0xD1FFAB1E LSL #16 movk x27, #0xD1FFAB1E LSL #32 add x11, x27, #16 ldr x1, [x11] blr x1 G_M000_IG45: ldp x27, x28, [sp, #0x60] ldp x25, x26, [sp, #0x50] ldp x23, x24, [sp, #0x40] ldp x21, x22, [sp, #0x30] ldp x19, x20, [sp, #0x20] ldp fp, lr, [sp], #0x70 ret lr G_M000_IG46: stp fp, lr, [sp, #-0x70]! stp x19, x20, [sp, #0x20] stp x21, x22, [sp, #0x30] stp x23, x24, [sp, #0x40] stp x25, x26, [sp, #0x50] stp x27, x28, [sp, #0x60] add x3, fp, #144 str x3, [sp, #0x18] G_M000_IG47: ldr x0, [fp, #0x20] cbz x0, G_M000_IG48 movz x27, #0xD1FFAB1E movk x27, #0xD1FFAB1E LSL #16 movk x27, #0xD1FFAB1E LSL #32 sub x11, x27, #16 ldr x1, [x11] blr x1 G_M000_IG48: ldp x27, x28, [sp, #0x60] ldp x25, x26, [sp, #0x50] ldp x23, x24, [sp, #0x40] ldp x21, x22, [sp, #0x30] ldp x19, x20, [sp, #0x20] ldp fp, lr, [sp], #0x70 ret lr G_M000_IG49: stp fp, lr, [sp, #-0x70]! stp x19, x20, [sp, #0x20] stp x21, x22, [sp, #0x30] stp x23, x24, [sp, #0x40] stp x25, x26, [sp, #0x50] stp x27, x28, [sp, #0x60] add x3, fp, #144 str x3, [sp, #0x18] G_M000_IG50: ldr x0, [fp, #0x18] cbz x0, G_M000_IG51 movz x27, #0xD1FFAB1E movk x27, #0xD1FFAB1E LSL #16 movk x27, #0xD1FFAB1E LSL #32 sub x11, x27, #48 ldr x1, [x11] blr x1 G_M000_IG51: ldp x27, x28, [sp, #0x60] ldp x25, x26, [sp, #0x50] ldp x23, x24, [sp, #0x40] ldp x21, x22, [sp, #0x30] ldp x19, x20, [sp, #0x20] ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 1384 1034: JIT compiled System.Buffers.TlsOverPerCoreLockedStacksArrayPool`1[ushort]:Trim() [Tier1 with Static PGO, IL size=523, code size=1384] ; Assembly listing for method System.Buffers.Utilities:GetMemoryPressure():int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 71 ; 0 inlinees with PGO data; 5 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, wzr movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [x0, #0x18] scvtf d16, x1 ldr x0, [x0, #0x08] scvtf d17, x0 ldr d18, [@RWD00] fmul d18, d17, d18 fcmp d16, d18 bge G_M000_IG04 ldr d18, [@RWD08] fmul d17, d17, d18 fcmp d16, d17 cset x0, ge G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG04: mov w0, #2 G_M000_IG05: ldp fp, lr, [sp], #0x10 ret lr RWD00 dq 3FECCCCCCCCCCCCDh ; 0.9 RWD08 dq 3FE6666666666666h ; 0.7 ; Total bytes of code 100 1035: JIT compiled System.Buffers.Utilities:GetMemoryPressure() [Tier1 with Static PGO, IL size=68, code size=100] ; Assembly listing for method System.GC:GetGCMemoryInfo(int):System.GCMemoryInfo ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 100 ; 0 inlinees with PGO data; 3 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x40]! stp x19, x20, [sp, #0x18] stp x21, x22, [sp, #0x28] str x23, [sp, #0x38] mov fp, sp mov w19, w0 G_M000_IG02: cmp w19, #0 ccmp w19, #3, 0, ge bgt G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x20, x0 mov w1, w19 bl System.GC:GetMemoryInfo(System.GCMemoryInfoData,int) mov x0, x20 G_M000_IG03: ldr x23, [sp, #0x38] ldp x21, x22, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 mov x20, x0 str wzr, [x19, #0x08] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x21, x0 mov w0, #3 str w0, [x21, #0x08] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x22, x0 mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov x23, x0 mov x2, x21 mov x1, x19 mov x0, x20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x2, x0 mov x1, x23 mov x0, x22 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x22 bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 284 1036: JIT compiled System.GC:GetGCMemoryInfo(int) [Tier1 with Static PGO, IL size=61, code size=284] ; Assembly listing for method System.Diagnostics.Tracing.EventSource:WriteEvent(int,int,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 8 single block inlinees; 0 inlinees without PGO data G_M000_IG01: sub sp, sp, #32 stp fp, lr, [sp, #0x10] add fp, sp, #16 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 str x4, [fp, #-0x10] str w2, [fp, #-0x04] str w3, [fp, #-0x08] G_M000_IG02: ldrb w4, [x0, #0x9D] cbz w4, G_M000_IG04 G_M000_IG03: ldr wzr, [sp], #-0x20 mov x4, sp sub x2, fp, #4 str x2, [x4] mov w2, #4 stp w2, wzr, [x4, #0x08] sub x2, fp, #8 str x2, [x4, #0x10] mov w2, #4 stp w2, wzr, [x4, #0x18] mov x2, xzr mov w3, #2 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 G_M000_IG04: movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #-0x10] cmp xip0, xip1 beq G_M000_IG05 bl CORINFO_HELP_FAIL_FAST G_M000_IG05: sub sp, fp, #16 ldp fp, lr, [sp, #0x10] add sp, sp, #32 ret lr ; Total bytes of code 156 1037: JIT compiled System.Diagnostics.Tracing.EventSource:WriteEvent(int,int,int) [Tier1, IL size=97, code size=156] ; Assembly listing for method System.Runtime.CompilerServices.ConditionalWeakTable`2[System.__Canon,System.__Canon]:System.Collections.Generic.IEnumerable>.GetEnumerator():System.Collections.Generic.IEnumerator`1[System.Collections.Generic.KeyValuePair`2[System.__Canon,System.__Canon]]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; PGO data available, but IL did not match ; 1 inlinees with PGO data; 4 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x40]! str x19, [sp, #0x38] mov fp, sp add x1, sp, #64 str x1, [fp, #0x30] str x0, [fp, #0x28] str x0, [fp, #0x18] G_M000_IG02: ldr x1, [x0, #0x08] str x1, [fp, #0x10] str wzr, [fp, #0x20] G_M000_IG03: ldrb w2, [fp, #0x20] cbnz w2, G_M000_IG07 add x1, fp, #32 ldr x0, [fp, #0x10] bl System.Threading.Monitor:ReliableEnter(System.Object,byref) ldr x0, [fp, #0x18] ldr x1, [x0, #0x10] dmb ishld cbz x1, G_M000_IG09 G_M000_IG04: ldr w1, [x1, #0x28] cbz w1, G_M000_IG09 ldr x1, [x0] ldr x2, [x1, #0x30] ldr x2, [x2] ldr x2, [x2, #0x30] cbz x2, G_M000_IG08 G_M000_IG05: mov x0, x2 bl CORINFO_HELP_NEWFAST mov x19, x0 add x14, x19, #8 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF ldr x15, [fp, #0x18] ldr w0, [x15, #0x18] add w0, w0, #1 str w0, [x15, #0x18] ldr x0, [x15, #0x10] dmb ishld ldr w0, [x0, #0x28] sub w0, w0, #1 str w0, [x19, #0x10] movn w0, #0 str w0, [x19, #0x14] G_M000_IG06: b G_M000_IG13 G_M000_IG07: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 brk_windows #0 G_M000_IG08: mov x0, x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS mov x2, x0 b G_M000_IG05 G_M000_IG09: ldr x1, [x0] ldr x2, [x1, #0x30] ldr x2, [x2] ldr x2, [x2, #0x28] cbz x2, G_M000_IG11 G_M000_IG10: b G_M000_IG12 G_M000_IG11: mov x0, x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS mov x2, x0 G_M000_IG12: mov x0, x2 bl CORINFO_HELP_GETGENERICS_GCSTATIC_BASE ldr x19, [x0] ldr x15, [fp, #0x18] b G_M000_IG06 G_M000_IG13: ldrb w0, [fp, #0x20] cbz w0, G_M000_IG15 G_M000_IG14: ldr x0, [fp, #0x10] bl System.Threading.Monitor:Exit(System.Object) ldr x15, [fp, #0x18] G_M000_IG15: mov x0, x19 G_M000_IG16: ldr x19, [sp, #0x38] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG17: stp fp, lr, [sp, #-0x20]! str x19, [sp, #0x18] add x3, fp, #64 str x3, [sp, #0x10] G_M000_IG18: ldrb w0, [fp, #0x20] cbz w0, G_M000_IG19 ldr x0, [fp, #0x10] bl System.Threading.Monitor:Exit(System.Object) G_M000_IG19: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 376 1038: JIT compiled System.Runtime.CompilerServices.ConditionalWeakTable`2[System.__Canon,System.__Canon]:System.Collections.Generic.IEnumerable>.GetEnumerator() [Tier1, IL size=69, code size=376] ; Assembly listing for method System.Runtime.CompilerServices.ConditionalWeakTable`2+Enumerator[System.__Canon,System.__Canon]:.ctor(System.Runtime.CompilerServices.ConditionalWeakTable`2[System.__Canon,System.__Canon]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 2 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: add x14, x0, #8 mov x15, x1 bl CORINFO_HELP_ASSIGN_REF ldr w2, [x1, #0x18] add w2, w2, #1 str w2, [x1, #0x18] ldr x1, [x1, #0x10] dmb ishld ldr w1, [x1, #0x28] sub w1, w1, #1 str w1, [x0, #0x10] movn w1, #0 str w1, [x0, #0x14] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 68 1039: JIT compiled System.Runtime.CompilerServices.ConditionalWeakTable`2+Enumerator[System.__Canon,System.__Canon]:.ctor(System.Runtime.CompilerServices.ConditionalWeakTable`2[System.__Canon,System.__Canon]) [Tier1, IL size=56, code size=68] ; Assembly listing for method System.Runtime.CompilerServices.ConditionalWeakTable`2+Enumerator[System.__Canon,System.__Canon]:Dispose():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 91 ; 1 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x40]! str x19, [sp, #0x38] mov fp, sp add x1, sp, #64 str x1, [fp, #0x30] str x0, [fp, #0x28] str x0, [fp, #0x18] G_M000_IG02: ldr xzr, [x0] add x1, x0, #8 mov x2, xzr swpal x2, x19, [x1] cbz x19, G_M000_IG08 stp xzr, xzr, [x0, #0x18] ldr x1, [x19, #0x08] str x1, [fp, #0x10] str wzr, [fp, #0x20] G_M000_IG03: ldrb w2, [fp, #0x20] cbnz w2, G_M000_IG04 add x1, fp, #32 ldr x0, [fp, #0x10] bl System.Threading.Monitor:ReliableEnter(System.Object,byref) b G_M000_IG05 G_M000_IG04: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 brk_windows #0 G_M000_IG05: ldr w0, [x19, #0x18] sub w0, w0, #1 str w0, [x19, #0x18] G_M000_IG06: ldrb w0, [fp, #0x20] cbz w0, G_M000_IG07 ldr x0, [fp, #0x10] bl System.Threading.Monitor:Exit(System.Object) G_M000_IG07: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x18] G_M000_IG08: ldr x19, [sp, #0x38] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG09: stp fp, lr, [sp, #-0x20]! str x19, [sp, #0x18] add x3, fp, #64 str x3, [sp, #0x10] G_M000_IG10: ldrb w0, [fp, #0x20] cbz w0, G_M000_IG11 ldr x0, [fp, #0x10] bl System.Threading.Monitor:Exit(System.Object) G_M000_IG11: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 224 1040: JIT compiled System.Runtime.CompilerServices.ConditionalWeakTable`2+Enumerator[System.__Canon,System.__Canon]:Dispose() [Tier1 with Static PGO, IL size=78, code size=224] ; Assembly listing for method System.GC:SuppressFinalize(System.Object) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 1 inlinees with PGO data; 0 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: cbz x0, G_M000_IG04 G_M000_IG03: ldp fp, lr, [sp], #0x10 b System.GC:_SuppressFinalize(System.Object) G_M000_IG04: mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 brk_windows #0 ; Total bytes of code 64 1041: JIT compiled System.GC:SuppressFinalize(System.Object) [Tier1, IL size=18, code size=64] ; Assembly listing for method System.GC:ReRegisterForFinalize(System.Object) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 1 inlinees with PGO data; 0 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: cbz x0, G_M000_IG04 G_M000_IG03: ldp fp, lr, [sp], #0x10 b System.GC:_ReRegisterForFinalize(System.Object) G_M000_IG04: mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 brk_windows #0 ; Total bytes of code 64 1042: JIT compiled System.GC:ReRegisterForFinalize(System.Object) [Tier1, IL size=18, code size=64] ; Assembly listing for method System.Runtime.ConstrainedExecution.CriticalFinalizerObject:Finalize():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 29149 ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 16 1043: JIT compiled System.Runtime.ConstrainedExecution.CriticalFinalizerObject:Finalize() [Tier1 with Static PGO, IL size=10, code size=16] ; Assembly listing for method System.Number:WriteTwoDigits[ushort](uint,ulong) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] add x2, x2, #16 lsl w0, w0, #2 mov w0, w0 add x0, x2, x0 ldr w0, [x0] str w0, [x1] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 56 1044: JIT compiled System.Number:WriteTwoDigits[ushort](uint,ulong) [Tier1, IL size=75, code size=56] ; Assembly listing for method System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[ubyte](ubyte[]):byref ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldrsb wzr, [x0] add x0, x0, #16 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 24 1045: JIT compiled System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[ubyte](ubyte[]) [Tier1, IL size=7, code size=24] ; Assembly listing for method System.Runtime.CompilerServices.Unsafe:CopyBlockUnaligned(byref,byref,uint) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w2, w2 bl CORINFO_HELP_MEMCPY G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 24 1046: JIT compiled System.Runtime.CompilerServices.Unsafe:CopyBlockUnaligned(byref,byref,uint) [Tier1, IL size=9, code size=24] ; Assembly listing for method System.Math:DivRem(ulong,ulong):System.ValueTuple`2[ulong,ulong] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: cmp x1, #0 beq G_M000_IG04 udiv x2, x0, x1 msub x1, x2, x1, x0 mov x0, x2 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG04: bl CORINFO_HELP_THROWDIVZERO brk_windows #0 ; Total bytes of code 44 1047: JIT compiled System.Math:DivRem(ulong,ulong) [Tier1, IL size=16, code size=44] ; Assembly listing for method System.Text.StringBuilder:Append(ushort):System.Text.StringBuilder:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 120042 G_M000_IG01: stp fp, lr, [sp, #-0x20]! str x19, [sp, #0x18] mov fp, sp mov x19, x0 G_M000_IG02: ldr w0, [x19, #0x18] mov w2, w0 ldr x3, [x19, #0x08] ldr w4, [x3, #0x08] cmp w4, w2 bls G_M000_IG06 G_M000_IG03: add x3, x3, #16 strh w1, [x3, w2, UXTW #2] add w1, w0, #1 str w1, [x19, #0x18] G_M000_IG04: mov x0, x19 G_M000_IG05: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG06: uxth w1, w1 mov x0, x19 mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG04 ; Total bytes of code 108 1048: JIT compiled System.Text.StringBuilder:Append(ushort) [Tier1 with Static PGO, IL size=51, code size=108] ; Assembly listing for method Perfolizer.Horology.TimeInterval:get_Nanoseconds():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr d0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1049: JIT compiled Perfolizer.Horology.TimeInterval:get_Nanoseconds() [Tier1, IL size=7, code size=20] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:get_Nanoseconds():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr d0, [x0, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1050: JIT compiled BenchmarkDotNet.Reports.Measurement:get_Nanoseconds() [Tier1, IL size=7, code size=20] ; Assembly listing for method BenchmarkDotNet.Engines.IterationData:get_IterationStage():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w0, [x0, #0x04] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1051: JIT compiled BenchmarkDotNet.Engines.IterationData:get_IterationStage() [Tier1, IL size=7, code size=20] ; Assembly listing for method System.Number+BigInteger:ShiftLeft(uint):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 4 ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x10] stp x21, x22, [sp, #0x20] mov fp, sp mov x19, x0 G_M000_IG02: ldr w0, [x19] cbnz w0, G_M000_IG11 G_M000_IG03: ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: add w22, w22, #1 add w0, w22, #1 str w0, [x19] neg w0, w20 add w0, w0, #32 mov w2, wzr b G_M000_IG09 G_M000_IG05: add x0, x19, #4 sbfiz x2, x22, #2, #32 add x0, x0, x2 add x2, x19, #4 ldr w2, [x2, w21, SXTW #2] str w2, [x0] sub w21, w21, #1 sub w22, w22, #1 G_M000_IG06: tbz w21, #31, G_M000_IG05 ldr w0, [x19] add w0, w0, w1 str w0, [x19] mov x0, x19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG07: ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG08: add x5, x19, #4 orr w2, w2, w4 str w2, [x5, w22, SXTW #2] lsl w2, w3, w20 sub w21, w21, #1 sub w22, w22, #1 G_M000_IG09: add x3, x19, #4 ldr w3, [x3, w21, SXTW #2] lsr w4, w3, w0 cmp w21, #0 bgt G_M000_IG08 add x0, x19, #4 orr w2, w2, w4 str w2, [x0, w22, SXTW #2] add x0, x19, #4 sub w2, w22, #1 lsl w3, w3, w20 str w3, [x0, w2, SXTW #2] mov x0, x19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, x19, #4 ldr w1, [x19] sub w1, w1, #1 ldr w0, [x0, w1, SXTW #2] cbnz w0, G_M000_IG10 ldr w0, [x19] sub w0, w0, #1 str w0, [x19] G_M000_IG10: ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG11: cbz w1, G_M000_IG03 and w20, w1, #31 lsr w1, w1, #5 sub w21, w0, #1 add w22, w21, w1 cbz w20, G_M000_IG06 b G_M000_IG04 ; Total bytes of code 332 1052: JIT compiled System.Number+BigInteger:ShiftLeft(uint) [Tier1 with Static PGO, IL size=337, code size=332] ; Assembly listing for method System.Number:ExtractFractionAndBiasedExponent(double,byref):ulong ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 82 G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov x1, v0.d[0] and x2, x1, #0xD1FFAB1E lsr x1, x1, #52 and w1, w1, #0xD1FFAB1E str w1, [x0] ldr w1, [x0] cbz w1, G_M000_IG05 orr x2, x2, #0xD1FFAB1E sub w1, w1, #0xD1FFAB1E str w1, [x0] G_M000_IG03: mov x0, x2 G_M000_IG04: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG05: movn w1, #0xD1FFAB1E str w1, [x0] b G_M000_IG03 ; Total bytes of code 72 1053: JIT compiled System.Number:ExtractFractionAndBiasedExponent(double,byref) [Tier1 with Static PGO, IL size=69, code size=72] ; Assembly listing for method System.Number+BigInteger:Clear(uint):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 1 inlinees with PGO data; 2 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp G_M000_IG02: ldrsb wzr, [x0] add x0, x0, #4 lsl w1, w1, #2 mov w1, w1 str x1, [fp, #0x18] cbz x1, G_M000_IG05 G_M000_IG03: cmp x1, #0xD1FFAB1E bhi G_M000_IG06 G_M000_IG04: mov w1, wzr ldr w2, [fp, #0x18] bl CORINFO_HELP_MEMSET G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG06: ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] G_M000_IG07: ldp fp, lr, [sp], #0x20 br x2 ; Total bytes of code 88 1054: JIT compiled System.Number+BigInteger:Clear(uint) [Tier1, IL size=26, code size=88] ; Assembly listing for method System.Number+BigInteger:SetUInt64(byref,ulong) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 4 G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov x2, #0xD1FFAB1E cmp x1, x2 bls G_M000_IG04 str w1, [x0, #0x04] lsr x1, x1, #32 str w1, [x0, #0x08] mov w1, #2 str w1, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG04: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] G_M000_IG05: ldp fp, lr, [sp], #0x10 br x2 ; Total bytes of code 72 1055: JIT compiled System.Number+BigInteger:SetUInt64(byref,ulong) [Tier1 with Static PGO, IL size=55, code size=72] ; Assembly listing for method System.Number+BigInteger:Multiply(byref,uint,byref) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 4 ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x18] str x21, [sp, #0x28] mov fp, sp mov w20, w1 mov x19, x2 mov x2, x0 G_M000_IG02: ldr w1, [x2] cmp w1, #1 ble G_M000_IG07 cmp w20, #1 bls G_M000_IG09 mov w3, wzr mov w4, wzr cmp w1, #0 ble G_M000_IG05 G_M000_IG03: add x0, x2, #4 mov w21, w20 G_M000_IG04: sbfiz x2, x3, #2, #32 ldr w5, [x0, x2] mov w4, w4 madd x4, x5, x21, x4 ldrsb wzr, [x19] add x5, x19, #4 str w4, [x5, x2] lsr x4, x4, #32 add w3, w3, #1 cmp w3, w1 blt G_M000_IG04 G_M000_IG05: cbnz w4, G_M000_IG12 str w1, [x19] G_M000_IG06: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG07: mov x0, x2 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov w1, w0 mov w21, w20 mul x1, x1, x21 mov x0, x19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] G_M000_IG08: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 br x2 G_M000_IG09: cbnz w20, G_M000_IG10 str wzr, [x19] b G_M000_IG06 G_M000_IG10: mov x0, x19 mov x1, x2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] G_M000_IG11: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 br x2 G_M000_IG12: ldrsb wzr, [x19] add x0, x19, #4 str w4, [x0, w3, SXTW #2] add w0, w1, #1 str w0, [x19] b G_M000_IG06 ; Total bytes of code 288 1056: JIT compiled System.Number+BigInteger:Multiply(byref,uint,byref) [Tier1 with Static PGO, IL size=158, code size=288] ; Assembly listing for method System.String:Ctor(System.ReadOnlySpan`1[ushort]):System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 103944 ; 1 inlinees with PGO data; 2 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x18] str x21, [sp, #0x28] mov fp, sp mov x20, x0 mov w19, w1 G_M000_IG02: cbz w19, G_M000_IG05 G_M000_IG03: mov w0, w19 bl System.String:FastAllocateString(int):System.String mov x21, x0 ldrsb wzr, [x21] add x0, x21, #12 mov w2, w19 lsl x2, x2, #1 mov x1, x20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x21 G_M000_IG04: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG05: movz x0, #8 movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG06: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 128 1057: JIT compiled System.String:Ctor(System.ReadOnlySpan`1[ushort]) [Tier1 with Static PGO, IL size=55, code size=128] ; Assembly listing for method Perfolizer.Horology.Frequency:.ctor(double):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: str d0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1058: JIT compiled Perfolizer.Horology.Frequency:.ctor(double) [Tier1, IL size=8, code size=20] ; Assembly listing for method Perfolizer.Horology.Frequency:get_Hertz():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr d0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1059: JIT compiled Perfolizer.Horology.Frequency:get_Hertz() [Tier1, IL size=7, code size=20] ; Assembly listing for method System.Enum:ToString():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; PGO data available, but IL did not match ; 5 inlinees with PGO data; 21 single block inlinees; 19 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x18] str x21, [sp, #0x28] mov fp, sp mov x19, x0 G_M000_IG02: mov x0, x19 bl System.Object:GetType():System.Type:this mov x20, x0 add x21, x19, #8 ldr x0, [x19] bl System.Enum:InternalGetCorElementType(ulong):ubyte sub w19, w0, #4 cmp w19, #7 bhi G_M000_IG52 mov w0, w19 adr x1, [@RWD00] ldr w1, [x1, x0, LSL #2] adr x2, [G_M000_IG02] add x1, x1, x2 br x1 G_M000_IG03: mov x0, x20 mov x1, x21 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG53 G_M000_IG04: ldrb w21, [x21] ldr x19, [x20, #0x10] cbz x19, G_M000_IG12 G_M000_IG05: ldr x0, [x19] G_M000_IG06: cbz x0, G_M000_IG11 G_M000_IG07: ldr x2, [x0, #0x78] G_M000_IG08: cbz x2, G_M000_IG13 G_M000_IG09: ldr x0, [x2] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 cmp x0, x1 bne G_M000_IG13 G_M000_IG10: ldr x0, [x2, #0x10] cbz x0, G_M000_IG13 mov x0, x2 b G_M000_IG14 G_M000_IG11: mov x2, xzr b G_M000_IG08 G_M000_IG12: mov x0, xzr b G_M000_IG06 G_M000_IG13: mov x0, x20 mov w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG14: ldrb w1, [x0, #0x18] cbnz w1, G_M000_IG23 ldr x20, [x0, #0x10] ldrb w1, [x0, #0x19] cbz w1, G_M000_IG15 ldr w19, [x20, #0x08] cmp w19, w21 bls G_M000_IG21 add x0, x20, #16 ldr x0, [x0, w21, UXTW #3] b G_M000_IG22 G_M000_IG15: ldr x0, [x0, #0x08] cbz x0, G_M000_IG18 G_M000_IG16: add x3, x0, #16 ldr w2, [x0, #0x08] G_M000_IG17: ldr w0, [x0, #0x08] cmp w0, #32 ble G_M000_IG19 mov x0, x3 mov w1, w2 mov w2, w21 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG20 G_M000_IG18: mov x3, xzr mov w2, wzr b G_M000_IG17 G_M000_IG19: mov x0, x3 mov w1, w21 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG20: ldr w19, [x20, #0x08] cmp w19, w0 bls G_M000_IG21 add x1, x20, #16 ldr x0, [x1, w0, UXTW #3] b G_M000_IG22 G_M000_IG21: mov x0, xzr G_M000_IG22: b G_M000_IG24 G_M000_IG23: mov w1, w21 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG24: cbnz x0, G_M000_IG25 mov w0, w21 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG25: b G_M000_IG53 G_M000_IG26: mov x0, x20 mov x1, x21 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG53 G_M000_IG27: mov x0, x20 mov x1, x21 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG53 G_M000_IG28: ldr w21, [x21] ldr x19, [x20, #0x10] cbz x19, G_M000_IG36 G_M000_IG29: ldr x0, [x19] G_M000_IG30: cbz x0, G_M000_IG35 G_M000_IG31: ldr x2, [x0, #0x78] G_M000_IG32: cbz x2, G_M000_IG37 G_M000_IG33: ldr x0, [x2] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 cmp x0, x1 bne G_M000_IG37 G_M000_IG34: ldr x0, [x2, #0x10] cbz x0, G_M000_IG37 mov x0, x2 b G_M000_IG38 G_M000_IG35: mov x2, xzr b G_M000_IG32 G_M000_IG36: mov x0, xzr b G_M000_IG30 G_M000_IG37: mov x0, x20 mov w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG38: ldrb w1, [x0, #0x18] cbnz w1, G_M000_IG46 ldr x20, [x0, #0x10] ldrb w1, [x0, #0x19] cbz w1, G_M000_IG39 mov w0, w21 ldr w19, [x20, #0x08] cmp w19, w0 bls G_M000_IG44 add x0, x20, #16 ldr x0, [x0, w21, UXTW #3] b G_M000_IG45 G_M000_IG39: ldr x0, [x0, #0x08] cbnz x0, G_M000_IG40 mov x3, xzr mov w2, wzr b G_M000_IG41 G_M000_IG40: add x3, x0, #16 ldr w2, [x0, #0x08] G_M000_IG41: ldr w0, [x0, #0x08] cmp w0, #32 ble G_M000_IG42 mov x0, x3 mov w1, w2 mov w2, w21 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG43 G_M000_IG42: mov x0, x3 mov w1, w21 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG43: ldr w19, [x20, #0x08] cmp w19, w0 bls G_M000_IG44 add x1, x20, #16 ldr x0, [x1, w0, UXTW #3] b G_M000_IG45 G_M000_IG44: mov x0, xzr G_M000_IG45: b G_M000_IG47 G_M000_IG46: mov w1, w21 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG47: cbnz x0, G_M000_IG48 mov w0, w21 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG48: b G_M000_IG53 G_M000_IG49: mov x0, x20 mov x1, x21 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG53 G_M000_IG50: mov x0, x20 mov x1, x21 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG53 G_M000_IG51: mov x0, x20 mov x1, x21 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG53 G_M000_IG52: mov x0, x20 mov x1, x21 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG53: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 ret lr RWD00 dd G_M000_IG03 - G_M000_IG02 dd G_M000_IG04 - G_M000_IG02 dd G_M000_IG26 - G_M000_IG02 dd G_M000_IG27 - G_M000_IG02 dd G_M000_IG28 - G_M000_IG02 dd G_M000_IG49 - G_M000_IG02 dd G_M000_IG50 - G_M000_IG02 dd G_M000_IG51 - G_M000_IG02 ; Total bytes of code 1016 1060: JIT compiled System.Enum:ToString() [Tier1, IL size=158, code size=1016] ; Assembly listing for method System.Enum:g__InitializeEnumInfo|7_0[uint](System.RuntimeType,bool):System.Enum+EnumInfo`1[uint] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 2 inlinees with PGO data; 9 single block inlinees; 2 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0xD0]! stp x19, x20, [sp, #0x80] stp x21, x22, [sp, #0x90] stp x23, x24, [sp, #0xA0] stp x25, x26, [sp, #0xB0] stp x27, x28, [sp, #0xC0] mov fp, sp str xzr, [fp, #0x70] str xzr, [fp, #0x68] str x0, [fp, #0x78] mov w19, w1 G_M000_IG02: add x0, fp, #24 mov x1, x12 bl CORINFO_HELP_INIT_PINVOKE_FRAME mov x20, x0 mov x0, sp str x0, [fp, #0x38] mov x0, fp str x0, [fp, #0x48] movi v16.4s, #0 str q16, [fp, #0x58] add x0, fp, #120 str x0, [fp, #0x58] ldr x0, [fp, #0x78] add x21, fp, #88 cbz x0, G_M000_IG19 G_M000_IG03: ldr x22, [x0, #0x18] G_M000_IG04: str x22, [x21, #0x08] ldp x0, x1, [fp, #0x58] add x2, fp, #112 add x3, fp, #104 tst w19, #255 bne G_M000_IG06 G_M000_IG05: mov w4, wzr b G_M000_IG07 G_M000_IG06: mov w4, #1 G_M000_IG07: movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 str x5, [fp, #0x28] adr x5, [G_M000_IG10] str x5, [fp, #0x40] add x5, fp, #24 str x5, [x20, #0x10] strb wzr, [x20, #0x0C] G_M000_IG08: movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 G_M000_IG09: blr x5 G_M000_IG10: mov w0, #1 strb w0, [x20, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG11 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG11: ldr x0, [fp, #0x20] str x0, [x20, #0x10] ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 mov w2, wzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 mov w21, w0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x22, x0 ldp x20, x19, [fp, #0x68] strb w21, [x22, #0x18] add x14, x22, #8 mov x15, x19 bl CORINFO_HELP_ASSIGN_REF add x14, x22, #16 mov x15, x20 bl CORINFO_HELP_ASSIGN_REF mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG13 G_M000_IG12: cbz x19, G_M000_IG20 ldr w4, [x19, #0x08] mov x1, x19 mov x2, x20 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w3, wzr mov x5, xzr movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 G_M000_IG13: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 strb w0, [x22, #0x19] ldr x0, [fp, #0x78] ldr x1, [x0, #0x10] cbz x1, G_M000_IG16 G_M000_IG14: ldr x1, [x0, #0x10] ldr x1, [x1] cbz x1, G_M000_IG16 G_M000_IG15: b G_M000_IG17 G_M000_IG16: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x1, x0 G_M000_IG17: add x14, x1, #120 mov x15, x22 bl CORINFO_HELP_ASSIGN_REF mov x0, x22 G_M000_IG18: ldp x27, x28, [sp, #0xC0] ldp x25, x26, [sp, #0xB0] ldp x23, x24, [sp, #0xA0] ldp x21, x22, [sp, #0x90] ldp x19, x20, [sp, #0x80] ldp fp, lr, [sp], #0xD0 ret lr G_M000_IG19: mov x22, xzr b G_M000_IG04 G_M000_IG20: mov w0, #75 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 brk_windows #0 ; Total bytes of code 584 1061: JIT compiled System.Enum:g__InitializeEnumInfo|7_0[uint](System.RuntimeType,bool) [Tier1, IL size=73, code size=584] ; Assembly listing for method System.RuntimeType:IsDefined(System.Type,bool):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 4262 ; 1 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! stp x19, x20, [sp, #0x10] mov fp, sp mov x19, x0 mov w20, w2 G_M000_IG02: cbz x1, G_M000_IG08 ldr x0, [x1] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 cmp x0, x2 bne G_M000_IG07 G_M000_IG03: cbz x1, G_M000_IG09 G_M000_IG04: ldr x2, [x1] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 cmp x2, x0 bne G_M000_IG09 G_M000_IG05: uxtb w2, w20 mov x0, x19 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG06: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 br x3 G_M000_IG07: mov x0, x1 ldr x1, [x1] ldr x1, [x1, #0x58] ldr x1, [x1] blr x1 mov x1, x0 b G_M000_IG03 G_M000_IG08: mov w0, #233 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 brk_windows #0 G_M000_IG09: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 mov x20, x0 mov w0, #233 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov x2, x0 mov x1, x20 mov x0, x19 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x19 bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 292 1062: JIT compiled System.RuntimeType:IsDefined(System.Type,bool) [Tier1 with Static PGO, IL size=51, code size=292] ; Assembly listing for method System.Reflection.CustomAttribute:IsDefined(System.RuntimeType,System.RuntimeType,bool):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 4262 ; 0 inlinees with PGO data; 8 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x10] stp x21, x22, [sp, #0x20] mov fp, sp mov x19, x0 mov x20, x1 mov w21, w2 G_M000_IG02: ldrsb wzr, [x19] mov x0, x19 bl System.RuntimeTypeHandle:GetElementType(System.RuntimeType):System.RuntimeType cbnz x0, G_M000_IG09 mov x0, x19 mov x1, x20 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG11 mov x0, x19 bl System.RuntimeTypeHandle:GetModule(System.RuntimeType):System.Reflection.RuntimeModule mov x22, x0 mov x0, x19 bl System.RuntimeTypeHandle:GetToken(System.RuntimeType):int mov w1, w0 mov x0, x22 mov x2, x20 mov w3, wzr mov w4, wzr movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 cbnz w0, G_M000_IG11 G_M000_IG03: uxtb w21, w21 cbz w21, G_M000_IG09 G_M000_IG04: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x19, x0 cbz x19, G_M000_IG09 G_M000_IG05: ldr x0, [x19] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 cmp x0, x1 bne G_M000_IG09 G_M000_IG06: ldrsb wzr, [x19] mov x0, x19 bl System.RuntimeTypeHandle:GetModule(System.RuntimeType):System.Reflection.RuntimeModule mov x22, x0 mov x0, x19 bl System.RuntimeTypeHandle:GetToken(System.RuntimeType):int mov w1, w0 mov w4, w21 mov x0, x22 mov x2, x20 mov w3, wzr movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 cbnz w0, G_M000_IG11 G_M000_IG07: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x19, x0 cbz x19, G_M000_IG09 G_M000_IG08: ldr x0, [x19] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 cmp x0, x1 beq G_M000_IG06 G_M000_IG09: mov w0, wzr G_M000_IG10: ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG11: mov w0, #1 G_M000_IG12: ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 368 1063: JIT compiled System.Reflection.CustomAttribute:IsDefined(System.RuntimeType,System.RuntimeType,bool) [Tier1 with Static PGO, IL size=105, code size=368] ; Assembly listing for method System.Reflection.PseudoCustomAttribute:IsDefined(System.RuntimeType,System.RuntimeType):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 4262 ; 2 inlinees with PGO data; 3 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x10] stp x21, x22, [sp, #0x20] mov fp, sp mov x20, x0 mov x19, x1 G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 cmp x19, x0 beq G_M000_IG14 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 cmp x19, x0 cset x21, eq G_M000_IG03: uxtb w22, w21 cbnz w22, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] mov x1, x19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 tbz w0, #31, G_M000_IG05 mov w0, wzr G_M000_IG04: ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 cmp x19, x0 bne G_M000_IG09 G_M000_IG06: ldrsb wzr, [x20] mov x0, x20 bl System.RuntimeTypeHandle:GetAttributes(System.RuntimeType):int tbz w0, #13, G_M000_IG08 mov w0, #1 G_M000_IG07: ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG08: cbnz w22, G_M000_IG10 G_M000_IG09: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 cmp x19, x0 bne G_M000_IG12 G_M000_IG10: ldrsb wzr, [x20] mov x0, x20 bl System.RuntimeTypeHandle:GetAttributes(System.RuntimeType):int tbz w0, #12, G_M000_IG12 mov w0, #1 G_M000_IG11: ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG12: mov w0, wzr G_M000_IG13: ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG14: mov w21, #1 b G_M000_IG03 ; Total bytes of code 280 1064: JIT compiled System.Reflection.PseudoCustomAttribute:IsDefined(System.RuntimeType,System.RuntimeType) [Tier1 with Static PGO, IL size=132, code size=280] ; Assembly listing for method System.Collections.Generic.HashSet`1[System.__Canon]:FindItemIndex(System.__Canon):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 268571 ; 0 inlinees with PGO data; 2 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x60]! stp x19, x20, [sp, #0x20] stp x21, x22, [sp, #0x30] stp x23, x24, [sp, #0x40] stp x25, x26, [sp, #0x50] mov fp, sp str x0, [fp, #0x18] mov x19, x0 mov x20, x1 G_M000_IG02: ldr x0, [x19, #0x08] cbz x0, G_M000_IG14 G_M000_IG03: ldr x21, [x19, #0x10] mov w22, wzr ldr x23, [x19, #0x18] cbz x20, G_M000_IG16 G_M000_IG04: ldr x0, [x19] ldr x1, [x0, #0x30] ldr x1, [x1] ldr x11, [x1, #0x58] cbz x11, G_M000_IG05 b G_M000_IG06 G_M000_IG05: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS mov x11, x0 G_M000_IG06: mov x0, x23 mov x1, x20 ldr x2, [x11] blr x2 mov w24, w0 G_M000_IG07: ldr x0, [x19, #0x08] ldr w1, [x0, #0x08] ldr x2, [x19, #0x20] mov w3, w24 mul x2, x2, x3 lsr x2, x2, #32 add x2, x2, #1 mov w1, w1 mul x1, x2, x1 lsr x1, x1, #32 ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG17 add x0, x0, #16 ubfiz x1, x1, #2, #32 add x0, x0, x1 ldr w0, [x0] sub w25, w0, #1 b G_M000_IG13 G_M000_IG08: ldr w0, [x21, #0x08] cmp w25, w0 bhs G_M000_IG17 ubfiz x0, x25, #4, #32 add x0, x0, #16 add x26, x21, x0 ldr w0, [x26, #0x08] cmp w0, w24 bne G_M000_IG12 ldr x0, [x19] ldr x1, [x0, #0x30] ldr x1, [x1] ldr x11, [x1, #0x60] cbz x11, G_M000_IG09 b G_M000_IG10 G_M000_IG09: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_RUNTIMEHANDLE_CLASS mov x11, x0 G_M000_IG10: ldr x1, [x26] mov x0, x23 mov x2, x20 ldr x3, [x11] blr x3 cbz w0, G_M000_IG12 mov w0, w25 G_M000_IG11: ldp x25, x26, [sp, #0x50] ldp x23, x24, [sp, #0x40] ldp x21, x22, [sp, #0x30] ldp x19, x20, [sp, #0x20] ldp fp, lr, [sp], #0x60 ret lr G_M000_IG12: ldr w25, [x26, #0x0C] add w22, w22, #1 ldr w0, [x21, #0x08] cmp w0, w22 bhs G_M000_IG13 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 G_M000_IG13: tbz w25, #31, G_M000_IG08 G_M000_IG14: movn w0, #0 G_M000_IG15: ldp x25, x26, [sp, #0x50] ldp x23, x24, [sp, #0x40] ldp x21, x22, [sp, #0x30] ldp x19, x20, [sp, #0x20] ldp fp, lr, [sp], #0x60 ret lr G_M000_IG16: mov w24, wzr b G_M000_IG07 G_M000_IG17: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 424 1065: JIT compiled System.Collections.Generic.HashSet`1[System.__Canon]:FindItemIndex(System.__Canon) [Tier1 with Static PGO, IL size=260, code size=424] ; Assembly listing for method System.Collections.Generic.ObjectEqualityComparer`1[System.__Canon]:GetHashCode(System.__Canon):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; PGO data available, but IL did not match G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x1, [fp, #0x18] G_M000_IG02: add x1, fp, #24 ldr x0, [fp, #0x10] cbnz x0, G_M000_IG05 G_M000_IG03: ldr x1, [x1] str x1, [fp, #0x10] add x1, fp, #16 ldr x0, [fp, #0x10] cbnz x0, G_M000_IG05 mov w0, wzr G_M000_IG04: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG05: ldr x0, [x1] ldr x1, [x0] ldr x1, [x1, #0x40] ldr x1, [x1, #0x18] blr x1 G_M000_IG06: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 88 1066: JIT compiled System.Collections.Generic.ObjectEqualityComparer`1[System.__Canon]:GetHashCode(System.__Canon) [Tier1, IL size=49, code size=88] ; Assembly listing for method System.RuntimeType:GetHashCode():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldp fp, lr, [sp], #0x10 b System.Runtime.CompilerServices.RuntimeHelpers:GetHashCode(System.Object):int ; Total bytes of code 16 1067: JIT compiled System.RuntimeType:GetHashCode() [Tier1, IL size=7, code size=16] ; Assembly listing for method System.Reflection.CustomAttribute:IsCustomAttributeDefined(System.Reflection.RuntimeModule,int,System.RuntimeType,int,bool):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 52184 ; 1 inlinees with PGO data; 13 single block inlinees; 0 inlinees without PGO data G_M000_IG01: sub sp, sp, #0xD1FFAB1E stp fp, lr, [sp, #0x10] stp x19, x20, [sp, #0xD8] stp x21, x22, [sp, #0xE8] str x23, [sp, #0xF8] add fp, sp, #16 add x9, fp, #32 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] stp q16, q16, [x9, #0x80] movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 str x5, [fp, #0xC0] mov x19, x0 mov w20, w1 mov x21, x2 mov w23, w3 mov w22, w4 G_M000_IG02: ldrsb wzr, [x19] mov x0, x19 bl System.ModuleHandle:_GetMetadataImport(System.Reflection.RuntimeModule):long str x19, [fp, #0x60] str x0, [fp, #0x68] add x3, fp, #112 ldr x0, [fp, #0x68] mov w2, w20 mov w1, #0xD1FFAB1E bl System.Reflection.MetadataImport:_Enum(long,int,int,byref) ldr w0, [fp, #0x78] cbnz w0, G_M000_IG09 G_M000_IG03: mov w0, wzr movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #0xC0] cmp xip0, xip1 beq G_M000_IG04 bl CORINFO_HELP_FAIL_FAST G_M000_IG04: ldr x23, [sp, #0xF8] ldp x21, x22, [sp, #0xE8] ldp x19, x20, [sp, #0xD8] ldp fp, lr, [sp, #0x10] add sp, sp, #0xD1FFAB1E ret lr G_M000_IG05: add x1, fp, #124 ldr w1, [x1, w23, SXTW #2] G_M000_IG06: add x2, fp, #88 add x3, fp, #72 ldr x0, [fp, #0x68] bl System.Reflection.MetadataImport:_GetCustomAttributeProps(long,int,byref,byref) ldr w0, [fp, #0x58] add x5, fp, #32 str x5, [sp] add x5, fp, #24 str x5, [sp, #0x08] uxtb w5, w22 add x1, fp, #96 add x7, fp, #40 add x6, fp, #48 mov x2, x19 mov w3, w20 mov x4, x21 movz x8, #0xD1FFAB1E movk x8, #0xD1FFAB1E LSL #16 movk x8, #0xD1FFAB1E LSL #32 ldr x8, [x8] blr x8 cbnz w0, G_M000_IG14 G_M000_IG07: add w23, w23, #1 ldr w0, [fp, #0x78] cmp w23, w0 blt G_M000_IG10 G_M000_IG08: b G_M000_IG12 G_M000_IG09: stp xzr, xzr, [fp, #0x48] str xzr, [fp, #0x58] cbz x21, G_M000_IG16 stp xzr, xzr, [fp, #0x30] str xzr, [fp, #0x40] mov w23, wzr ldr w2, [fp, #0x78] cmp w2, #0 ble G_M000_IG12 G_M000_IG10: ldr x2, [fp, #0x70] cbz x2, G_M000_IG05 G_M000_IG11: ldr x2, [fp, #0x70] ldr w3, [x2, #0x08] cmp w23, w3 bhs G_M000_IG21 add x2, x2, #16 ldr w1, [x2, w23, UXTW #2] b G_M000_IG06 G_M000_IG12: mov w0, wzr movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #0xC0] cmp xip0, xip1 beq G_M000_IG13 bl CORINFO_HELP_FAIL_FAST G_M000_IG13: ldr x23, [sp, #0xF8] ldp x21, x22, [sp, #0xE8] ldp x19, x20, [sp, #0xD8] ldp fp, lr, [sp, #0x10] add sp, sp, #0xD1FFAB1E ret lr G_M000_IG14: mov w0, #1 movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #0xC0] cmp xip0, xip1 beq G_M000_IG15 bl CORINFO_HELP_FAIL_FAST G_M000_IG15: ldr x23, [sp, #0xF8] ldp x21, x22, [sp, #0xE8] ldp x19, x20, [sp, #0xD8] ldp fp, lr, [sp, #0x10] add sp, sp, #0xD1FFAB1E ret lr G_M000_IG16: mov w19, wzr b G_M000_IG20 G_M000_IG17: add x0, fp, #112 mov w1, w19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 mov w1, w0 add x2, fp, #88 add x3, fp, #72 ldr x0, [fp, #0x68] bl System.Reflection.MetadataImport:_GetCustomAttributeProps(long,int,byref,byref) ldr w0, [fp, #0x58] cmp w0, w23 bne G_M000_IG19 mov w0, #1 movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #0xC0] cmp xip0, xip1 beq G_M000_IG18 bl CORINFO_HELP_FAIL_FAST G_M000_IG18: ldr x23, [sp, #0xF8] ldp x21, x22, [sp, #0xE8] ldp x19, x20, [sp, #0xD8] ldp fp, lr, [sp, #0x10] add sp, sp, #0xD1FFAB1E ret lr G_M000_IG19: add w19, w19, #1 G_M000_IG20: ldr w0, [fp, #0x78] cmp w19, w0 blt G_M000_IG17 b G_M000_IG12 G_M000_IG21: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 644 1068: JIT compiled System.Reflection.CustomAttribute:IsCustomAttributeDefined(System.Reflection.RuntimeModule,int,System.RuntimeType,int,bool) [Tier1 with Static PGO, IL size=216, code size=644] ; Assembly listing for method System.Enum+EnumInfo`1[uint]:.ctor(bool,uint[],System.String[]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x18] str x21, [sp, #0x28] mov fp, sp mov x20, x0 mov x19, x2 mov x21, x3 G_M000_IG02: strb w1, [x20, #0x18] add x14, x20, #8 mov x15, x19 bl CORINFO_HELP_ASSIGN_REF add x14, x20, #16 mov x15, x21 bl CORINFO_HELP_ASSIGN_REF mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG04 G_M000_IG03: cbz x19, G_M000_IG06 ldr w4, [x19, #0x08] mov x1, x19 mov x2, x21 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w3, wzr mov x5, xzr movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 G_M000_IG04: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 strb w0, [x20, #0x19] G_M000_IG05: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG06: mov w0, #75 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 brk_windows #0 ; Total bytes of code 212 1069: JIT compiled System.Enum+EnumInfo`1[uint]:.ctor(bool,uint[],System.String[]) [Tier1, IL size=55, code size=212] ; Assembly listing for method System.Enum:AreSorted[uint](uint[]):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 1 inlinees with PGO data; 0 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w1, #1 ldr w2, [x0, #0x08] cmp w2, #1 ble G_M000_IG06 add x0, x0, #16 align [4 bytes for IG03] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG03: sub w3, w1, #1 cmp w3, w2 bhs G_M000_IG10 ubfiz x3, x3, #2, #32 add x3, x0, x3 ldr w4, [x0, w1, UXTW #2] ldr w5, [x3] cmp w5, w4 blo G_M000_IG05 G_M000_IG04: ldr w3, [x3] cmp w3, w4 bhi G_M000_IG08 G_M000_IG05: add w1, w1, #1 cmp w2, w1 bgt G_M000_IG03 G_M000_IG06: mov w0, #1 G_M000_IG07: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG08: mov w0, wzr G_M000_IG09: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG10: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 124 1070: JIT compiled System.Enum:AreSorted[uint](uint[]) [Tier1, IL size=50, code size=124] ; Assembly listing for method System.Enum:AreSequentialFromZero[uint](uint[]):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 0 single block inlinees; 3 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w1, wzr ldr w2, [x0, #0x08] cmp w2, #0 ble G_M000_IG04 add x0, x0, #16 align [4 bytes for IG03] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG03: ldr w3, [x0, w1, UXTW #2] sxtw x4, w1 cmp x3, x4 bne G_M000_IG06 add w1, w1, #1 cmp w2, w1 bgt G_M000_IG03 G_M000_IG04: mov w0, #1 G_M000_IG05: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG06: mov w0, wzr G_M000_IG07: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 84 1071: JIT compiled System.Enum:AreSequentialFromZero[uint](uint[]) [Tier1, IL size=34, code size=84] ; Assembly listing for method System.RuntimeType:InitializeCache():System.RuntimeType+RuntimeTypeCache:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 14282 ; 3 inlinees with PGO data; 13 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0xE0]! stp x19, x20, [sp, #0x90] stp x21, x22, [sp, #0xA0] stp x23, x24, [sp, #0xB0] stp x25, x26, [sp, #0xC0] stp x27, x28, [sp, #0xD0] mov fp, sp str xzr, [fp, #0x88] str xzr, [fp, #0x80] str xzr, [fp, #0x78] str xzr, [fp, #0x70] mov x19, x0 G_M000_IG02: add x0, fp, #24 mov x1, x12 bl CORINFO_HELP_INIT_PINVOKE_FRAME mov x20, x0 mov x0, sp str x0, [fp, #0x38] mov x0, fp str x0, [fp, #0x48] ldr x0, [x19, #0x10] cbnz x0, G_M000_IG10 G_M000_IG03: str x19, [fp, #0x68] str x19, [fp, #0x88] ldr x0, [fp, #0x88] cbz x0, G_M000_IG27 str x0, [fp, #0x80] add x0, fp, #128 ldr x1, [fp, #0x80] cbz x1, G_M000_IG24 G_M000_IG04: ldr x2, [x1, #0x18] G_M000_IG05: mov x1, x2 mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 str x3, [fp, #0x28] adr x3, [G_M000_IG08] str x3, [fp, #0x40] add x3, fp, #24 str x3, [x20, #0x10] strb wzr, [x20, #0x0C] G_M000_IG06: movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 G_M000_IG07: blr x3 G_M000_IG08: mov x19, x0 mov w0, #1 strb w0, [x20, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG09 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG09: ldr x0, [fp, #0x20] str x0, [x20, #0x10] mov x1, x19 ldr x19, [fp, #0x68] add x0, x19, #16 mov x2, xzr casal x2, x1, [x0] cbnz x2, G_M000_IG23 G_M000_IG10: ldr x0, [x19, #0x10] ldr x1, [x0] mov x21, x1 cbz x21, G_M000_IG12 G_M000_IG11: ldr x0, [x21] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 cmp x0, x2 bne G_M000_IG28 G_M000_IG12: cbnz x21, G_M000_IG22 G_M000_IG13: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x21, x0 str x21, [fp, #0x60] str wzr, [x21, #0x90] add x14, x21, #8 mov x15, x19 bl CORINFO_HELP_ASSIGN_REF str x19, [fp, #0x68] mov x0, x19 bl System.RuntimeTypeHandle:GetModule(System.RuntimeType):System.Reflection.RuntimeModule mov x22, x0 str x22, [fp, #0x58] ldr x3, [x22, #0x08] cbnz x3, G_M000_IG19 G_M000_IG14: str x22, [fp, #0x70] str xzr, [fp, #0x78] add x0, fp, #112 ldr x1, [fp, #0x70] ldr x1, [x1, #0x20] add x2, fp, #120 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 str x3, [fp, #0x28] adr x3, [G_M000_IG17] str x3, [fp, #0x40] add x3, fp, #24 str x3, [x20, #0x10] strb wzr, [x20, #0x0C] G_M000_IG15: movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 G_M000_IG16: blr x3 G_M000_IG17: mov w0, #1 strb w0, [x20, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG18 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG18: ldr x14, [fp, #0x20] str x14, [x20, #0x10] ldr x3, [fp, #0x78] str xzr, [fp, #0x78] ldr x22, [fp, #0x58] add x14, x22, #8 mov x15, x3 bl CORINFO_HELP_ASSIGN_REF G_M000_IG19: ldr x19, [fp, #0x68] cmp x3, x19 cset x0, eq ldr x21, [fp, #0x60] strb w0, [x21, #0x94] ldr x0, [x19, #0x10] mov x1, x21 mov x2, xzr bl System.Runtime.InteropServices.GCHandle:InternalCompareExchange(long,System.Object,System.Object):System.Object mov x1, x0 cbz x0, G_M000_IG21 G_M000_IG20: ldr x2, [x0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 cmp x2, x3 bne G_M000_IG29 G_M000_IG21: cmp x0, #0 csel x21, x21, x0, eq G_M000_IG22: b G_M000_IG25 G_M000_IG23: add x0, fp, #136 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG10 G_M000_IG24: mov x2, xzr b G_M000_IG05 G_M000_IG25: mov x0, x21 G_M000_IG26: ldp x27, x28, [sp, #0xD0] ldp x25, x26, [sp, #0xC0] ldp x23, x24, [sp, #0xB0] ldp x21, x22, [sp, #0xA0] ldp x19, x20, [sp, #0x90] ldp fp, lr, [sp], #0xE0 ret lr G_M000_IG27: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 mov x2, x0 mov x0, x19 mov x1, xzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x19 bl CORINFO_HELP_THROW G_M000_IG28: mov x0, x2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 brk_windows #0 G_M000_IG29: mov x0, x3 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 brk_windows #0 ; Total bytes of code 796 1072: JIT compiled System.RuntimeType:InitializeCache() [Tier1 with Static PGO, IL size=121, code size=796] ; Assembly listing for method System.RuntimeType+RuntimeTypeCache:.ctor(System.RuntimeType):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 1 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x18] str x21, [sp, #0x28] mov fp, sp mov x19, x0 mov x20, x1 G_M000_IG02: str wzr, [x19, #0x90] add x14, x19, #8 mov x15, x20 bl CORINFO_HELP_ASSIGN_REF mov x0, x20 bl System.RuntimeTypeHandle:GetModule(System.RuntimeType):System.Reflection.RuntimeModule mov x21, x0 ldr x1, [x21, #0x08] cbnz x1, G_M000_IG04 G_M000_IG03: mov x0, x21 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x1, x0 add x14, x21, #8 mov x15, x1 bl CORINFO_HELP_ASSIGN_REF G_M000_IG04: cmp x1, x20 cset x0, eq strb w0, [x19, #0x94] G_M000_IG05: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 128 1073: JIT compiled System.RuntimeType+RuntimeTypeCache:.ctor(System.RuntimeType) [Tier1, IL size=44, code size=128] ; Assembly listing for method System.Reflection.RuntimeModule:get_RuntimeType():System.RuntimeType:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 14279 ; 0 inlinees with PGO data; 5 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0xC0]! stp x19, x20, [sp, #0x70] stp x21, x22, [sp, #0x80] stp x23, x24, [sp, #0x90] stp x25, x26, [sp, #0xA0] stp x27, x28, [sp, #0xB0] mov fp, sp str xzr, [fp, #0x68] str xzr, [fp, #0x60] mov x19, x0 G_M000_IG02: add x0, fp, #24 mov x1, x12 bl CORINFO_HELP_INIT_PINVOKE_FRAME mov x20, x0 mov x0, sp str x0, [fp, #0x38] mov x0, fp str x0, [fp, #0x48] ldr x0, [x19, #0x08] cbnz x0, G_M000_IG08 G_M000_IG03: str x19, [fp, #0x58] str x19, [fp, #0x60] str xzr, [fp, #0x68] add x0, fp, #96 ldr x1, [fp, #0x60] ldr x1, [x1, #0x20] add x2, fp, #104 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 str x3, [fp, #0x28] adr x3, [G_M000_IG06] str x3, [fp, #0x40] add x3, fp, #24 str x3, [x20, #0x10] strb wzr, [x20, #0x0C] G_M000_IG04: movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 G_M000_IG05: blr x3 G_M000_IG06: mov w0, #1 strb w0, [x20, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG07 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG07: ldr x14, [fp, #0x20] str x14, [x20, #0x10] ldr x0, [fp, #0x68] str xzr, [fp, #0x68] ldr x19, [fp, #0x58] add x14, x19, #8 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG08: ldp x27, x28, [sp, #0xB0] ldp x25, x26, [sp, #0xA0] ldp x23, x24, [sp, #0x90] ldp x21, x22, [sp, #0x80] ldp x19, x20, [sp, #0x70] ldp fp, lr, [sp], #0xC0 ret lr ; Total bytes of code 256 1074: JIT compiled System.Reflection.RuntimeModule:get_RuntimeType() [Tier1 with Static PGO, IL size=26, code size=256] ; Assembly listing for method System.ModuleHandle:GetModuleType(System.Reflection.RuntimeModule):System.RuntimeType ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 4 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0xC0]! stp x19, x20, [sp, #0x70] stp x21, x22, [sp, #0x80] stp x23, x24, [sp, #0x90] stp x25, x26, [sp, #0xA0] stp x27, x28, [sp, #0xB0] mov fp, sp str xzr, [fp, #0x60] str x0, [fp, #0x68] G_M000_IG02: add x0, fp, #32 mov x1, x12 bl CORINFO_HELP_INIT_PINVOKE_FRAME mov x19, x0 mov x0, sp str x0, [fp, #0x40] mov x0, fp str x0, [fp, #0x50] add x0, fp, #104 ldr x1, [fp, #0x68] ldr x1, [x1, #0x20] add x2, fp, #96 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 str x3, [fp, #0x30] adr x3, [G_M000_IG05] str x3, [fp, #0x48] add x3, fp, #32 str x3, [x19, #0x10] strb wzr, [x19, #0x0C] G_M000_IG03: movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 G_M000_IG04: blr x3 G_M000_IG05: mov w0, #1 strb w0, [x19, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG06 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG06: ldr x0, [fp, #0x28] str x0, [x19, #0x10] ldr x0, [fp, #0x60] G_M000_IG07: ldp x27, x28, [sp, #0xB0] ldp x25, x26, [sp, #0xA0] ldp x23, x24, [sp, #0x90] ldp x21, x22, [sp, #0x80] ldp x19, x20, [sp, #0x70] ldp fp, lr, [sp], #0xC0 ret lr ; Total bytes of code 212 1075: JIT compiled System.ModuleHandle:GetModuleType(System.Reflection.RuntimeModule) [Tier1, IL size=23, code size=212] ; Assembly listing for method System.SpanHelpers:Fill[ushort](byref,ulong,ushort) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 68 ; 1 inlinees with PGO data; 5 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: cmp x1, #8 bhs G_M000_IG09 G_M000_IG03: mov x3, xzr cmp x1, #8 blo G_M000_IG05 and x4, x1, #-8 G_M000_IG04: lsl x5, x3, #1 strh w2, [x0, x5] lsl x5, x3, #1 add x5, x5, #2 strh w2, [x0, x5] lsl x5, x3, #1 add x5, x5, #4 strh w2, [x0, x5] lsl x5, x3, #1 add x5, x5, #6 strh w2, [x0, x5] lsl x5, x3, #1 add x5, x5, #8 strh w2, [x0, x5] lsl x5, x3, #1 add x5, x5, #10 strh w2, [x0, x5] lsl x5, x3, #1 add x5, x5, #12 strh w2, [x0, x5] lsl x5, x3, #1 add x5, x5, #14 strh w2, [x0, x5] add x3, x3, #8 cmp x3, x4 blo G_M000_IG04 G_M000_IG05: tbz w1, #2, G_M000_IG06 lsl x4, x3, #1 strh w2, [x0, x4] lsl x4, x3, #1 add x4, x4, #2 strh w2, [x0, x4] lsl x4, x3, #1 add x4, x4, #4 strh w2, [x0, x4] lsl x4, x3, #1 add x4, x4, #6 strh w2, [x0, x4] add x3, x3, #4 G_M000_IG06: tbz w1, #1, G_M000_IG07 lsl x4, x3, #1 strh w2, [x0, x4] lsl x4, x3, #1 add x4, x4, #2 strh w2, [x0, x4] add x3, x3, #2 G_M000_IG07: tbz w1, #0, G_M000_IG08 lsl x1, x3, #1 strh w2, [x0, x1] G_M000_IG08: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG09: uxth w2, w2 dup v16.8h, w2 lsl x2, x1, #1 and x3, x2, #-32 mov x4, xzr cmp x1, #16 blo G_M000_IG11 G_M000_IG10: str q16, [x0, x4] add x1, x4, #16 str q16, [x0, x1] add x4, x4, #32 cmp x4, x3 blo G_M000_IG10 G_M000_IG11: tbz w2, #4, G_M000_IG12 str q16, [x0, x4] G_M000_IG12: sub x1, x2, #16 str q16, [x0, x1] G_M000_IG13: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 312 1076: JIT compiled System.SpanHelpers:Fill[ushort](byref,ulong,ushort) [Tier1 with Static PGO, IL size=865, code size=312] ; Assembly listing for method System.Text.StringBuilder:AppendWithExpansion(byref,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 54089 ; 6 inlinees with PGO data; 7 single block inlinees; 2 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x40]! stp x19, x20, [sp, #0x10] stp x21, x22, [sp, #0x20] stp x23, x24, [sp, #0x30] mov fp, sp mov x19, x0 mov x20, x1 mov w21, w2 G_M000_IG02: ldp w3, w2, [x19, #0x18] add w2, w2, w3 add w2, w2, w21 ldr w0, [x19, #0x20] cmp w2, w0 bgt G_M000_IG08 cmp w2, w21 blt G_M000_IG08 ldr x2, [x19, #0x08] ldr w0, [x2, #0x08] sub w22, w0, w3 cmp w22, #0 ble G_M000_IG05 G_M000_IG03: cbz x2, G_M000_IG09 ldr w0, [x2, #0x08] cmp w0, w3 blo G_M000_IG10 add x2, x2, #16 ubfiz x1, x3, #1, #32 add x4, x2, x1 sub w5, w0, w3 mov x0, x4 G_M000_IG04: cmp w22, w5 bhi G_M000_IG12 mov w2, w22 lsl x2, x2, #1 mov x1, x20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [x19, #0x08] ldr w0, [x0, #0x08] str w0, [x19, #0x18] G_M000_IG05: sub w23, w21, w22 mov x0, x19 mov w1, w23 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 sbfiz x2, x22, #1, #32 add x1, x20, x2 ldr x2, [x19, #0x08] cbz x2, G_M000_IG11 add x0, x2, #16 ldr w24, [x2, #0x08] cmp w23, w24 bhi G_M000_IG12 G_M000_IG06: mov w2, w23 lsl x2, x2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str w23, [x19, #0x18] G_M000_IG07: ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG08: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov x20, x0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 mov x2, x0 mov x1, x20 mov x0, x19 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x19 bl CORINFO_HELP_THROW G_M000_IG09: cbnz w3, G_M000_IG10 mov x0, xzr mov w5, wzr b G_M000_IG04 G_M000_IG10: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 G_M000_IG11: mov x0, xzr mov w24, wzr cmp w23, w24 bls G_M000_IG06 G_M000_IG12: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 ; Total bytes of code 476 1077: JIT compiled System.Text.StringBuilder:AppendWithExpansion(byref,int) [Tier1 with Static PGO, IL size=155, code size=476] ; Assembly listing for method System.Text.StringBuilder:ExpandByABlock(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 68949 ; 4 inlinees with PGO data; 8 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! stp x19, x20, [sp, #0x10] mov fp, sp mov x19, x0 G_M000_IG02: ldr w0, [x19, #0x1C] add w2, w1, w0 ldr w3, [x19, #0x18] add w2, w2, w3 ldr w4, [x19, #0x20] cmp w2, w4 bgt G_M000_IG06 cmp w2, w1 blt G_M000_IG06 add w0, w0, w3 mov w2, w0 mov w3, #0xD1FFAB1E mov w4, #0xD1FFAB1E cmp w2, w3 csel w2, w2, w4, le cmp w1, w2 csel w1, w1, w2, ge add w0, w0, w1 cmp w0, w1 blt G_M000_IG07 cmp w1, #0xD1FFAB1E blt G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] mov w2, #16 bl System.GC:AllocateNewArray(long,int,int):System.Array mov x20, x0 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST ldr w14, [x19, #0x18] str w14, [x0, #0x18] ldr w14, [x19, #0x1C] str w14, [x0, #0x1C] ldr x15, [x19, #0x08] add x14, x0, #8 bl CORINFO_HELP_ASSIGN_REF ldr x15, [x19, #0x10] add x14, x0, #16 bl CORINFO_HELP_ASSIGN_REF ldr w14, [x19, #0x20] str w14, [x0, #0x20] add x14, x19, #16 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF ldp w15, w14, [x19, #0x18] add w14, w14, w15 stp wzr, w14, [x19, #0x18] add x14, x19, #8 mov x15, x20 bl CORINFO_HELP_ASSIGN_REF G_M000_IG04: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG05: sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC mov x20, x0 b G_M000_IG03 G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov x20, x0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 mov x2, x0 mov x1, x20 mov x0, x19 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x19 bl CORINFO_HELP_THROW G_M000_IG07: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x0, x19 bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 432 1078: JIT compiled System.Text.StringBuilder:ExpandByABlock(int) [Tier1 with Static PGO, IL size=144, code size=432] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:get_Operations():long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr x0, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1079: JIT compiled BenchmarkDotNet.Reports.Measurement:get_Operations() [Tier1, IL size=7, code size=20] ; Assembly listing for method System.String:PadLeft(int,ushort):System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; PGO data available, but IL did not match ; 1 inlinees with PGO data; 3 single block inlinees; 3 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x40]! stp x19, x20, [sp, #0x10] stp x21, x22, [sp, #0x20] stp x23, x24, [sp, #0x30] mov fp, sp mov x20, x0 mov w19, w1 mov w21, w2 G_M000_IG02: tbnz w19, #31, G_M000_IG07 ldr w22, [x20, #0x08] sub w23, w19, w22 cmp w23, #0 bgt G_M000_IG05 G_M000_IG03: mov x0, x20 G_M000_IG04: ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG05: mov w0, w19 bl System.String:FastAllocateString(int):System.String mov x19, x0 ldrsb wzr, [x19] add x24, x19, #12 mov x0, x24 uxth w2, w21 mov w1, w23 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 sbfiz x2, x23, #1, #32 add x0, x24, x2 add x1, x20, #12 sxtw x2, w22 lsl x2, x2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x19 G_M000_IG06: ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG07: mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov w1, w19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 brk_windows #0 ; Total bytes of code 240 1080: JIT compiled System.String:PadLeft(int,ushort) [Tier1, IL size=83, code size=240] ; Assembly listing for method System.Double:ToString(System.String,System.IFormatProvider):System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 1 inlinees with PGO data; 0 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! str d8, [sp, #0x20] str x19, [sp, #0x28] mov fp, sp mov x19, x1 G_M000_IG02: ldr d8, [x0] cbz x2, G_M000_IG04 G_M000_IG03: mov x0, x2 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] b G_M000_IG05 G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x18] G_M000_IG05: fmov d0, d8 mov x0, x19 ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] G_M000_IG06: ldr x19, [sp, #0x28] ldr d8, [sp, #0x20] ldp fp, lr, [sp], #0x30 br x2 ; Total bytes of code 128 1081: JIT compiled System.Double:ToString(System.String,System.IFormatProvider) [Tier1, IL size=15, code size=128] ; Assembly listing for method System.Globalization.NumberFormatInfo:g__GetProviderNonNull|58_0(System.IFormatProvider):System.Globalization.NumberFormatInfo ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! str x19, [sp, #0x18] mov fp, sp mov x19, x0 G_M000_IG02: mov x1, x19 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz x0, G_M000_IG07 G_M000_IG03: ldrb w1, [x0, #0x61] cbnz w1, G_M000_IG07 ldr x1, [x0, #0x18] cbnz x1, G_M000_IG05 ldr x1, [x0] ldr x1, [x1, #0x50] ldr x1, [x1, #0x10] G_M000_IG04: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 br x1 G_M000_IG05: mov x0, x1 G_M000_IG06: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG07: mov x0, x19 cbz x0, G_M000_IG09 G_M000_IG08: ldr x11, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 cmp x11, x1 csel x0, x0, xzr, eq G_M000_IG09: cbnz x0, G_M000_IG13 mov x0, x19 movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 cbz x0, G_M000_IG11 G_M000_IG10: ldr x1, [x0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 cmp x1, x2 csel x0, x0, xzr, eq G_M000_IG11: cbnz x0, G_M000_IG13 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] G_M000_IG12: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 br x0 G_M000_IG13: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 256 1082: JIT compiled System.Globalization.NumberFormatInfo:g__GetProviderNonNull|58_0(System.IFormatProvider) [Tier1, IL size=76, code size=256] ; Assembly listing for method System.Number:FormatDouble(double,System.String,System.Globalization.NumberFormatInfo):System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; PGO data available, but IL did not match ; 3 inlinees with PGO data; 9 single block inlinees; 1 inlinees without PGO data G_M000_IG01: sub sp, sp, #80 str x19, [sp, #0x38] stp fp, lr, [sp, #0x40] add fp, sp, #64 sub x9, fp, #56 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 str x2, [fp, #-0x40] mov x3, x1 G_M000_IG02: ldr wzr, [sp], #-0x40 mov x1, sp str x1, [fp, #-0x18] mov w1, #32 str w1, [fp, #-0x10] str xzr, [fp, #-0x28] str wzr, [fp, #-0x20] cbz x0, G_M000_IG10 G_M000_IG03: add x1, x0, #12 ldr w2, [x0, #0x08] G_M000_IG04: sub x0, fp, #40 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 mov x19, x0 cbnz x19, G_M000_IG06 G_M000_IG05: ldr w0, [fp, #-0x20] ldr w1, [fp, #-0x10] cmp w0, w1 bhi G_M000_IG11 ldr x1, [fp, #-0x18] str x1, [fp, #-0x38] str w0, [fp, #-0x30] sub x0, fp, #56 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x19, x0 G_M000_IG06: ldr x1, [fp, #-0x28] cbz x1, G_M000_IG08 G_M000_IG07: str xzr, [fp, #-0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] mov w2, wzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG08: mov x0, x19 movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #-0x40] cmp xip0, xip1 beq G_M000_IG09 bl CORINFO_HELP_FAIL_FAST G_M000_IG09: sub sp, fp, #64 ldp fp, lr, [sp, #0x40] ldr x19, [sp, #0x38] add sp, sp, #80 ret lr G_M000_IG10: mov x1, xzr mov w2, wzr b G_M000_IG04 G_M000_IG11: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 ; Total bytes of code 320 1083: JIT compiled System.Number:FormatDouble(double,System.String,System.Globalization.NumberFormatInfo) [Tier1, IL size=71, code size=320] ; Assembly listing for method System.Number:FormatDouble[ushort](byref,double,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo):System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 2 inlinees with PGO data; 10 single block inlinees; 0 inlinees without PGO data G_M000_IG01: sub sp, sp, #128 str d8, [sp, #0x38] stp x19, x20, [sp, #0x40] stp x21, x22, [sp, #0x50] stp x23, x24, [sp, #0x60] stp fp, lr, [sp, #0x70] add fp, sp, #112 str xzr, [fp, #-0x50] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 str x4, [fp, #-0x70] mov x20, x0 mov x21, x1 mov w22, w2 mov x19, x3 fmov d8, d0 G_M000_IG02: mov x0, v8.d[0] and x0, x0, #0xD1FFAB1E mov x1, #0xD1FFAB1E cmp x0, x1 blt G_M000_IG09 G_M000_IG03: fcmp d8, d8 beq G_M000_IG05 ldr x0, [x19, #0x58] movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #-0x70] cmp xip0, xip1 beq G_M000_IG04 bl CORINFO_HELP_FAIL_FAST G_M000_IG04: sub sp, fp, #112 ldp fp, lr, [sp, #0x70] ldp x23, x24, [sp, #0x60] ldp x21, x22, [sp, #0x50] ldp x19, x20, [sp, #0x40] ldr d8, [sp, #0x38] add sp, sp, #128 ret lr G_M000_IG05: mov x0, v8.d[0] tbnz x0, #63, G_M000_IG07 ldr x0, [x19, #0x60] movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #-0x70] cmp xip0, xip1 beq G_M000_IG06 bl CORINFO_HELP_FAIL_FAST G_M000_IG06: sub sp, fp, #112 ldp fp, lr, [sp, #0x70] ldp x23, x24, [sp, #0x60] ldp x21, x22, [sp, #0x50] ldp x19, x20, [sp, #0x40] ldr d8, [sp, #0x38] add sp, sp, #128 ret lr G_M000_IG07: ldr x0, [x19, #0x68] movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #-0x70] cmp xip0, xip1 beq G_M000_IG08 bl CORINFO_HELP_FAIL_FAST G_M000_IG08: sub sp, fp, #112 ldp fp, lr, [sp, #0x70] ldp x23, x24, [sp, #0x60] ldp x21, x22, [sp, #0x50] ldp x19, x20, [sp, #0x40] ldr d8, [sp, #0x38] add sp, sp, #128 ret lr G_M000_IG09: mov x0, x21 mov w1, w22 sub x2, fp, #64 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov w23, w0 ldr wzr, [sp] sub sp, sp, #0xD1FFAB1E mov x3, sp ldr w1, [fp, #-0x40] mov w0, #15 cmp w23, #0 csel w1, w1, w0, ne str w1, [fp, #-0x40] str wzr, [fp, #-0x60] str wzr, [fp, #-0x5C] strb wzr, [fp, #-0x58] strb wzr, [fp, #-0x57] mov w1, #3 strb w1, [fp, #-0x56] str x3, [fp, #-0x50] mov w3, #0xD1FFAB1E str w3, [fp, #-0x48] ldr w3, [fp, #-0x48] cmp w3, #0 bls G_M000_IG16 ldr x3, [fp, #-0x50] strb wzr, [x3] mov x3, v8.d[0] lsr x3, x3, #63 strb w3, [fp, #-0x58] sub x3, fp, #104 sub x1, fp, #64 mov w0, w23 mov x2, x19 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 mov w24, w0 fcmp d8, #0.0 beq G_M000_IG11 ldrb w1, [fp, #-0x68] cbz w1, G_M000_IG10 sub x1, fp, #96 fmov d0, d8 ldr w0, [fp, #-0x40] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG11 G_M000_IG10: ldrb w1, [fp, #-0x68] sub x2, fp, #96 fmov d0, d8 ldr w0, [fp, #-0x40] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG11: cbz w23, G_M000_IG13 ldr w1, [fp, #-0x40] cmn w1, #1 bne G_M000_IG12 ldr w1, [fp, #-0x60] mov w0, #17 cmp w1, #17 csel w24, w1, w0, ge G_M000_IG12: sub x1, fp, #96 mov x0, x20 mov w2, w23 mov w3, w24 mov x4, x19 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 b G_M000_IG14 G_M000_IG13: mov x2, x21 mov w3, w22 sub x1, fp, #96 mov x0, x20 mov x4, x19 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 G_M000_IG14: mov x0, xzr movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #-0x70] cmp xip0, xip1 beq G_M000_IG15 bl CORINFO_HELP_FAIL_FAST G_M000_IG15: sub sp, fp, #112 ldp fp, lr, [sp, #0x70] ldp x23, x24, [sp, #0x60] ldp x21, x22, [sp, #0x50] ldp x19, x20, [sp, #0x40] ldr d8, [sp, #0x38] add sp, sp, #128 ret lr G_M000_IG16: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 748 1084: JIT compiled System.Number:FormatDouble[ushort](byref,double,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo) [Tier1, IL size=296, code size=748] ; Assembly listing for method System.Number:ParseFormatSpecifier(System.ReadOnlySpan`1[ushort],byref):ushort ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 3 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w3, wzr cmp w1, #0 ble G_M000_IG11 G_M000_IG03: ldrh w3, [x0] orr w4, w3, #32 sub w4, w4, #97 cmp w4, #25 bhi G_M000_IG11 cmp w1, #1 bne G_M000_IG04 movn w1, #0 str w1, [x2] b G_M000_IG15 G_M000_IG04: cmp w1, #2 bne G_M000_IG05 ldrh w4, [x0, #0x02] sub w4, w4, #48 cmp w4, #10 bhs G_M000_IG06 str w4, [x2] b G_M000_IG15 G_M000_IG05: cmp w1, #3 bne G_M000_IG06 ldrh w4, [x0, #0x02] sub w4, w4, #48 ldrh w5, [x0, #0x04] sub w5, w5, #48 cmp w4, #10 ccmp w5, #10, c, lo bhs G_M000_IG06 mov w1, #10 madd w0, w4, w1, w5 str w0, [x2] b G_M000_IG15 G_M000_IG06: mov w4, wzr mov w5, #1 b G_M000_IG08 G_M000_IG07: movz w7, #0xD1FFAB1E movk w7, #0xD1FFAB1E LSL #16 cmp w4, w7 bge G_M000_IG17 add w5, w5, #1 mov w7, #10 madd w4, w4, w7, w6 sub w4, w4, #48 G_M000_IG08: cmp w5, w1 bhs G_M000_IG09 ldrh w6, [x0, w5, UXTW #2] sub w7, w6, #48 cmp w7, #9 bls G_M000_IG07 G_M000_IG09: cmp w5, w1 bhs G_M000_IG10 ldrh w6, [x0, w5, UXTW #2] cbnz w6, G_M000_IG11 G_M000_IG10: str w4, [x2] b G_M000_IG15 G_M000_IG11: movn w0, #0 str w0, [x2] cbz w1, G_M000_IG13 cbz w3, G_M000_IG13 mov w0, wzr G_M000_IG12: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG13: mov w0, #71 G_M000_IG14: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG15: uxth w0, w3 G_M000_IG16: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG17: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 ; Total bytes of code 312 1085: JIT compiled System.Number:ParseFormatSpecifier(System.ReadOnlySpan`1[ushort],byref) [Tier1, IL size=259, code size=312] ; Assembly listing for method System.Number:GetFloatingPointMaxDigitsAndPrecision(ushort,byref,System.Globalization.NumberFormatInfo,byref):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; PGO data available, but IL did not match ; 0 inlinees with PGO data; 3 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: uxth w4, w0 cbnz w4, G_M000_IG05 G_M000_IG03: mov w0, #1 strb w0, [x3] ldr w0, [x1] G_M000_IG04: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG05: ldr w5, [x1] mov w0, w5 cmp w4, #82 bhi G_M000_IG07 sub w6, w4, #67 cmp w6, #4 bhi G_M000_IG06 mov w7, w6 adr x8, [@RWD00] ldr w8, [x8, x7, LSL #2] adr x4, [G_M000_IG02] add x8, x8, x4 br x8 G_M000_IG06: sub w7, w4, #78 cmp w7, #4 bhi G_M000_IG20 mov w4, w7 adr x6, [@RWD20] ldr w6, [x6, x4, LSL #2] adr x7, [G_M000_IG02] add x6, x6, x7 br x6 G_M000_IG07: sub w8, w4, #99 cmp w8, #4 bhi G_M000_IG08 mov w4, w8 adr x6, [@RWD40] ldr w6, [x6, x4, LSL #2] adr x7, [G_M000_IG02] add x6, x6, x7 br x6 G_M000_IG08: sub w4, w4, #110 cmp w4, #4 bhi G_M000_IG20 mov w4, w4 adr x6, [@RWD60] ldr w6, [x6, x4, LSL #2] adr x7, [G_M000_IG02] add x6, x6, x7 br x6 G_M000_IG09: cmn w5, #1 bne G_M000_IG10 ldr w5, [x2, #0xD1FFAB1E] str w5, [x1] G_M000_IG10: strb wzr, [x3] b G_M000_IG19 G_M000_IG11: cmn w5, #1 bne G_M000_IG12 mov w5, #6 str w5, [x1] G_M000_IG12: ldr w2, [x1] add w2, w2, #1 str w2, [x1] b G_M000_IG16 G_M000_IG13: cmn w5, #1 bne G_M000_IG10 ldr w2, [x2, #0xD1FFAB1E] str w2, [x1] b G_M000_IG10 G_M000_IG14: cbnz w5, G_M000_IG16 G_M000_IG15: movn w5, #0 str w5, [x1] G_M000_IG16: mov w1, #1 strb w1, [x3] b G_M000_IG19 G_M000_IG17: cmn w5, #1 bne G_M000_IG18 ldr w5, [x2, #0xD1FFAB1E] str w5, [x1] G_M000_IG18: ldr w2, [x1] add w2, w2, #2 str w2, [x1] b G_M000_IG10 G_M000_IG19: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG20: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 RWD00 dd G_M000_IG09 - G_M000_IG02 dd G_M000_IG20 - G_M000_IG02 dd G_M000_IG11 - G_M000_IG02 dd G_M000_IG13 - G_M000_IG02 dd G_M000_IG14 - G_M000_IG02 RWD20 dd G_M000_IG13 - G_M000_IG02 dd G_M000_IG20 - G_M000_IG02 dd G_M000_IG17 - G_M000_IG02 dd G_M000_IG20 - G_M000_IG02 dd G_M000_IG15 - G_M000_IG02 RWD40 dd G_M000_IG09 - G_M000_IG02 dd G_M000_IG20 - G_M000_IG02 dd G_M000_IG11 - G_M000_IG02 dd G_M000_IG13 - G_M000_IG02 dd G_M000_IG14 - G_M000_IG02 RWD60 dd G_M000_IG13 - G_M000_IG02 dd G_M000_IG20 - G_M000_IG02 dd G_M000_IG17 - G_M000_IG02 dd G_M000_IG20 - G_M000_IG02 dd G_M000_IG15 - G_M000_IG02 ; Total bytes of code 360 1086: JIT compiled System.Number:GetFloatingPointMaxDigitsAndPrecision(ushort,byref,System.Globalization.NumberFormatInfo,byref) [Tier1, IL size=248, code size=360] ; Assembly listing for method System.Number:RoundNumber(byref,int,bool) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 178 ; 0 inlinees with PGO data; 2 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr x3, [x0, #0x10] mov w4, wzr b G_M000_IG04 align [4 bytes for IG03] align [4 bytes] align [4 bytes] align [0 bytes] G_M000_IG03: add w4, w4, #1 G_M000_IG04: cmp w4, w1 bge G_M000_IG06 G_M000_IG05: ldrb w5, [x3, w4, SXTW #2] cbnz w5, G_M000_IG03 G_M000_IG06: cmp w4, w1 bne G_M000_IG08 G_M000_IG07: ldrb w1, [x3, w4, SXTW #2] cmp w1, #0 cset x5, eq uxtb w2, w2 orr w2, w5, w2 cbnz w2, G_M000_IG08 cmp w1, #53 bge G_M000_IG17 G_M000_IG08: cmp w4, #0 ble G_M000_IG10 G_M000_IG09: sub w1, w4, #1 ldrb w1, [x3, w1, SXTW #2] cmp w1, #48 beq G_M000_IG13 G_M000_IG10: cbz w4, G_M000_IG14 G_M000_IG11: strb wzr, [x3, w4, SXTW #2] str w4, [x0] G_M000_IG12: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG13: sub w4, w4, #1 b G_M000_IG08 G_M000_IG14: ldrb w1, [x0, #0x0A] cmp w1, #3 bne G_M000_IG20 G_M000_IG15: str wzr, [x0, #0x04] b G_M000_IG11 G_M000_IG16: sub w4, w4, #1 G_M000_IG17: cmp w4, #0 ble G_M000_IG18 sub w1, w4, #1 ldrb w1, [x3, w1, SXTW #2] cmp w1, #57 beq G_M000_IG16 G_M000_IG18: cmp w4, #0 ble G_M000_IG19 sub w1, w4, #1 add x1, x3, w1, SXTW ldrb w2, [x1] add w2, w2, #1 strb w2, [x1] b G_M000_IG10 G_M000_IG19: add x4, x0, #4 ldr w1, [x4] add w1, w1, #1 str w1, [x4] mov w1, #49 strb w1, [x3] mov w4, #1 b G_M000_IG10 G_M000_IG20: strb wzr, [x0, #0x08] b G_M000_IG15 ; Total bytes of code 264 1087: JIT compiled System.Number:RoundNumber(byref,int,bool) [Tier1 with Static PGO, IL size=158, code size=264] ; Assembly listing for method System.String:op_Implicit(System.String):System.ReadOnlySpan`1[ushort] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 312432 ; 0 inlinees with PGO data; 2 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp G_M000_IG02: cbz x0, G_M000_IG05 G_M000_IG03: add x1, x0, #12 ldr w0, [x0, #0x08] str w0, [fp, #0x1C] mov x0, x1 ldr w1, [fp, #0x1C] G_M000_IG04: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG05: mov x0, xzr mov w1, wzr G_M000_IG06: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 1088: JIT compiled System.String:op_Implicit(System.String) [Tier1 with Static PGO, IL size=31, code size=56] ; Assembly listing for method System.Runtime.InteropServices.MemoryMarshal:Cast[ushort,ushort](System.ReadOnlySpan`1[ushort]):System.ReadOnlySpan`1[ushort] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 4 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG03: bl CORINFO_HELP_THROWDIVZERO G_M000_IG04: bl CORINFO_HELP_OVERFLOW brk_windows #0 ; Total bytes of code 28 1089: JIT compiled System.Runtime.InteropServices.MemoryMarshal:Cast[ushort,ushort](System.ReadOnlySpan`1[ushort]) [Tier1, IL size=114, code size=28] ; Assembly listing for method System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 16 1090: JIT compiled System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]) [Tier1, IL size=8, code size=16] ; Assembly listing for method System.ReadOnlySpan`1[ushort]:.ctor(byref,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: str x1, [x0] str w2, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 24 1091: JIT compiled System.ReadOnlySpan`1[ushort]:.ctor(byref,int) [Tier1, IL size=15, code size=24] ; Assembly listing for method System.ReadOnlySpan`1[ushort]:ToString():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 39002 ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp G_M000_IG02: ldr x1, [x0] ldr w0, [x0, #0x08] str w0, [fp, #0x1C] mov x0, x1 ldr w1, [fp, #0x1C] bl System.String:.ctor(System.ReadOnlySpan`1[ushort]):this G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 1092: JIT compiled System.ReadOnlySpan`1[ushort]:ToString() [Tier1 with Static PGO, IL size=144, code size=40] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:get_IterationStage():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w0, [x0, #0x04] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1093: JIT compiled BenchmarkDotNet.Reports.Measurement:get_IterationStage() [Tier1, IL size=7, code size=20] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:GcCollect():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 5 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0xB0]! stp x19, x20, [sp, #0x60] stp x21, x22, [sp, #0x70] stp x23, x24, [sp, #0x80] stp x25, x26, [sp, #0x90] stp x27, x28, [sp, #0xA0] mov fp, sp mov x19, x0 G_M000_IG02: add x0, fp, #32 mov x1, x12 bl CORINFO_HELP_INIT_PINVOKE_FRAME mov x20, x0 mov x0, sp str x0, [fp, #0x40] mov x0, fp str x0, [fp, #0x50] ldrb w0, [x19, #0xB8] cbz w0, G_M000_IG16 G_M000_IG03: movn w0, #0 mov w1, #2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 str x2, [fp, #0x30] adr x2, [G_M000_IG06] str x2, [fp, #0x48] add x2, fp, #32 str x2, [x20, #0x10] strb wzr, [x20, #0x0C] G_M000_IG04: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 G_M000_IG05: blr x2 G_M000_IG06: mov w0, #1 strb w0, [x20, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG07 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG07: ldr x0, [fp, #0x28] str x0, [x20, #0x10] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x30] adr x0, [G_M000_IG10] str x0, [fp, #0x48] add x0, fp, #32 str x0, [x20, #0x10] strb wzr, [x20, #0x0C] G_M000_IG08: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG09: blr x0 G_M000_IG10: mov w0, #1 strb w0, [x20, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG11 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG11: ldr x0, [fp, #0x28] str x0, [x20, #0x10] movn w0, #0 mov w1, #2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 str x2, [fp, #0x30] adr x2, [G_M000_IG14] str x2, [fp, #0x48] add x2, fp, #32 str x2, [x20, #0x10] strb wzr, [x20, #0x0C] G_M000_IG12: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 G_M000_IG13: blr x2 G_M000_IG14: mov w0, #1 strb w0, [x20, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG15 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG15: ldr x0, [fp, #0x28] str x0, [x20, #0x10] G_M000_IG16: ldp x27, x28, [sp, #0xA0] ldp x25, x26, [sp, #0x90] ldp x23, x24, [sp, #0x80] ldp x21, x22, [sp, #0x70] ldp x19, x20, [sp, #0x60] ldp fp, lr, [sp], #0xB0 ret lr ; Total bytes of code 404 1094: JIT compiled BenchmarkDotNet.Engines.Engine:GcCollect() [Tier1, IL size=15, code size=404] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_ForceGcCleanups():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldrb w0, [x0, #0xB8] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1095: JIT compiled BenchmarkDotNet.Engines.Engine:get_ForceGcCleanups() [Tier1, IL size=7, code size=20] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:ForceGcCollect() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 3 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0xB0]! stp x19, x20, [sp, #0x60] stp x21, x22, [sp, #0x70] stp x23, x24, [sp, #0x80] stp x25, x26, [sp, #0x90] stp x27, x28, [sp, #0xA0] mov fp, sp G_M000_IG02: add x0, fp, #32 mov x1, x12 bl CORINFO_HELP_INIT_PINVOKE_FRAME mov x19, x0 mov x0, sp str x0, [fp, #0x40] mov x0, fp str x0, [fp, #0x50] movn w0, #0 mov w1, #2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 str x2, [fp, #0x30] adr x2, [G_M000_IG05] str x2, [fp, #0x48] add x2, fp, #32 str x2, [x19, #0x10] strb wzr, [x19, #0x0C] G_M000_IG03: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 G_M000_IG04: blr x2 G_M000_IG05: mov w0, #1 strb w0, [x19, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG06 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG06: ldr x0, [fp, #0x28] str x0, [x19, #0x10] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x30] adr x0, [G_M000_IG09] str x0, [fp, #0x48] add x0, fp, #32 str x0, [x19, #0x10] strb wzr, [x19, #0x0C] G_M000_IG07: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG08: blr x0 G_M000_IG09: mov w0, #1 strb w0, [x19, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG10 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG10: ldr x0, [fp, #0x28] str x0, [x19, #0x10] movn w0, #0 mov w1, #2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 str x2, [fp, #0x30] adr x2, [G_M000_IG13] str x2, [fp, #0x48] add x2, fp, #32 str x2, [x19, #0x10] strb wzr, [x19, #0x0C] G_M000_IG11: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 G_M000_IG12: blr x2 G_M000_IG13: mov w0, #1 strb w0, [x19, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG14 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG14: ldr x0, [fp, #0x28] str x0, [x19, #0x10] G_M000_IG15: ldp x27, x28, [sp, #0xA0] ldp x25, x26, [sp, #0x90] ldp x23, x24, [sp, #0x80] ldp x21, x22, [sp, #0x70] ldp x19, x20, [sp, #0x60] ldp fp, lr, [sp], #0xB0 ret lr ; Total bytes of code 392 1096: JIT compiled BenchmarkDotNet.Engines.Engine:ForceGcCollect() [Tier1, IL size=16, code size=392] ; Assembly listing for method System.GC:WaitForPendingFinalizers() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0xB0]! stp x19, x20, [sp, #0x60] stp x21, x22, [sp, #0x70] stp x23, x24, [sp, #0x80] stp x25, x26, [sp, #0x90] stp x27, x28, [sp, #0xA0] mov fp, sp G_M000_IG02: add x0, fp, #32 mov x1, x12 bl CORINFO_HELP_INIT_PINVOKE_FRAME mov x19, x0 mov x0, sp str x0, [fp, #0x40] mov x0, fp str x0, [fp, #0x50] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 str x0, [fp, #0x30] adr x0, [G_M000_IG05] str x0, [fp, #0x48] add x0, fp, #32 str x0, [x19, #0x10] strb wzr, [x19, #0x0C] G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG04: blr x0 G_M000_IG05: mov w0, #1 strb w0, [x19, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG06 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG06: ldr x0, [fp, #0x28] str x0, [x19, #0x10] G_M000_IG07: ldp x27, x28, [sp, #0xA0] ldp x25, x26, [sp, #0x90] ldp x23, x24, [sp, #0x80] ldp x21, x22, [sp, #0x70] ldp x19, x20, [sp, #0x60] ldp fp, lr, [sp], #0xB0 ret lr ; Total bytes of code 184 1097: JIT compiled System.GC:WaitForPendingFinalizers() [Tier1, IL size=6, code size=184] ; Assembly listing for method System.Diagnostics.Tracing.EventSource:IsEnabled():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldrb w0, [x0, #0x9D] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1098: JIT compiled System.Diagnostics.Tracing.EventSource:IsEnabled() [Tier1, IL size=7, code size=20] ; Assembly listing for method System.Diagnostics.Tracing.EventSource:WriteEvent(int,long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 5 single block inlinees; 0 inlinees without PGO data G_M000_IG01: sub sp, sp, #32 stp fp, lr, [sp, #0x10] add fp, sp, #16 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 str x3, [fp, #-0x10] str x2, [fp, #-0x08] G_M000_IG02: ldrb w4, [x0, #0x9D] cbz w4, G_M000_IG04 G_M000_IG03: ldr wzr, [sp], #-0x10 mov x4, sp sub x2, fp, #8 str x2, [x4] mov w2, #8 stp w2, wzr, [x4, #0x08] mov x2, xzr mov w3, #1 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 G_M000_IG04: movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #-0x10] cmp xip0, xip1 beq G_M000_IG05 bl CORINFO_HELP_FAIL_FAST G_M000_IG05: sub sp, fp, #16 ldp fp, lr, [sp, #0x10] add sp, sp, #32 ret lr ; Total bytes of code 136 1099: JIT compiled System.Diagnostics.Tracing.EventSource:WriteEvent(int,long) [Tier1, IL size=53, code size=136] ; Assembly listing for method Perfolizer.Horology.WindowsClock:GetTimestamp():long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: add x0, fp, #24 bl Perfolizer.Horology.WindowsClock:QueryPerformanceCounter(byref):bool ldr x0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 32 1100: JIT compiled Perfolizer.Horology.WindowsClock:GetTimestamp() [Tier1, IL size=10, code size=32] ; Assembly listing for method System.Int32:System.IBinaryIntegerParseAndFormatInfo.get_IsSigned():bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, #1 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1101: JIT compiled System.Int32:System.IBinaryIntegerParseAndFormatInfo.get_IsSigned() [Tier1, IL size=2, code size=20] ; Assembly listing for method System.Math:Round(double):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 35 ; 0 inlinees with PGO data; 2 single block inlinees; 2 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov x0, v0.d[0] lsr x1, x0, #52 and w1, w1, #0xD1FFAB1E cmp w1, #0xD1FFAB1E ble G_M000_IG04 cmp w1, #0xD1FFAB1E bge G_M000_IG11 neg w1, w1 add w1, w1, #0xD1FFAB1E mov x2, #1 lsl x1, x2, x1 sub x2, x1, #1 add x0, x0, x1, LSR #1 bic x3, x0, x2 bic x1, x0, x1 tst x0, x2 csel x0, x3, x1, ne fmov d0, x0 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG04: lsl x2, x0, #1 cbnz x2, G_M000_IG06 G_M000_IG05: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG06: cmp w1, #0xD1FFAB1E bne G_M000_IG07 tst x0, #0xD1FFAB1E bne G_M000_IG08 G_M000_IG07: movi v16.16b, #0 b G_M000_IG09 G_M000_IG08: fmov d16, #1.0000 G_M000_IG09: ldr q17, [@RWD00] bif v0.2d, v16.2d, v17.2d G_M000_IG10: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG11: ldp fp, lr, [sp], #0x10 ret lr RWD00 dq 8000000000000000h, 8000000000000000h ; Total bytes of code 156 1102: JIT compiled System.Math:Round(double) [Tier1 with Static PGO, IL size=135, code size=156] ; Assembly listing for method System.Number:Dragon4Double(double,int,bool,byref) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 4 ; 1 inlinees with PGO data; 1 single block inlinees; 1 inlinees without PGO data G_M000_IG01: sub sp, sp, #48 stp fp, lr, [sp, #0x08] str x19, [sp, #0x28] add fp, sp, #8 mov w4, w0 mov x19, x2 G_M000_IG02: mov x6, v0.d[0] and x0, x6, #0xD1FFAB1E lsr x6, x6, #52 and w8, w6, #0xD1FFAB1E cbz w8, G_M000_IG06 orr x0, x0, #0xD1FFAB1E sub w8, w8, #0xD1FFAB1E G_M000_IG03: mov w3, wzr lsr x6, x0, #52 cbz x6, G_M000_IG07 mov w2, #52 mov x3, #0xD1FFAB1E cmp x0, x3 cset x3, eq G_M000_IG04: add x6, fp, #24 str x6, [sp] ldr x6, [x19, #0x10] add x7, x19, #16 ldr x7, [x7, #0x08] uxtb w5, w1 mov w1, w8 movz x8, #0xD1FFAB1E movk x8, #0xD1FFAB1E LSL #16 movk x8, #0xD1FFAB1E LSL #32 ldr x8, [x8] blr x8 ldr w1, [fp, #0x18] add w1, w1, #1 str w1, [x19, #0x04] add x1, x19, #16 ldr w2, [x1, #0x08] cmp w0, w2 bhs G_M000_IG08 ldr x1, [x1] strb wzr, [x1, w0, UXTW #2] str w0, [x19] G_M000_IG05: ldr x19, [sp, #0x28] ldp fp, lr, [sp, #0x08] add sp, sp, #48 ret lr G_M000_IG06: movn w8, #0xD1FFAB1E b G_M000_IG03 G_M000_IG07: orr x2, x0, #1 clz x2, x2 eor w2, w2, #63 b G_M000_IG04 G_M000_IG08: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 216 1103: JIT compiled System.Number:Dragon4Double(double,int,bool,byref) [Tier1 with Static PGO, IL size=114, code size=216] ; Assembly listing for method System.Number:Dragon4(ulong,int,uint,bool,int,bool,System.Span`1[ubyte],byref):uint ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 4 ; 4 inlinees with PGO data; 9 single block inlinees; 4 inlinees without PGO data G_M000_IG01: movn x9, #0xD1FFAB1E ldr wzr, [sp, x9] stp x19, x20, [sp, #-0x50]! stp x21, x22, [sp, #0x10] stp x23, x24, [sp, #0x20] stp x25, x26, [sp, #0x30] stp x27, x28, [sp, #0x40] mov x8, #0xD1FFAB1E sub sp, sp, x8 stp fp, lr, [sp] mov fp, sp movz x8, #0xD1FFAB1E movk x8, #0xD1FFAB1E LSL #16 movk x8, #0xD1FFAB1E LSL #32 str x8, [fp, #0xD1FFAB1E] str x6, [fp, #0x18] str x7, [fp, #0x20] mov x21, x0 mov w20, w1 mov w22, w2 mov w19, w4 mov w23, w5 G_M000_IG02: ldr x24, [fp, #0xD1FFAB1E] mov w25, wzr tst w3, #255 bne G_M000_IG26 cmp w20, #0 bgt G_M000_IG29 lsl x1, x21, #1 mov x0, #0xD1FFAB1E cmp x1, x0 bls G_M000_IG30 str w1, [fp, #0xD1FFAB1E] lsr x0, x1, #32 str w0, [fp, #0xD1FFAB1E] mov w0, #2 str w0, [fp, #0xD1FFAB1E] G_M000_IG03: neg w0, w20 add w0, w0, #1 add x1, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 mov w1, #1 str w1, [fp, #0xD1FFAB1E] str w1, [fp, #0xD1FFAB1E] G_M000_IG04: add x26, fp, #0xD1FFAB1E G_M000_IG05: add w1, w22, w20 scvtf d16, w1 ldr d17, [@RWD00] fmul d16, d16, d17 ldr d17, [@RWD08] fsub d16, d16, d17 frintp d16, d16 fcvtzs w27, d16 cmp w27, #0 ble G_M000_IG31 cmp w27, #9 bhi G_M000_IG06 cmp w27, #10 bhs G_M000_IG47 ubfiz x1, x27, #2, #32 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w1, [x1, x0] add x0, fp, #0xD1FFAB1E add x2, fp, #0xD1FFAB1E movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG08 G_M000_IG06: ldr w1, [fp, #0xD1FFAB1E] cbz w1, G_M000_IG08 add x1, fp, #0xD1FFAB1E mov w0, w27 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [fp, #0xD1FFAB1E] cmp w0, #1 bgt G_M000_IG07 ldr w2, [fp, #0xD1FFAB1E] cmp w0, #0 csel w1, wzr, w2, le add x0, fp, #0xD1FFAB1E add x2, fp, #0xD1FFAB1E movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG08 G_M000_IG07: ldr w2, [fp, #0xD1FFAB1E] str w2, [fp, #0x28] sxtw x2, w2 lsl x2, x2, #2 add x1, fp, #0xD1FFAB1E add x0, fp, #44 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x0, fp, #40 add x1, fp, #0xD1FFAB1E add x2, fp, #0xD1FFAB1E movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG08: mvn w0, w21 and w28, w0, #1 cmn w19, #1 beq G_M000_IG32 G_M000_IG09: add x0, fp, #0xD1FFAB1E add x1, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 tbnz w0, #31, G_M000_IG35 G_M000_IG10: add w27, w27, #1 G_M000_IG11: ldr w22, [fp, #0x20] sub w21, w27, w22 cmn w19, #1 beq G_M000_IG12 neg w0, w19 sub w1, w27, w19 tst w23, #255 csel w0, w0, w1, eq cmp w0, w21 csel w21, w21, w0, le G_M000_IG12: sub w27, w27, #1 str w27, [x24] add x0, fp, #0xD1FFAB1E ldr w1, [fp, #0xD1FFAB1E] sub w1, w1, #1 ldr w2, [x0, w1, UXTW #2] movz w0, #0xD1FFAB1E movk w0, #0xD1FFAB1E LSL #16 cmp w2, #8 ccmp w2, w0, c, hs bhi G_M000_IG36 G_M000_IG13: cmn w19, #1 beq G_M000_IG37 G_M000_IG14: cmp w27, w21 blt G_M000_IG42 mov w23, wzr mov w19, wzr G_M000_IG15: add x0, fp, #0xD1FFAB1E add x1, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 mov w28, w0 ldr w0, [fp, #0xD1FFAB1E] cbz w0, G_M000_IG17 G_M000_IG16: cmp w27, w21 ble G_M000_IG17 cmp w25, w22 bhs G_M000_IG47 ldr x0, [fp, #0x18] add w1, w28, #48 strb w1, [x0, w25, UXTW #2] add w25, w25, #1 add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 sub w27, w27, #1 b G_M000_IG15 G_M000_IG17: cmp w23, w19 bne G_M000_IG18 add x0, fp, #0xD1FFAB1E mov w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #0xD1FFAB1E add x1, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 lsr w23, w0, #31 cbz w0, G_M000_IG46 G_M000_IG18: cbz w23, G_M000_IG19 cmp w25, w22 bhs G_M000_IG47 ldr x1, [fp, #0x18] add w0, w28, #48 strb w0, [x1, w25, UXTW #2] b G_M000_IG23 G_M000_IG19: cmp w28, #9 bne G_M000_IG22 G_M000_IG20: cbnz w25, G_M000_IG21 cmp w22, #0 bls G_M000_IG47 ldr x0, [fp, #0x18] mov w1, #49 strb w1, [x0] mov w25, #1 ldr w0, [x24] add w0, w0, #1 str w0, [x24] b G_M000_IG24 G_M000_IG21: sub w25, w25, #1 cmp w25, w22 bhs G_M000_IG47 ldr x0, [fp, #0x18] ldrb w0, [x0, w25, UXTW #2] cmp w0, #57 beq G_M000_IG20 ldr x0, [fp, #0x18] mov w1, w25 add x0, x0, x1 ldrb w1, [x0] add w1, w1, #1 strb w1, [x0] b G_M000_IG23 G_M000_IG22: cmp w25, w22 bhs G_M000_IG47 ldr x0, [fp, #0x18] add w1, w28, #49 strb w1, [x0, w25, UXTW #2] G_M000_IG23: add w25, w25, #1 G_M000_IG24: mov w0, w25 movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #0xD1FFAB1E] cmp xip0, xip1 beq G_M000_IG25 bl CORINFO_HELP_FAIL_FAST G_M000_IG25: ldp fp, lr, [sp] mov xip1, #0xD1FFAB1E add sp, sp, xip1 ldp x27, x28, [sp, #0x40] ldp x25, x26, [sp, #0x30] ldp x23, x24, [sp, #0x20] ldp x21, x22, [sp, #0x10] ldp x19, x20, [sp], #0x50 ret lr G_M000_IG26: cmp w20, #0 ble G_M000_IG27 lsl x1, x21, #2 add x0, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #0xD1FFAB1E mov w1, w20 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #0xD1FFAB1E mov w1, #4 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x1, fp, #0xD1FFAB1E mov w0, w20 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add w0, w20, #1 add x1, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG28 G_M000_IG27: lsl x1, x21, #2 add x0, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 neg w0, w20 add w0, w0, #2 add x1, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #0xD1FFAB1E mov w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #0xD1FFAB1E mov w1, #2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG28: add x26, fp, #0xD1FFAB1E b G_M000_IG05 G_M000_IG29: lsl x1, x21, #1 add x0, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #0xD1FFAB1E mov w1, w20 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #0xD1FFAB1E mov w1, #2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x1, fp, #0xD1FFAB1E mov w0, w20 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG04 G_M000_IG30: add x0, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG03 G_M000_IG31: tbz w27, #31, G_M000_IG08 neg w0, w27 add x1, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #0xD1FFAB1E add x1, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #0xD1FFAB1E add x1, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #0xD1FFAB1E cmp x26, x0 beq G_M000_IG08 add x0, fp, #0xD1FFAB1E mov x2, x26 mov w1, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mvn w0, w21 and w28, w0, #1 cmn w19, #1 bne G_M000_IG09 G_M000_IG32: add x0, fp, #0xD1FFAB1E add x2, fp, #0xD1FFAB1E mov x1, x26 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x0, fp, #0xD1FFAB1E add x1, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w28, G_M000_IG33 cmp w0, #0 cset x1, gt b G_M000_IG34 G_M000_IG33: cmp w0, #0 cset x1, ge G_M000_IG34: uxtb w0, w1 cbnz w0, G_M000_IG10 G_M000_IG35: add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 add x0, fp, #0xD1FFAB1E cmp x26, x0 beq G_M000_IG11 add x0, fp, #0xD1FFAB1E mov x2, x26 mov w1, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG11 G_M000_IG36: orr w0, w2, #1 clz w0, w0 eor w0, w0, #31 neg w0, w0 add w0, w0, #59 and w20, w0, #31 add x0, fp, #0xD1FFAB1E mov w1, w20 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #0xD1FFAB1E mov w1, w20 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #0xD1FFAB1E mov w1, w20 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #0xD1FFAB1E cmp x26, x0 beq G_M000_IG13 add x0, fp, #0xD1FFAB1E mov x2, x26 mov w1, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 cmn w19, #1 bne G_M000_IG14 G_M000_IG37: add x0, fp, #0xD1FFAB1E add x1, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 mov w19, w0 add x0, fp, #0xD1FFAB1E add x2, fp, #0xD1FFAB1E mov x1, x26 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x0, fp, #0xD1FFAB1E add x1, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 mov w20, w0 add x0, fp, #0xD1FFAB1E add x1, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w28, G_M000_IG38 cmp w20, #0 cset x23, le cmp w0, #0 cset x0, ge mov w20, w0 b G_M000_IG39 G_M000_IG38: lsr w23, w20, #31 cmp w0, #0 cset x20, gt G_M000_IG39: orr w0, w23, w20 cbnz w0, G_M000_IG41 mov w0, w19 mov w19, w20 mov w20, w28 mov w28, w0 cmp w27, w21 beq G_M000_IG17 cmp w25, w22 bhs G_M000_IG47 ldr x0, [fp, #0x18] add w1, w28, #48 strb w1, [x0, w25, UXTW #2] add w25, w25, #1 add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 add x0, fp, #0xD1FFAB1E cmp x26, x0 beq G_M000_IG40 add x0, fp, #0xD1FFAB1E mov x2, x26 mov w1, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG40: sub w27, w27, #1 mov w28, w20 b G_M000_IG37 G_M000_IG41: mov w28, w19 mov w19, w20 b G_M000_IG17 G_M000_IG42: add x0, fp, #0xD1FFAB1E add x1, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 mov w28, w0 cmp w28, #5 bhi G_M000_IG43 cmp w28, #5 bne G_M000_IG44 ldr w0, [fp, #0xD1FFAB1E] cbz w0, G_M000_IG44 G_M000_IG43: ldr w0, [x24] add w0, w0, #1 str w0, [x24] mov w28, #1 G_M000_IG44: cmp w22, #0 bls G_M000_IG47 ldr x0, [fp, #0x18] add w1, w28, #48 strb w1, [x0] mov w0, #1 movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #0xD1FFAB1E] cmp xip0, xip1 beq G_M000_IG45 bl CORINFO_HELP_FAIL_FAST G_M000_IG45: ldp fp, lr, [sp] mov xip1, #0xD1FFAB1E add sp, sp, xip1 ldp x27, x28, [sp, #0x40] ldp x25, x26, [sp, #0x30] ldp x23, x24, [sp, #0x20] ldp x21, x22, [sp, #0x10] ldp x19, x20, [sp], #0x50 ret lr G_M000_IG46: mvn w0, w28 and w23, w0, #1 b G_M000_IG18 G_M000_IG47: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 RWD00 dq 3FD34413509F79FFh ; 0.301029996 RWD08 dq 3FE6147AE147AE14h ; 0.69 ; Total bytes of code 2468 1104: JIT compiled System.Number:Dragon4(ulong,int,uint,bool,int,bool,System.Span`1[ubyte],byref) [Tier1 with Static PGO, IL size=1029, code size=2468] ; Assembly listing for method System.Number+BigInteger:Pow2(uint,byref) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 4 ; 1 inlinees with PGO data; 4 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x18] str x21, [sp, #0x28] mov fp, sp mov x19, x1 G_M000_IG02: and w20, w0, #31 lsr w21, w0, #5 add w0, w21, #1 str w0, [x19] cbz w21, G_M000_IG05 add x0, x19, #4 lsl w1, w21, #2 mov w1, w1 str x1, [fp, #0x10] cbz x1, G_M000_IG05 G_M000_IG03: cmp x1, #0xD1FFAB1E bhi G_M000_IG07 G_M000_IG04: mov w1, wzr ldr w2, [fp, #0x10] bl CORINFO_HELP_MEMSET G_M000_IG05: add x0, x19, #4 mov w1, #1 lsl w1, w1, w20 str w1, [x0, w21, UXTW #2] G_M000_IG06: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG07: ldr x1, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG05 ; Total bytes of code 140 1105: JIT compiled System.Number+BigInteger:Pow2(uint,byref) [Tier1 with Static PGO, IL size=55, code size=140] ; Assembly listing for method System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:get_Count():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w0, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1106: JIT compiled System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:get_Count() [Tier1, IL size=7, code size=20] ; Assembly listing for method System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:Add(BenchmarkDotNet.Reports.Measurement):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w2, [x0, #0x14] add w2, w2, #1 str w2, [x0, #0x14] ldr x2, [x0, #0x08] ldr w3, [x0, #0x10] ldr w4, [x2, #0x08] cmp w4, w3 bls G_M000_IG05 G_M000_IG03: add w4, w3, #1 str w4, [x0, #0x10] ubfiz x0, x3, #5, #32 add x0, x0, #16 add x0, x2, x0 ldp q16, q17, [x1] stp q16, q17, [x0] G_M000_IG04: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG05: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] G_M000_IG06: ldp fp, lr, [sp], #0x10 br x2 ; Total bytes of code 100 1107: JIT compiled System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:Add(BenchmarkDotNet.Reports.Measurement) [Tier1, IL size=60, code size=100] ; Assembly listing for method System.Math:Max(long,long):long ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 50029 G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: cmp x0, x1 csel x0, x0, x1, ge G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 24 1108: JIT compiled System.Math:Max(long,long) [Tier1 with Static PGO, IL size=8, code size=24] ; Assembly listing for method System.Int32:GetHashCode():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1109: JIT compiled System.Int32:GetHashCode() [Tier1, IL size=3, code size=20] ; Assembly listing for method System.Collections.HashHelpers:FastMod(uint,uint,ulong):uint ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, w0 mul x0, x2, x0 lsr x0, x0, #32 add x0, x0, #1 mov w1, w1 mul x0, x0, x1 lsr x0, x0, #32 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 44 1110: JIT compiled System.Collections.HashHelpers:FastMod(uint,uint,ulong) [Tier1, IL size=20, code size=44] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_Host():BenchmarkDotNet.Engines.IHost:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1111: JIT compiled BenchmarkDotNet.Engines.Engine:get_Host() [Tier1, IL size=7, code size=20] ; Assembly listing for method System.IO.StreamWriter:Flush(bool,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 607 ; 9 inlinees with PGO data; 6 single block inlinees; 0 inlinees without PGO data G_M000_IG01: sub sp, sp, #80 stp x19, x20, [sp, #0x18] stp x21, x22, [sp, #0x28] str x23, [sp, #0x38] stp fp, lr, [sp, #0x40] add fp, sp, #64 str xzr, [fp, #-0x30] str xzr, [fp, #-0x38] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 str x3, [fp, #-0x40] mov x19, x0 mov w21, w1 mov w20, w2 G_M000_IG02: ldrb w0, [x19, #0x5B] cbnz w0, G_M000_IG28 ldr w0, [x19, #0x50] uxtb w1, w21 orr w0, w0, w1 uxtb w1, w20 orr w0, w0, w1 cbz w0, G_M000_IG29 ldrb w0, [x19, #0x59] cbz w0, G_M000_IG18 G_M000_IG03: ldr x0, [x19, #0x38] cbz x0, G_M000_IG14 G_M000_IG04: add x22, x0, #16 ldr w23, [x0, #0x08] G_M000_IG05: ldr x0, [x19, #0x30] ldr x1, [x19, #0x40] ldr w2, [x19, #0x50] cbz x1, G_M000_IG31 ldr w3, [x1, #0x08] cmp w3, w2 blo G_M000_IG27 add x1, x1, #16 G_M000_IG06: ldr x3, [x0] movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 cmp x3, x5 bne G_M000_IG17 G_M000_IG07: mov x3, x22 mov w4, w23 mov x5, #1 cmp w2, #0 csel x1, x1, x5, ne str x1, [fp, #-0x30] cmp w4, #0 csel x3, x3, x5, ne str x3, [fp, #-0x38] uxtb w5, w20 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 str xzr, [fp, #-0x30] str xzr, [fp, #-0x38] G_M000_IG08: mov w2, w0 str wzr, [x19, #0x50] cmp w2, #0 ble G_M000_IG10 G_M000_IG09: ldr x0, [x19, #0x20] cmp w2, w23 bhi G_M000_IG27 mov x1, x22 ldr x3, [x0] ldr x3, [x3, #0x60] ldr x3, [x3, #0x38] blr x3 G_M000_IG10: tst w21, #255 bne G_M000_IG13 G_M000_IG11: movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #-0x40] cmp xip0, xip1 beq G_M000_IG12 bl CORINFO_HELP_FAIL_FAST G_M000_IG12: sub sp, fp, #64 ldp fp, lr, [sp, #0x40] ldr x23, [sp, #0x38] ldp x21, x22, [sp, #0x28] ldp x19, x20, [sp, #0x18] add sp, sp, #80 ret lr G_M000_IG13: ldr x0, [x19, #0x20] ldr x1, [x0] ldr x1, [x1, #0x50] ldr x1, [x1, #0x30] blr x1 b G_M000_IG11 G_M000_IG14: ldr x0, [x19, #0x28] ldr w1, [x19, #0x50] ldr x2, [x0] ldr x2, [x2, #0x68] ldr x2, [x2, #0x20] blr x2 cmp w0, #0xD1FFAB1E bgt G_M000_IG22 G_M000_IG15: ldr wzr, [sp] sub sp, sp, #0xD1FFAB1E mov x22, sp mov w23, #0xD1FFAB1E G_M000_IG16: b G_M000_IG05 G_M000_IG17: mov x3, x22 mov w4, w23 uxtb w5, w20 ldr x6, [x0] ldr x6, [x6, #0x48] ldr x6, [x6, #0x10] blr x6 b G_M000_IG08 G_M000_IG18: mov w0, #1 strb w0, [x19, #0x59] ldr x0, [x19, #0x28] ldr x22, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 cmp x22, x1 beq G_M000_IG25 G_M000_IG19: ldr x1, [x22, #0x40] ldr x1, [x1, #0x30] blr x1 mov w2, w1 G_M000_IG20: mov x1, x0 cmp w2, #0 ble G_M000_IG03 G_M000_IG21: ldr x0, [x19, #0x20] ldr x3, [x0] ldr x3, [x3, #0x60] ldr x3, [x3, #0x38] blr x3 b G_M000_IG03 G_M000_IG22: ldr x0, [x19, #0x28] ldr x1, [x19, #0x40] ldr w1, [x1, #0x08] ldr x2, [x0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 cmp x2, x3 beq G_M000_IG26 G_M000_IG23: ldr x2, [x2, #0x68] ldr x2, [x2, #0x20] blr x2 G_M000_IG24: sxtw x1, w0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC add x14, x19, #56 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF add x22, x0, #16 ldr w23, [x0, #0x08] b G_M000_IG16 G_M000_IG25: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov w2, w1 b G_M000_IG20 G_M000_IG26: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG24 G_M000_IG27: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 G_M000_IG28: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 brk_windows #0 G_M000_IG29: movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #-0x40] cmp xip0, xip1 beq G_M000_IG30 bl CORINFO_HELP_FAIL_FAST G_M000_IG30: sub sp, fp, #64 ldp fp, lr, [sp, #0x40] ldr x23, [sp, #0x38] ldp x21, x22, [sp, #0x28] ldp x19, x20, [sp, #0x18] add sp, sp, #80 ret lr G_M000_IG31: cbnz w2, G_M000_IG27 mov x1, xzr mov w2, wzr b G_M000_IG06 ; Total bytes of code 816 1112: JIT compiled System.IO.StreamWriter:Flush(bool,bool) [Tier1 with Static PGO, IL size=272, code size=816] ; Assembly listing for method System.Text.UTF8Encoding:GetMaxByteCount(int):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; PGO data available, but IL did not match ; 0 inlinees with PGO data; 3 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! stp x19, x20, [sp, #0x10] mov fp, sp mov x20, x0 mov w19, w1 G_M000_IG02: tbnz w19, #31, G_M000_IG06 sxtw x0, w19 add x19, x0, #1 ldr x0, [x20, #0x10] ldr x1, [x0] ldr x1, [x1, #0x40] ldr x1, [x1, #0x28] blr x1 cmp w0, #1 ble G_M000_IG04 G_M000_IG03: ldr x0, [x20, #0x10] ldr x1, [x0] ldr x1, [x1, #0x40] ldr x1, [x1, #0x28] blr x1 sxtw x0, w0 mul x19, x0, x19 G_M000_IG04: mov x0, #3 mul x19, x19, x0 mov x0, #0xD1FFAB1E cmp x19, x0 bgt G_M000_IG07 mov w0, w19 G_M000_IG05: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG06: movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov w1, w19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 brk_windows #0 G_M000_IG07: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov x20, x0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 mov x2, x0 mov x1, x20 mov x0, x19 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x19 bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 288 1113: JIT compiled System.Text.UTF8Encoding:GetMaxByteCount(int) [Tier1, IL size=79, code size=288] ; Assembly listing for method System.Text.EncoderExceptionFallback:get_MaxCharCount():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1114: JIT compiled System.Text.EncoderExceptionFallback:get_MaxCharCount() [Tier1, IL size=2, code size=20] ; Assembly listing for method System.Text.EncoderNLS:GetBytes(ulong,int,ulong,int,bool):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; PGO data available, but IL did not match ; 2 inlinees with PGO data; 2 single block inlinees; 2 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! stp x19, x20, [sp, #0x10] mov fp, sp mov x6, x0 mov w19, w2 mov w20, w4 G_M000_IG02: cbz x1, G_M000_IG04 cbz x3, G_M000_IG05 tbnz w20, #31, G_M000_IG06 tbnz w19, #31, G_M000_IG07 strb w5, [x6, #0x26] mov w0, #1 strb w0, [x6, #0x27] ldr x0, [x6, #0x18] mov w2, w19 mov w4, w20 mov x5, x6 ldr x6, [x0] ldr x6, [x6, #0x70] ldr x6, [x6, #0x30] G_M000_IG03: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 br x6 G_M000_IG04: movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 brk_windows #0 G_M000_IG05: mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 brk_windows #0 G_M000_IG06: movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov w1, w20 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 brk_windows #0 G_M000_IG07: movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov w1, w19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 brk_windows #0 ; Total bytes of code 288 1115: JIT compiled System.Text.EncoderNLS:GetBytes(ulong,int,ulong,int,bool) [Tier1, IL size=78, code size=288] ; Assembly listing for method System.Text.Encoding:GetBytes(ulong,int,ulong,int,System.Text.EncoderNLS):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 5647 ; 1 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x60]! stp x19, x20, [sp, #0x28] stp x21, x22, [sp, #0x38] stp x23, x24, [sp, #0x48] str x25, [sp, #0x58] mov fp, sp mov x21, x0 mov x22, x1 mov w20, w2 mov x23, x3 mov w24, w4 mov x19, x5 G_M000_IG02: mov w25, wzr str wzr, [fp, #0x20] ldrh w4, [x19, #0x24] cbnz w4, G_M000_IG08 ldr x4, [x19, #0x10] cbnz x4, G_M000_IG10 G_M000_IG03: ldr x25, [x21] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 cmp x25, x4 bne G_M000_IG05 G_M000_IG04: add x4, fp, #24 add x5, fp, #16 mov x0, x22 mov w1, w20 mov x2, x23 mov w3, w24 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x5, [fp, #0x18] sub x5, x5, x22 add x5, x5, x5, LSR #63 asr x5, x5, #1 str w5, [fp, #0x20] ldr x5, [fp, #0x10] sub x25, x5, x23 b G_M000_IG06 G_M000_IG05: add x5, fp, #32 mov x0, x21 mov x1, x22 mov w2, w20 mov x3, x23 mov w4, w24 ldr x6, [x25, #0x70] ldr x6, [x6, #0x38] blr x6 mov w25, w0 G_M000_IG06: ldr w0, [fp, #0x20] cmp w0, w20 bne G_M000_IG08 str w20, [x19, #0x20] mov w0, w25 G_M000_IG07: ldr x25, [sp, #0x58] ldp x23, x24, [sp, #0x48] ldp x21, x22, [sp, #0x38] ldp x19, x20, [sp, #0x28] ldp fp, lr, [sp], #0x60 ret lr G_M000_IG08: mov x0, x21 mov x1, x22 mov w2, w20 mov x3, x23 mov w4, w24 ldr w5, [fp, #0x20] mov w6, w25 mov x7, x19 movz x8, #0xD1FFAB1E movk x8, #0xD1FFAB1E LSL #16 movk x8, #0xD1FFAB1E LSL #32 ldr x8, [x8] blr x8 G_M000_IG09: ldr x25, [sp, #0x58] ldp x23, x24, [sp, #0x48] ldp x21, x22, [sp, #0x38] ldp x19, x20, [sp, #0x28] ldp fp, lr, [sp], #0x60 ret lr G_M000_IG10: ldr x0, [x19, #0x10] ldr x1, [x0] ldr x1, [x1, #0x48] ldr x1, [x1] blr x1 cmp w0, #0 cset x0, gt cbnz w0, G_M000_IG08 b G_M000_IG03 ; Total bytes of code 368 1116: JIT compiled System.Text.Encoding:GetBytes(ulong,int,ulong,int,System.Text.EncoderNLS) [Tier1 with Static PGO, IL size=57, code size=368] ; Assembly listing for method System.Text.EncoderNLS:get_HasLeftoverData():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 5647 G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldrh w1, [x0, #0x24] cbnz w1, G_M000_IG04 ldr x1, [x0, #0x10] cbnz x1, G_M000_IG06 mov w0, wzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG04: mov w0, #1 G_M000_IG05: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG06: ldr x0, [x0, #0x10] ldr x1, [x0] ldr x1, [x1, #0x48] ldr x1, [x1] blr x1 cmp w0, #0 cset x0, gt G_M000_IG07: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 84 1117: JIT compiled System.Text.EncoderNLS:get_HasLeftoverData() [Tier1 with Static PGO, IL size=35, code size=84] ; Assembly listing for method System.Text.Unicode.Utf8Utility:TranscodeToUtf8(ulong,int,ulong,int,byref,byref):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 183636 ; 13 inlinees with PGO data; 29 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x40]! stp x19, x20, [sp, #0x10] stp x21, x22, [sp, #0x20] stp x23, x24, [sp, #0x30] mov fp, sp mov x19, x0 mov w22, w1 mov x20, x2 mov w21, w3 mov x23, x4 mov x24, x5 G_M000_IG02: cmp w22, w21 csel w2, w22, w21, le mov w2, w2 mov x0, x19 mov x1, x20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x19, x19, x0, LSL #1 add x20, x20, x0 cmp w0, w22 bne G_M000_IG35 G_M000_IG03: str x19, [x23] str x20, [x24] mov w0, wzr G_M000_IG04: ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG05: sub w3, w2, #0xD1FFAB1E, LSL #12 movn w0, #0xD1FFAB1E LSL #16 cmp w3, w0 bhi G_M000_IG09 cmp w21, #4 blt G_M000_IG61 G_M000_IG06: lsr w0, w2, #6 and w0, w0, #0xD1FFAB1E lsl w2, w2, #8 and w2, w2, #0xD1FFAB1E add w0, w0, w2 movz w2, #0xD1FFAB1E movk w2, #0xD1FFAB1E LSL #16 add w0, w0, w2 str w0, [x20] add x19, x19, #4 add x20, x20, #4 sub w21, w21, #4 cmp x19, x1 bhi G_M000_IG18 G_M000_IG07: ldr w2, [x19] sub w0, w2, #128 uxth w0, w0 cmp w0, #0xD1FFAB1E bhs G_M000_IG12 b G_M000_IG05 G_M000_IG08: b G_M000_IG27 G_M000_IG09: cmp w21, #2 blt G_M000_IG55 lsl w0, w2, #2 and w0, w0, #0xD1FFAB1E and w3, w2, #63 add w0, w0, w3 mov w3, #0xD1FFAB1E add w0, w0, w3 uxth w0, w0 rev16 w0, w0 uxth w0, w0 strh w0, [x20] cmp w2, #0xD1FFAB1E, LSL #12 bhs G_M000_IG32 cmp w21, #3 blt G_M000_IG60 lsr w2, w2, #16 strb w2, [x20, #0x02] add x19, x19, #4 add x20, x20, #3 sub w21, w21, #3 G_M000_IG10: cmp x19, x1 bhi G_M000_IG18 G_M000_IG11: ldr w2, [x19] G_M000_IG12: tst w2, #0xD1FFAB1E beq G_M000_IG16 G_M000_IG13: tst w2, #0xD1FFAB1E beq G_M000_IG37 G_M000_IG14: tst w2, #0xD1FFAB1E bne G_M000_IG33 G_M000_IG15: b G_M000_IG05 G_M000_IG16: cmp w21, #2 blt G_M000_IG61 orr w2, w2, w2, LSR #8 strh w2, [x20] add x19, x19, #4 add x20, x20, #2 sub w21, w21, #2 sub x0, x1, x19 add x0, x0, x0, LSR #63 asr x0, x0, #1 add w0, w0, #2 mov w0, w0 sxtw x2, w21 cmp x0, x2 ble G_M000_IG08 G_M000_IG17: b G_M000_IG39 G_M000_IG18: sub x0, x1, x19 add x0, x0, x0, LSR #63 asr x0, x0, #1 add w22, w0, #2 G_M000_IG19: cbz w22, G_M000_IG24 G_M000_IG20: ldrh w3, [x19] G_M000_IG21: cmp w3, #127 bhi G_M000_IG51 G_M000_IG22: cbz w21, G_M000_IG55 strb w3, [x20] add x19, x19, #2 add x20, x20, #1 G_M000_IG23: cmp w22, #1 bgt G_M000_IG55 G_M000_IG24: mov w0, wzr G_M000_IG25: str x19, [x23] str x20, [x24] G_M000_IG26: ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG27: lsr w2, w0, #3 mov w3, wzr cmp w2, #0 bls G_M000_IG30 G_M000_IG28: ldr q17, [x19] cmtst v18.8h, v17.8h, v16.8h sminp v18.8h, v18.8h, v18.8h umov x4, v18.d[0] cbnz x4, G_M000_IG40 G_M000_IG29: sqxtun v17.8b, v17.8h str d17, [x20] add x19, x19, #16 add x20, x20, #8 add w3, w3, #1 cmp w3, w2 blo G_M000_IG28 G_M000_IG30: sub w21, w21, w3, LSL #3 tbz w0, #2, G_M000_IG10 G_M000_IG31: ldr x0, [x19] tst x0, #0xD1FFAB1E bne G_M000_IG41 ins v17.d[0], x0 sqxtun v17.8b, v17.8h st1 {v17.s}[0], [x20] add x19, x19, #8 b G_M000_IG59 G_M000_IG32: add x19, x19, #2 add x20, x20, #2 sub w21, w21, #2 cmp x19, x1 bhi G_M000_IG18 ldr w2, [x19] G_M000_IG33: movn w0, #0xD1FFAB1E add w0, w2, w0 tst w0, #0xD1FFAB1E beq G_M000_IG58 tst w2, #0xD1FFAB1E beq G_M000_IG49 mov w0, #0xD1FFAB1E add w0, w2, w0 mov w3, #0xD1FFAB1E cmp w0, w3 blo G_M000_IG49 G_M000_IG34: b G_M000_IG43 G_M000_IG35: sub w22, w22, w0 sub w21, w21, w0 cmp w22, #2 blt G_M000_IG19 G_M000_IG36: ubfiz x0, x22, #1, #32 add x0, x19, x0 sub x1, x0, #4 ldr q16, [@RWD00] b G_M000_IG11 G_M000_IG37: cbz w21, G_M000_IG55 G_M000_IG38: b G_M000_IG46 G_M000_IG39: mov x0, x2 b G_M000_IG27 G_M000_IG40: sub w21, w21, w3, LSL #3 umov x0, v17.d[0] tst x0, #0xD1FFAB1E beq G_M000_IG45 G_M000_IG41: mov w2, w0 tst w2, #0xD1FFAB1E bne G_M000_IG13 G_M000_IG42: orr w2, w2, w2, LSR #8 strh w2, [x20] add x19, x19, #4 add x20, x20, #2 sub w21, w21, #2 lsr x2, x0, #32 b G_M000_IG13 G_M000_IG43: cmp w21, #6 blt G_M000_IG49 lsl w0, w2, #2 and w0, w0, #0xD1FFAB1E and w3, w2, #63 orr w0, w0, w3, LSL #16 lsr w3, w2, #4 and w3, w3, #0xD1FFAB1E lsr w4, w2, #12 and w4, w4, #15 orr w3, w3, w4 add w0, w0, w3 movz w3, #0xD1FFAB1E movk w3, #0xD1FFAB1E LSL #16 add w0, w0, w3 str w0, [x20] lsr w0, w2, #22 and w0, w0, #63 lsr w2, w2, #8 and w2, w2, #0xD1FFAB1E add w0, w0, w2 mov w2, #0xD1FFAB1E add w0, w0, w2 strh w0, [x20, #0x04] add x19, x19, #4 add x20, x20, #6 sub w21, w21, #6 cmp x19, x1 bhi G_M000_IG18 G_M000_IG44: b G_M000_IG47 G_M000_IG45: sqxtun v18.8b, v17.8h st1 {v18.s}[0], [x20] add x19, x19, #8 add x20, x20, #4 sub w21, w21, #4 mov w0, #1 umov x0, v17.d[1] b G_M000_IG41 G_M000_IG46: strb w2, [x20] add x19, x19, #2 add x20, x20, #1 sub w21, w21, #1 cmp x19, x1 bhi G_M000_IG18 ldr w2, [x19] b G_M000_IG14 G_M000_IG47: ldr w2, [x19] tst w2, #0xD1FFAB1E bne G_M000_IG33 G_M000_IG48: b G_M000_IG12 G_M000_IG49: cmp w21, #3 blt G_M000_IG55 lsl w0, w2, #2 and w0, w0, #0xD1FFAB1E uxth w3, w2 add w0, w0, w3, LSR #12 mov w3, #0xD1FFAB1E add w0, w0, w3 strh w0, [x20] and w0, w2, #63 orr w0, w0, #0xD1FFAB1E strb w0, [x20, #0x02] add x19, x19, #2 add x20, x20, #3 sub w21, w21, #3 cmp w2, #0xD1FFAB1E, LSL #12 bhs G_M000_IG57 cbz w21, G_M000_IG55 lsr w2, w2, #16 strb w2, [x20] add x19, x19, #2 add x20, x20, #1 sub w21, w21, #1 cmp x19, x1 bhi G_M000_IG18 ldr w2, [x19] tst w2, #0xD1FFAB1E bne G_M000_IG33 G_M000_IG50: b G_M000_IG12 G_M000_IG51: cmp w3, #0xD1FFAB1E bhs G_M000_IG53 G_M000_IG52: cmp w21, #2 blt G_M000_IG55 and w0, w3, #63 orr w0, w0, #0xD1FFAB1E strb w0, [x20, #0x01] lsr w3, w3, #6 orr w0, w3, #0xD1FFAB1E strb w0, [x20] add x19, x19, #2 add x20, x20, #2 b G_M000_IG23 G_M000_IG53: movn w0, #0xD1FFAB1E add w0, w3, w0 cmp w0, #0xD1FFAB1E bls G_M000_IG54 cmp w21, #3 blt G_M000_IG55 and w0, w3, #63 orr w0, w0, #0xD1FFAB1E strb w0, [x20, #0x02] lsr w0, w3, #6 and w0, w0, #63 orr w0, w0, #0xD1FFAB1E strb w0, [x20, #0x01] lsr w0, w3, #12 orr w0, w0, #0xD1FFAB1E strb w0, [x20] add x19, x19, #2 add x20, x20, #3 b G_M000_IG23 G_M000_IG54: mov w0, #0xD1FFAB1E cmp w3, w0 bhi G_M000_IG56 mov w0, #2 b G_M000_IG25 G_M000_IG55: mov w0, #1 b G_M000_IG25 G_M000_IG56: mov w0, #3 b G_M000_IG25 G_M000_IG57: cmp x19, x1 bhi G_M000_IG18 ldr w2, [x19] b G_M000_IG13 G_M000_IG58: movz w0, #0xD1FFAB1E movk w0, #0xD1FFAB1E LSL #16 add w0, w2, w0 tst w0, #0xD1FFAB1E bne G_M000_IG56 cmp w21, #4 blt G_M000_IG55 add w2, w2, #64 and w0, w2, #3 movz w3, #0xD1FFAB1E movk w3, #0xD1FFAB1E LSL #16 orr w0, w3, w0, LSL #20 movz w3, #0xD1FFAB1E movk w3, #63 LSL #16 and w3, w2, w3 rev w3, w3 ror w3, w3, #16 orr w0, w0, w3 lsr w3, w2, #6 and w3, w3, #0xD1FFAB1E orr w0, w0, w3 and w2, w2, #252 orr w0, w0, w2, LSL #6 str w0, [x20] add x19, x19, #4 G_M000_IG59: add x20, x20, #4 sub w21, w21, #4 b G_M000_IG10 G_M000_IG60: add x19, x19, #2 add x20, x20, #2 b G_M000_IG55 G_M000_IG61: uxth w3, w2 b G_M000_IG21 RWD00 dq FF80FF80FF80FF80h, FF80FF80FF80FF80h ; Total bytes of code 1428 1118: JIT compiled System.Text.Unicode.Utf8Utility:TranscodeToUtf8(ulong,int,ulong,int,byref,byref) [Tier1 with Static PGO, IL size=1559, code size=1428] ; Assembly listing for method System.Text.Ascii:NarrowUtf16ToAscii(ulong,ulong,ulong):ulong ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 10 single block inlinees; 2 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x10] stp x21, x22, [sp, #0x20] mov fp, sp mov x19, x0 mov x20, x1 mov x21, x2 G_M000_IG02: mov x0, xzr cmp x21, #32 blo G_M000_IG04 G_M000_IG03: ldr x22, [x19] tst x22, #0xD1FFAB1E bne G_M000_IG10 mov x0, x19 mov x1, x20 mov x2, x21 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG04: sub x1, x21, x0 cmp x1, #4 blo G_M000_IG06 add x2, x0, x1 sub x2, x2, #4 align [0 bytes for IG05] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG05: lsl x3, x0, #1 ldr x22, [x19, x3] tst x22, #0xD1FFAB1E bne G_M000_IG10 ins v16.d[0], x22 sqxtun v16.8b, v16.8h umov w3, v16.s[0] str w3, [x20, x0] add x0, x0, #4 cmp x0, x2 bls G_M000_IG05 G_M000_IG06: tbz w1, #1, G_M000_IG07 lsl x2, x0, #1 ldr w2, [x19, x2] tst w2, #0xD1FFAB1E bne G_M000_IG11 add x3, x20, x0 strb w2, [x3] lsr w2, w2, #16 strb w2, [x3, #0x01] add x0, x0, #2 G_M000_IG07: tbz w1, #0, G_M000_IG09 lsl x1, x0, #1 ldrh w2, [x19, x1] cmp w2, #127 bhi G_M000_IG09 G_M000_IG08: strb w2, [x20, x0] add x0, x0, #1 G_M000_IG09: ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG10: mov w2, w22 tst w2, #0xD1FFAB1E bne G_M000_IG11 add x1, x20, x0 strb w2, [x1] lsr w2, w2, #16 strb w2, [x1, #0x01] lsr x2, x22, #32 add x0, x0, #2 G_M000_IG11: tst w2, #0xD1FFAB1E beq G_M000_IG08 b G_M000_IG09 ; Total bytes of code 280 1119: JIT compiled System.Text.Ascii:NarrowUtf16ToAscii(ulong,ulong,ulong) [Tier1, IL size=491, code size=280] ; Assembly listing for method System.IO.FileStream:Write(System.ReadOnlySpan`1[ubyte]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 2914 ; 1 inlinees with PGO data; 3 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x40]! stp x19, x20, [sp, #0x28] str x21, [sp, #0x38] mov fp, sp str xzr, [fp, #0x18] mov x19, x1 mov w20, w2 G_M000_IG02: ldr x21, [x0, #0x10] ldr x0, [x21] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 cmp x0, x1 bne G_M000_IG07 G_M000_IG03: ldr x0, [x21, #0x18] ldr x1, [x0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 cmp x1, x2 bne G_M000_IG04 ldr x0, [x0, #0x18] ldr w0, [x0, #0x10] dmb ishld tbz w0, #0, G_M000_IG05 b G_M000_IG08 G_M000_IG04: ldr x1, [x1, #0x68] ldr x1, [x1, #0x28] blr x1 cbnz w0, G_M000_IG08 G_M000_IG05: str xzr, [fp, #0x18] str xzr, [fp, #0x20] ldp x3, x4, [fp, #0x18] mov x1, x19 mov w2, w20 mov x0, x21 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 G_M000_IG06: ldr x21, [sp, #0x38] ldp x19, x20, [sp, #0x28] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG07: mov x1, x19 mov w2, w20 mov x0, x21 ldr x3, [x21] ldr x3, [x3, #0x60] ldr x3, [x3, #0x38] blr x3 b G_M000_IG06 G_M000_IG08: mov x0, xzr movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 brk_windows #0 ; Total bytes of code 240 1120: JIT compiled System.IO.FileStream:Write(System.ReadOnlySpan`1[ubyte]) [Tier1 with Static PGO, IL size=13, code size=240] ; Assembly listing for method System.IO.Strategies.OSFileStreamStrategy:Write(System.ReadOnlySpan`1[ubyte]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 306 ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! stp x19, x20, [sp, #0x10] mov fp, sp mov x19, x0 mov w20, w2 G_M000_IG02: ldr x2, [x19, #0x18] ldr w2, [x2, #0x10] dmb ishld tbnz w2, #0, G_M000_IG04 ldr w2, [x19, #0x30] tbz w2, #1, G_M000_IG05 mov w2, w20 ldp x0, x3, [x19, #0x18] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [x19, #0x20] add x0, x0, w20, UXTW str x0, [x19, #0x20] G_M000_IG03: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 ; Total bytes of code 144 1121: JIT compiled System.IO.Strategies.OSFileStreamStrategy:Write(System.ReadOnlySpan`1[ubyte]) [Tier1 with Static PGO, IL size=75, code size=144] ; Assembly listing for method System.IO.RandomAccess:WriteAtOffset(Microsoft.Win32.SafeHandles.SafeFileHandle,System.ReadOnlySpan`1[ubyte],long) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; PGO data available, but IL did not match ; 1 inlinees with PGO data; 4 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x80]! stp x19, x20, [sp, #0x60] stp x21, x22, [sp, #0x70] mov fp, sp str xzr, [fp, #0x38] mov x19, x0 mov x22, x1 mov w21, w2 mov x20, x3 G_M000_IG02: cbnz w21, G_M000_IG04 G_M000_IG03: ldp x21, x22, [sp, #0x70] ldp x19, x20, [sp, #0x60] ldp fp, lr, [sp], #0x80 ret lr G_M000_IG04: ldrsb wzr, [x19] mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 tbz w0, #30, G_M000_IG06 mov x1, x22 mov w2, w21 mov x0, x19 mov x3, x20 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG05: ldp x21, x22, [sp, #0x70] ldp x19, x20, [sp, #0x60] ldp fp, lr, [sp], #0x80 ret lr G_M000_IG06: stp xzr, xzr, [fp, #0x10] stp xzr, xzr, [fp, #0x20] mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG08 G_M000_IG07: str w20, [fp, #0x20] asr x0, x20, #32 str w0, [fp, #0x24] G_M000_IG08: ldp q16, q17, [fp, #0x10] stp q16, q17, [fp, #0x40] str x22, [fp, #0x38] mov x1, x22 mov x0, x19 add x4, fp, #64 add x3, fp, #48 mov w2, w21 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 cbz w0, G_M000_IG10 G_M000_IG09: ldp x21, x22, [sp, #0x70] ldp x19, x20, [sp, #0x60] ldp fp, lr, [sp], #0x80 ret lr G_M000_IG10: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [x19, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 316 1122: JIT compiled System.IO.RandomAccess:WriteAtOffset(Microsoft.Win32.SafeHandles.SafeFileHandle,System.ReadOnlySpan`1[ubyte],long) [Tier1, IL size=89, code size=316] ; Assembly listing for method Microsoft.Win32.SafeHandles.SafeFileHandle:GetFileOptions():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 6301 G_M000_IG01: stp fp, lr, [sp, #-0x30]! str x19, [sp, #0x28] mov fp, sp mov x19, x0 G_M000_IG02: ldr w0, [x19, #0x40] dmb ishld cmn w0, #1 beq G_M000_IG04 G_M000_IG03: ldr x19, [sp, #0x28] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: add x2, fp, #32 add x1, fp, #16 mov x0, x19 mov w3, #4 mov w4, #16 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 cbnz w0, G_M000_IG06 mov w0, wzr ldr w1, [fp, #0x20] mov w2, #0xD1FFAB1E tst w1, #48 csel w0, w0, w2, ne ldr w1, [fp, #0x20] orr w2, w0, #0xD1FFAB1E tst w1, #2 csel w0, w0, w2, eq ldr w1, [fp, #0x20] orr w2, w0, #0xD1FFAB1E tst w1, #0xD1FFAB1E csel w0, w0, w2, eq ldr w1, [fp, #0x20] orr w2, w0, #0xD1FFAB1E tst w1, #4 csel w0, w0, w2, eq ldr w1, [fp, #0x20] orr w2, w0, #0xD1FFAB1E tst w1, #0xD1FFAB1E csel w0, w0, w2, eq ldr w1, [fp, #0x20] orr w2, w0, #0xD1FFAB1E tst w1, #8 csel w0, w0, w2, eq dmb ish str w0, [x19, #0x40] G_M000_IG05: ldr x19, [sp, #0x28] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG06: bl Interop+NtDll:RtlNtStatusToDosError(int):uint mov w19, w0 mov w0, #85 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov x1, x0 mov w0, w19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 272 1123: JIT compiled Microsoft.Win32.SafeHandles.SafeFileHandle:GetFileOptions() [Tier1 with Static PGO, IL size=159, code size=272] ; Assembly listing for method System.IO.RandomAccess:GetNativeOverlappedForSyncHandle(Microsoft.Win32.SafeHandles.SafeFileHandle,long):System.Threading.NativeOverlapped ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 6137 ; 2 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x50]! stp x19, x20, [sp, #0x30] stp x21, x22, [sp, #0x40] mov fp, sp mov x19, x0 mov x20, x1 mov x21, x8 G_M000_IG02: stp xzr, xzr, [fp, #0x10] stp xzr, xzr, [fp, #0x20] ldr w0, [x19, #0x10] dmb ishld tbnz w0, #0, G_M000_IG04 ldr w22, [x19, #0x44] dmb ishld cmn w22, #1 beq G_M000_IG06 G_M000_IG03: cmp w22, #1 bne G_M000_IG04 str w20, [fp, #0x20] asr x0, x20, #32 str w0, [fp, #0x24] G_M000_IG04: ldp q16, q17, [fp, #0x10] stp q16, q17, [x21] G_M000_IG05: ldp x21, x22, [sp, #0x40] ldp x19, x20, [sp, #0x30] ldp fp, lr, [sp], #0x50 ret lr G_M000_IG06: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov w22, w0 dmb ish str w22, [x19, #0x44] b G_M000_IG03 ; Total bytes of code 148 1124: JIT compiled System.IO.RandomAccess:GetNativeOverlappedForSyncHandle(Microsoft.Win32.SafeHandles.SafeFileHandle,long) [Tier1 with Static PGO, IL size=39, code size=148] ; Assembly listing for method Microsoft.Win32.SafeHandles.SafeFileHandle:get_CanSeek():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 130812 ; 1 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! stp x19, x20, [sp, #0x10] mov fp, sp mov x19, x0 G_M000_IG02: ldr w0, [x19, #0x10] dmb ishld tbnz w0, #0, G_M000_IG06 ldr w20, [x19, #0x44] dmb ishld cmn w20, #1 beq G_M000_IG05 G_M000_IG03: cmp w20, #1 cset x0, eq G_M000_IG04: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG05: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov w20, w0 dmb ish str w20, [x19, #0x44] b G_M000_IG03 G_M000_IG06: mov w0, wzr G_M000_IG07: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 120 1125: JIT compiled Microsoft.Win32.SafeHandles.SafeFileHandle:get_CanSeek() [Tier1 with Static PGO, IL size=20, code size=120] ; Assembly listing for method Interop+Kernel32:WriteFile(System.Runtime.InteropServices.SafeHandle,ulong,int,byref,ulong):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 382 ; 0 inlinees with PGO data; 4 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0xD0]! stp x19, x20, [sp, #0x80] stp x21, x22, [sp, #0x90] stp x23, x24, [sp, #0xA0] stp x25, x26, [sp, #0xB0] stp x27, x28, [sp, #0xC0] mov fp, sp str xzr, [fp, #0x68] add x5, sp, #208 str x5, [fp, #0x78] str x0, [fp, #0x60] mov x20, x1 mov w21, w2 mov x19, x3 mov x22, x4 G_M000_IG02: add x0, fp, #32 mov x1, x12 bl CORINFO_HELP_INIT_PINVOKE_FRAME mov x23, x0 mov x1, sp str x1, [fp, #0x40] mov x1, fp str x1, [fp, #0x50] str wzr, [fp, #0x70] G_M000_IG03: add x1, fp, #112 ldr x0, [fp, #0x60] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0x60] ldr x24, [x0, #0x08] G_M000_IG04: str x19, [fp, #0x68] mov w0, wzr movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 G_M000_IG05: blr x1 mov x0, x24 mov x1, x20 mov w2, w21 mov x3, x19 mov x4, x22 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 str x5, [fp, #0x30] adr x5, [G_M000_IG08] str x5, [fp, #0x48] add x5, fp, #32 str x5, [x23, #0x10] strb wzr, [x23, #0x0C] G_M000_IG06: movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 G_M000_IG07: blr x5 G_M000_IG08: mov w19, w0 mov w0, #1 strb w0, [x23, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG09 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG09: ldr x0, [fp, #0x28] str x0, [x23, #0x10] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG10: blr x0 mov w20, w0 G_M000_IG11: str xzr, [fp, #0x68] G_M000_IG12: ldrb w0, [fp, #0x70] cbz w0, G_M000_IG13 ldr x0, [fp, #0x60] mov w1, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG13: mov w0, w20 bl System.Runtime.InteropServices.Marshal:SetLastPInvokeError(int) mov w0, w19 G_M000_IG14: ldp x27, x28, [sp, #0xC0] ldp x25, x26, [sp, #0xB0] ldp x23, x24, [sp, #0xA0] ldp x21, x22, [sp, #0x90] ldp x19, x20, [sp, #0x80] ldp fp, lr, [sp], #0xD0 ret lr G_M000_IG15: stp fp, lr, [sp, #-0x70]! stp x19, x20, [sp, #0x20] stp x21, x22, [sp, #0x30] stp x23, x24, [sp, #0x40] stp x25, x26, [sp, #0x50] stp x27, x28, [sp, #0x60] add x3, fp, #208 str x3, [sp, #0x18] G_M000_IG16: str xzr, [fp, #0x68] G_M000_IG17: ldp x27, x28, [sp, #0x60] ldp x25, x26, [sp, #0x50] ldp x23, x24, [sp, #0x40] ldp x21, x22, [sp, #0x30] ldp x19, x20, [sp, #0x20] ldp fp, lr, [sp], #0x70 ret lr G_M000_IG18: stp fp, lr, [sp, #-0x70]! stp x19, x20, [sp, #0x20] stp x21, x22, [sp, #0x30] stp x23, x24, [sp, #0x40] stp x25, x26, [sp, #0x50] stp x27, x28, [sp, #0x60] add x3, fp, #208 str x3, [sp, #0x18] G_M000_IG19: ldrb w0, [fp, #0x70] cbz w0, G_M000_IG20 ldr x0, [fp, #0x60] ldrsb wzr, [x0] mov w1, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG20: ldp x27, x28, [sp, #0x60] ldp x25, x26, [sp, #0x50] ldp x23, x24, [sp, #0x40] ldp x21, x22, [sp, #0x30] ldp x19, x20, [sp, #0x20] ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 544 1126: JIT compiled Interop+Kernel32:WriteFile(System.Runtime.InteropServices.SafeHandle,ulong,int,byref,ulong) [Tier1 with Static PGO, IL size=84, code size=544] ; Assembly listing for method System.Runtime.InteropServices.SafeHandle:DangerousAddRef(byref):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 243598 ; 1 inlinees with PGO data; 0 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: add x2, x0, #16 ldar w3, [x2] tbnz w3, #0, G_M000_IG05 add w4, w3, #4 mov w5, w3 casal w5, w4, [x2] cmp w5, w3 bne G_M000_IG02 G_M000_IG03: mov w0, #1 strb w0, [x1] G_M000_IG04: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG05: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 brk_windows #0 ; Total bytes of code 80 1127: JIT compiled System.Runtime.InteropServices.SafeHandle:DangerousAddRef(byref) [Tier1 with Static PGO, IL size=45, code size=80] ; Assembly listing for method System.Runtime.InteropServices.SafeHandle:InternalRelease(bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 249337 ; 1 inlinees with PGO data; 0 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x18] str x21, [sp, #0x28] mov fp, sp mov x19, x0 mov w20, w1 G_M000_IG02: ldr w21, [x19, #0x10] dmb ishld tst w20, #255 bne G_M000_IG11 G_M000_IG03: tst w21, #0xD1FFAB1E bne G_M000_IG04 mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 brk_windows #0 G_M000_IG04: and w0, w21, #0xD1FFAB1E cmp w0, #4 bne G_M000_IG05 ldrb w0, [x19, #0x14] cbz w0, G_M000_IG05 mov x0, x19 ldr x1, [x19] ldr x1, [x1, #0x40] ldr x1, [x1, #0x20] blr x1 cmp w0, #0 cset x0, eq b G_M000_IG06 G_M000_IG05: mov w0, wzr G_M000_IG06: uxtb w0, w0 sub w1, w21, #4 and w2, w21, #0xD1FFAB1E cmp w2, #4 bne G_M000_IG07 orr w1, w1, #1 G_M000_IG07: tst w20, #255 beq G_M000_IG08 orr w1, w1, #2 G_M000_IG08: add x2, x19, #16 mov w3, w21 casal w3, w1, [x2] cmp w3, w21 bne G_M000_IG02 cbz w0, G_M000_IG10 bl System.Runtime.InteropServices.Marshal:GetLastPInvokeError():int mov w20, w0 mov x0, x19 ldr x1, [x19] ldr x1, [x1, #0x40] ldr x1, [x1, #0x38] blr x1 mov w0, w20 G_M000_IG09: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 b System.Runtime.InteropServices.Marshal:SetLastPInvokeError(int) G_M000_IG10: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG11: tbz w21, #1, G_M000_IG03 G_M000_IG12: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 276 1128: JIT compiled System.Runtime.InteropServices.SafeHandle:InternalRelease(bool) [Tier1 with Static PGO, IL size=120, code size=276] ; Assembly listing for method System.IO.FileStream:Flush():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 481 ; 5 inlinees with PGO data; 2 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x18] str x21, [sp, #0x28] mov fp, sp mov x19, x0 G_M000_IG02: ldr x0, [x19] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 cmp x0, x1 bne G_M000_IG14 mov x0, x19 ldr x0, [x0, #0x10] ldr x1, [x0] movz x20, #0xD1FFAB1E movk x20, #0xD1FFAB1E LSL #16 movk x20, #0xD1FFAB1E LSL #32 cmp x1, x20 bne G_M000_IG08 G_M000_IG03: ldr x0, [x0, #0x18] ldr x1, [x0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 cmp x1, x2 bne G_M000_IG15 ldr x0, [x0, #0x18] ldr w0, [x0, #0x10] dmb ishld and w21, w0, #1 G_M000_IG04: cbnz w21, G_M000_IG16 ldr x19, [x19, #0x10] ldr x1, [x19] cmp x1, x20 bne G_M000_IG12 G_M000_IG05: ldr w2, [x19, #0x2C] cmp w2, #0 ble G_M000_IG10 ldp x0, x1, [x19, #0x18] ldr x3, [x0] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 cmp x3, x4 bne G_M000_IG13 G_M000_IG06: cbz x1, G_M000_IG17 ldr w3, [x1, #0x08] cmp w3, w2 blo G_M000_IG17 add x1, x1, #16 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG07: str wzr, [x19, #0x2C] b G_M000_IG11 G_M000_IG08: ldr x1, [x0] ldr x1, [x1, #0x68] ldr x1, [x1, #0x28] blr x1 mov w21, w0 b G_M000_IG04 G_M000_IG09: ldr x21, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG10: ldr w0, [x19, #0x34] cmp w0, #0 ble G_M000_IG11 ldr x0, [x19, #0x18] ldr x1, [x0] ldr x1, [x1, #0x40] ldr x1, [x1, #0x38] blr x1 cbz w0, G_M000_IG11 mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG11: ldr x0, [x19, #0x18] mov w1, wzr ldr x2, [x0] ldr x2, [x2, #0x70] ldr x2, [x2] blr x2 b G_M000_IG09 G_M000_IG12: mov x0, x19 mov w1, wzr ldr x2, [x19] ldr x2, [x2, #0x70] ldr x2, [x2] blr x2 b G_M000_IG09 G_M000_IG13: mov w3, w2 mov w2, wzr ldr x4, [x0] ldr x4, [x4, #0x60] ldr x4, [x4, #0x30] blr x4 b G_M000_IG07 G_M000_IG14: mov x0, x19 mov w1, wzr ldr x2, [x19] ldr x2, [x2, #0x68] ldr x2, [x2, #0x28] blr x2 b G_M000_IG09 G_M000_IG15: ldr x1, [x0] ldr x1, [x1, #0x68] ldr x1, [x1, #0x28] blr x1 mov w21, w0 b G_M000_IG04 G_M000_IG16: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 G_M000_IG17: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 ; Total bytes of code 512 1129: JIT compiled System.IO.FileStream:Flush() [Tier1 with Static PGO, IL size=8, code size=512] ; Assembly listing for method System.IO.Strategies.OSFileStreamStrategy:get_IsClosed():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr x0, [x0, #0x18] ldr w0, [x0, #0x10] dmb ishld and w0, w0, #1 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 32 1130: JIT compiled System.IO.Strategies.OSFileStreamStrategy:get_IsClosed() [Tier1, IL size=12, code size=32] ; Assembly listing for method System.IO.Strategies.OSFileStreamStrategy:Flush(bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 2095 G_M000_IG01: stp fp, lr, [sp, #-0x20]! str x19, [sp, #0x18] mov fp, sp mov x19, x0 G_M000_IG02: tst w1, #255 bne G_M000_IG04 G_M000_IG03: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 cbz w0, G_M000_IG03 ldr x0, [x19, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] G_M000_IG05: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 br x1 ; Total bytes of code 100 1131: JIT compiled System.IO.Strategies.OSFileStreamStrategy:Flush(bool) [Tier1 with Static PGO, IL size=23, code size=100] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:WorkloadWarmupStop(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x2, [fp, #0x10] mov w1, #14 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 1132: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:WorkloadWarmupStop(long) [Tier0, IL size=10, code size=56] ; Assembly listing for method BenchmarkDotNet.Engines.HostExtensions:BeforeMainRun(BenchmarkDotNet.Engines.IHost) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 mov w1, #2 ldr x2, [x11] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 48 1133: JIT compiled BenchmarkDotNet.Engines.HostExtensions:BeforeMainRun(BenchmarkDotNet.Engines.IHost) [Tier0, IL size=8, code size=48] ; Assembly listing for method BenchmarkDotNet.Engines.EngineActualStage:RunWorkload(long,int,bool):System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Reports.Measurement]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] str w3, [fp, #0x18] G_M000_IG02: ldr w5, [fp, #0x18] uxtb w5, w5 ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] ldr w4, [fp, #0x1C] mov w2, #1 mov w3, wzr movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 80 1134: JIT compiled BenchmarkDotNet.Engines.EngineActualStage:RunWorkload(long,int,bool) [Tier0, IL size=12, code size=80] ; Assembly listing for method BenchmarkDotNet.Engines.EngineActualStage:Run(long,int,bool,int,bool):System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Reports.Measurement]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str xzr, [x9, #0x30] str x0, [fp, #0x68] str x1, [fp, #0x60] str w2, [fp, #0x5C] str w3, [fp, #0x58] str w4, [fp, #0x54] str w5, [fp, #0x50] G_M000_IG02: ldr w0, [fp, #0x58] uxtb w0, w0 cbnz w0, G_M000_IG03 ldr x0, [fp, #0x68] ldrsb wzr, [x0] ldr x0, [fp, #0x68] add x0, x0, #36 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG04 G_M000_IG03: ldr w0, [fp, #0x50] uxtb w0, w0 cbz w0, G_M000_IG08 G_M000_IG04: ldr x0, [fp, #0x68] ldr x1, [x0, #0x24] str x1, [fp, #0x48] ldr x0, [fp, #0x68] str x0, [fp, #0x40] ldr x0, [fp, #0x60] str x0, [fp, #0x38] ldr w0, [fp, #0x5C] str w0, [fp, #0x34] add x0, fp, #72 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG05 ldr x0, [fp, #0x40] str x0, [fp, #0x28] ldr x0, [fp, #0x38] str x0, [fp, #0x20] ldr w0, [fp, #0x34] str w0, [fp, #0x1C] mov w0, #10 str w0, [fp, #0x18] b G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x40] str x0, [fp, #0x28] ldr x0, [fp, #0x38] str x0, [fp, #0x20] ldr w0, [fp, #0x34] str w0, [fp, #0x1C] add x0, fp, #72 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x18] G_M000_IG06: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] ldr w2, [fp, #0x1C] ldr w3, [fp, #0x18] ldr w4, [fp, #0x54] movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 G_M000_IG07: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG08: ldr x0, [fp, #0x68] ldr x1, [fp, #0x60] ldr w2, [fp, #0x5C] ldr w3, [fp, #0x54] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG09: ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 360 1135: JIT compiled BenchmarkDotNet.Engines.EngineActualStage:Run(long,int,bool,int,bool) [Tier0, IL size=69, code size=360] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:WorkloadActualStart(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x2, [fp, #0x10] mov w1, #15 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 1136: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:WorkloadActualStart(long) [Tier0, IL size=10, code size=56] ; Assembly listing for method BenchmarkDotNet.Engines.AnonymousPipesHost:WriteLine(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr x0, [x0, #0x08] ldr x2, [x0] ldr x2, [x2, #0x68] ldr x2, [x2, #0x30] G_M000_IG03: ldp fp, lr, [sp], #0x10 br x2 ; Total bytes of code 32 1137: JIT compiled BenchmarkDotNet.Engines.AnonymousPipesHost:WriteLine(System.String) [Tier1, IL size=13, code size=32] ; Assembly listing for method System.IO.StreamWriter:WriteLine(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 7 inlinees with PGO data; 7 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x60]! stp x19, x20, [sp, #0x20] stp x21, x22, [sp, #0x30] stp x23, x24, [sp, #0x40] stp x25, x26, [sp, #0x50] mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] mov x19, x0 G_M000_IG02: ldr x0, [x19, #0x48] ldr w0, [x0, #0x34] dmb ishld mov w2, #0xD1FFAB1E tst w0, w2 beq G_M000_IG28 cbz x1, G_M000_IG18 G_M000_IG03: add x20, x1, #12 ldr w21, [x1, #0x08] G_M000_IG04: ldr x0, [x19, #0x48] ldr w0, [x0, #0x34] dmb ishld mov w1, #0xD1FFAB1E tst w0, w1 beq G_M000_IG28 cmp w21, #4 ble G_M000_IG12 G_M000_IG05: ldrb w0, [x19, #0x5B] cbnz w0, G_M000_IG29 ldr x22, [x19, #0x40] str x20, [fp, #0x18] ldr w23, [x22, #0x08] cmp w23, #0 bls G_M000_IG31 add x0, x22, #16 str x0, [fp, #0x10] ldr x22, [fp, #0x10] ldr w24, [x19, #0x50] cmp w21, #0 ble G_M000_IG19 G_M000_IG06: cmp w23, w24 beq G_M000_IG14 G_M000_IG07: sub w25, w23, w24 cmp w25, w21 bgt G_M000_IG11 G_M000_IG08: mov w26, w25 G_M000_IG09: lsl w0, w26, #1 sxtw x2, w0 sbfiz x0, x24, #1, #32 add x0, x22, x0 cmp x2, #0 blt G_M000_IG27 mov x1, x20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr w0, [x19, #0x50] add w0, w0, w26 str w0, [x19, #0x50] add w24, w24, w26 sbfiz x0, x26, #1, #32 add x20, x20, x0 sub w21, w21, w26 cmp w21, #0 bgt G_M000_IG06 G_M000_IG10: b G_M000_IG19 G_M000_IG11: mov w26, w21 b G_M000_IG09 G_M000_IG12: ldp w1, w0, [x19, #0x50] sub w0, w0, w1 cmp w0, w21 blt G_M000_IG05 G_M000_IG13: b G_M000_IG15 G_M000_IG14: mov x0, x19 mov w1, wzr mov w2, wzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov w24, wzr b G_M000_IG07 align [0 bytes for IG16] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG15: mov w0, wzr cmp w21, #0 ble G_M000_IG20 ldr x22, [x19, #0x40] G_M000_IG16: mov x1, x22 ldr w2, [x19, #0x50] add w3, w2, #1 str w3, [x19, #0x50] ldrh w3, [x20, w0, UXTW #2] ldr w23, [x1, #0x08] cmp w2, w23 bhs G_M000_IG31 add x1, x1, #16 strh w3, [x1, w2, UXTW #2] add w0, w0, #1 cmp w0, w21 blt G_M000_IG16 G_M000_IG17: b G_M000_IG20 G_M000_IG18: mov x20, xzr mov w21, wzr b G_M000_IG04 G_M000_IG19: str xzr, [fp, #0x10] str xzr, [fp, #0x18] G_M000_IG20: ldr x20, [x19, #0x08] mov w21, wzr ldr w0, [x20, #0x08] cmp w0, #0 ble G_M000_IG23 G_M000_IG21: ldp w0, w1, [x19, #0x50] cmp w0, w1 beq G_M000_IG30 G_M000_IG22: ldr x0, [x19, #0x40] ldr w1, [x19, #0x50] mov w2, w1 add x3, x20, #16 ldrh w3, [x3, w21, UXTW #2] ldr w4, [x0, #0x08] cmp w2, w4 bhs G_M000_IG31 add x0, x0, #16 strh w3, [x0, w2, UXTW #2] add w0, w1, #1 str w0, [x19, #0x50] add w21, w21, #1 ldr w0, [x20, #0x08] cmp w0, w21 bgt G_M000_IG21 G_M000_IG23: ldrb w0, [x19, #0x58] cbnz w0, G_M000_IG26 G_M000_IG24: str xzr, [fp, #0x18] str xzr, [fp, #0x10] G_M000_IG25: ldp x25, x26, [sp, #0x50] ldp x23, x24, [sp, #0x40] ldp x21, x22, [sp, #0x30] ldp x19, x20, [sp, #0x20] ldp fp, lr, [sp], #0x60 ret lr G_M000_IG26: mov x0, x19 mov w1, #1 mov w2, wzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG24 G_M000_IG27: bl CORINFO_HELP_OVERFLOW G_M000_IG28: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 G_M000_IG29: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 brk_windows #0 G_M000_IG30: mov x0, x19 mov w1, wzr mov w2, wzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG22 G_M000_IG31: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 700 1138: JIT compiled System.IO.StreamWriter:WriteLine(System.String) [Tier1, IL size=20, code size=700] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:WorkloadActualStop(long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x2, [fp, #0x10] mov w1, #16 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 1139: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:WorkloadActualStop(long) [Tier0, IL size=10, code size=56] ; Assembly listing for method Perfolizer.Horology.StartedClock:GetElapsed():Perfolizer.Horology.ClockSpan:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x40]! stp x19, x20, [sp, #0x18] stp x21, x22, [sp, #0x28] str x23, [sp, #0x38] mov fp, sp mov x19, x0 mov x20, x8 G_M000_IG02: ldp x0, x21, [x19] movz x22, #0xD1FFAB1E movk x22, #0xD1FFAB1E LSL #16 movk x22, #0xD1FFAB1E LSL #32 mov x11, x22 ldr x1, [x11] blr x1 mov x23, x0 ldr x0, [x19] add x11, x22, #8 ldr x1, [x11] blr x1 stp x21, x23, [x20] str d0, [x20, #0x10] G_M000_IG03: ldr x23, [sp, #0x38] ldp x21, x22, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 104 1140: JIT compiled Perfolizer.Horology.StartedClock:GetElapsed() [Tier1, IL size=34, code size=104] ; Assembly listing for method Perfolizer.Horology.WindowsClock:get_Frequency():Perfolizer.Horology.Frequency:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr d0, [@RWD00] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr RWD00 dq 416312D000000000h ; 10000000 ; Total bytes of code 20 1141: JIT compiled Perfolizer.Horology.WindowsClock:get_Frequency() [Tier1, IL size=12, code size=20] ; Assembly listing for method Perfolizer.Horology.ClockSpan:.ctor(long,long,Perfolizer.Horology.Frequency):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: stp x1, x2, [x0] str d0, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 24 1142: JIT compiled Perfolizer.Horology.ClockSpan:.ctor(long,long,Perfolizer.Horology.Frequency) [Tier1, IL size=22, code size=24] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:IterationStop(int,int,long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 7 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! stp x19, x20, [sp, #0x10] mov fp, sp mov w19, w2 G_M000_IG02: cmp w19, #3 bhi G_M000_IG18 mov w2, w19 adr x4, [@RWD00] ldr w4, [x4, x2, LSL #2] adr x5, [G_M000_IG02] add x4, x4, x5 br x4 G_M000_IG03: cbnz w1, G_M000_IG05 mov x2, x3 mov w1, #4 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG04: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 br x3 G_M000_IG05: cmp w1, #1 bne G_M000_IG18 mov x2, x3 mov w1, #6 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG06: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 br x3 G_M000_IG07: cmp w1, #1 bne G_M000_IG18 mov x2, x3 mov w1, #8 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG08: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 br x3 G_M000_IG09: cbnz w1, G_M000_IG11 mov x2, x3 mov w1, #10 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG10: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 br x3 G_M000_IG11: cmp w1, #1 bne G_M000_IG18 mov x2, x3 mov w1, #14 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG12: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 br x3 G_M000_IG13: cbnz w1, G_M000_IG15 mov x2, x3 mov w1, #12 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG14: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 br x3 G_M000_IG15: cmp w1, #1 bne G_M000_IG18 mov x2, x3 mov w1, #16 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG16: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 br x3 G_M000_IG17: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG18: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x20, x0 str w19, [x20, #0x08] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov x1, x0 mov x2, x20 mov x0, x19 mov x3, xzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 mov x0, x19 bl CORINFO_HELP_THROW brk_windows #0 RWD00 dd G_M000_IG03 - G_M000_IG02 dd G_M000_IG07 - G_M000_IG02 dd G_M000_IG09 - G_M000_IG02 dd G_M000_IG13 - G_M000_IG02 ; Total bytes of code 468 1143: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:IterationStop(int,int,long) [Tier1, IL size=125, code size=468] ; Assembly listing for method System.Diagnostics.Tracing.ActivityTracker:OnStop(System.String,System.String,int,byref,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 5 inlinees with PGO data; 10 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x50]! stp x19, x20, [sp, #0x18] stp x21, x22, [sp, #0x28] stp x23, x24, [sp, #0x38] str x25, [sp, #0x48] mov fp, sp str xzr, [fp, #0x10] mov x19, x0 mov x20, x4 mov w21, w5 G_M000_IG02: ldr x0, [x19, #0x08] cbnz x0, G_M000_IG04 G_M000_IG03: ldr x25, [sp, #0x48] ldp x23, x24, [sp, #0x38] ldp x21, x22, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x50 ret lr G_M000_IG04: mov x0, x1 mov x1, x2 mov w2, w3 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x22, x0 tst w21, #255 bne G_M000_IG05 mov x21, xzr b G_M000_IG06 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x21, [x0] G_M000_IG06: cbz x21, G_M000_IG07 ldrb w0, [x21, #0xB1] b G_M000_IG08 G_M000_IG07: mov w0, wzr G_M000_IG08: uxtb w23, w0 cbz w23, G_M000_IG11 ldrsb wzr, [x21] mov x0, x21 mov x3, x22 mov w1, #23 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [x19, #0x08] ldrsb wzr, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x1, x0 cbz x0, G_M000_IG10 G_M000_IG09: ldr x2, [x0] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 cmp x2, x3 bne G_M000_IG36 G_M000_IG10: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x3, x0 mov x0, x21 mov w1, #23 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG11: ldr x24, [x19, #0x08] ldrsb wzr, [x24] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_GCTHREADSTATIC_BASE ldr x0, [x0, #0x18] cbz x0, G_M000_IG17 G_M000_IG12: ldr x2, [x0, #0x08] cbz x2, G_M000_IG16 G_M000_IG13: ldr x0, [x2, #0x08] ldr x2, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 cmp x2, x1 bne G_M000_IG26 G_M000_IG14: ldr x2, [x0, #0x08] cmp x24, x2 bne G_M000_IG19 G_M000_IG15: ldr x2, [x0, #0x10] str x2, [fp, #0x10] b G_M000_IG20 G_M000_IG16: mov x1, xzr b G_M000_IG21 G_M000_IG17: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 b G_M000_IG12 align [0 bytes for IG28] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG18: mov w2, #1 str w2, [x24, #0x34] b G_M000_IG29 G_M000_IG19: str xzr, [fp, #0x10] G_M000_IG20: ldr x1, [fp, #0x10] G_M000_IG21: str xzr, [fp, #0x10] mov x24, x1 cbnz x24, G_M000_IG25 G_M000_IG22: mov x25, xzr mov x0, x22 mov x1, x24 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz x0, G_M000_IG27 G_M000_IG23: stp xzr, xzr, [x20] cbz w23, G_M000_IG24 ldrsb wzr, [x21] mov x0, x21 mov w1, #23 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG24: ldr x25, [sp, #0x48] ldp x23, x24, [sp, #0x38] ldp x21, x22, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x50 ret lr G_M000_IG25: ldr x0, [x24] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 cmp x0, x2 bne G_M000_IG37 b G_M000_IG22 G_M000_IG26: add x2, fp, #16 mov x1, x24 movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x3, [x11] blr x3 b G_M000_IG20 G_M000_IG27: ldr q16, [x0, #0x38] str q16, [x20] b G_M000_IG30 G_M000_IG28: ldr w2, [x24, #0x34] cbnz w2, G_M000_IG29 ldr w2, [x24, #0x30] tbz w2, #3, G_M000_IG18 cbnz x25, G_M000_IG29 mov x25, x24 G_M000_IG29: ldr x24, [x24, #0x10] G_M000_IG30: cmp x24, x0 beq G_M000_IG32 G_M000_IG31: cbnz x24, G_M000_IG28 G_M000_IG32: add x2, x0, #52 mov w1, #1 mov w3, wzr casal w3, w1, [x2] cbnz w3, G_M000_IG11 G_M000_IG33: cbnz x25, G_M000_IG34 ldr x25, [x0, #0x10] G_M000_IG34: ldr x0, [x19, #0x08] ldr x2, [x0, #0x08] cmp x2, #0 cset x2, ne mov x1, x25 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 cbz w23, G_M000_IG35 mov x0, x25 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x3, x0 ldrsb wzr, [x21] mov x0, x21 mov w1, #23 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 mov x0, x20 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 mov x2, xzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x3, x0 mov x0, x21 mov w1, #23 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG35: ldr x25, [sp, #0x48] ldp x23, x24, [sp, #0x38] ldp x21, x22, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x50 ret lr G_M000_IG36: mov x0, x3 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 brk_windows #0 G_M000_IG37: mov x0, x2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 brk_windows #0 ; Total bytes of code 1040 1144: JIT compiled System.Diagnostics.Tracing.ActivityTracker:OnStop(System.String,System.String,int,byref,bool) [Tier1, IL size=322, code size=1040] ; Assembly listing for method BenchmarkDotNet.Engines.IterationData:get_Index():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1145: JIT compiled BenchmarkDotNet.Engines.IterationData:get_Index() [Tier1, IL size=7, code size=20] ; Assembly listing for method Perfolizer.Horology.ClockSpan:GetNanoseconds():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] ldr x0, [x0, #0x18] scvtf d16, x0 fmul d0, d0, d16 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 64 1146: JIT compiled Perfolizer.Horology.ClockSpan:GetNanoseconds() [Tier1, IL size=19, code size=64] ; Assembly listing for method Perfolizer.Horology.ClockSpan:GetSeconds():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 1 inlinees with PGO data; 5 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldp x2, x1, [x0] sub x1, x1, x2 cmp x1, #0 csel x1, xzr, x1, le scvtf d0, x1 ldr d16, [x0, #0x10] fdiv d0, d0, d16 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 44 1147: JIT compiled Perfolizer.Horology.ClockSpan:GetSeconds() [Tier1, IL size=48, code size=44] ; Assembly listing for method Perfolizer.Horology.Frequency:op_Implicit(double):Perfolizer.Horology.Frequency ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 16 1148: JIT compiled Perfolizer.Horology.Frequency:op_Implicit(double) [Tier1, IL size=7, code size=16] ; Assembly listing for method Perfolizer.Horology.Frequency:op_Division(Perfolizer.Horology.Frequency,Perfolizer.Horology.Frequency):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 2 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: fdiv d0, d0, d1 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1149: JIT compiled Perfolizer.Horology.Frequency:op_Division(Perfolizer.Horology.Frequency,Perfolizer.Horology.Frequency) [Tier1, IL size=26, code size=20] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:.ctor(int,int,int,int,long,double):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: str x5, [x0, #0x10] str d0, [x0, #0x18] str w1, [x0, #0x08] stp w2, w3, [x0] str w4, [x0, #0x0C] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 36 1150: JIT compiled BenchmarkDotNet.Reports.Measurement:.ctor(int,int,int,int,long,double) [Tier1, IL size=46, code size=36] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:ToString():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 20 inlinees with PGO data; 27 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x40]! str d8, [sp, #0x18] stp x19, x20, [sp, #0x20] stp x21, x22, [sp, #0x30] mov fp, sp str xzr, [fp, #0x10] mov x19, x0 G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x20, x0 movn w0, #0xD1FFAB1E LSL #16 str w0, [x20, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, #16 bl CORINFO_HELP_NEWARR_1_VC add x14, x20, #8 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF ldr w21, [x19] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str w21, [x0, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x21, x0 ldr w22, [x19, #0x04] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str w22, [x0, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x1, x0 mov x0, x21 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 mov w1, #15 mov w2, #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 cbz x0, G_M000_IG04 G_M000_IG03: ldr w2, [x0, #0x08] add x1, x0, #12 mov x0, x20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG04: ldr w0, [x20, #0x18] ldr x1, [x20, #0x08] ldr w2, [x1, #0x08] cmp w2, w0 bls G_M000_IG16 G_M000_IG05: add x1, x1, #16 mov w2, #32 strh w2, [x1, w0, UXTW #2] ldr w0, [x20, #0x18] add w0, w0, #1 str w0, [x20, #0x18] G_M000_IG06: ldr w21, [x19, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x22, [x0] mov x0, x22 tbnz w21, #31, G_M000_IG12 G_M000_IG07: mov w0, w21 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG08: mov w1, #2 mov w2, #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 cbz x0, G_M000_IG10 G_M000_IG09: ldr w2, [x0, #0x08] add x1, x0, #12 mov x0, x20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG10: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 add x1, x1, #12 mov x0, x20 mov w2, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x21, [x19, #0x10] mov x0, x22 tbz x21, #63, G_M000_IG13 G_M000_IG11: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x2, [x0, #0x28] mov x0, x21 movn w1, #0 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG14 G_M000_IG12: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x2, [x0, #0x28] mov w0, w21 movn w1, #0 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG08 G_M000_IG13: mov x0, x21 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG14: cbz x0, G_M000_IG18 G_M000_IG15: b G_M000_IG17 G_M000_IG16: mov x0, x20 mov w1, #32 mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG06 G_M000_IG17: ldr w2, [x0, #0x08] add x1, x0, #12 mov x0, x20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG18: ldr w0, [x20, #0x18] ldr x1, [x20, #0x08] ldr w2, [x1, #0x08] cmp w2, w0 bls G_M000_IG28 G_M000_IG19: add x1, x1, #16 mov w2, #32 strh w2, [x1, w0, UXTW #2] ldr w0, [x20, #0x18] add w0, w0, #1 str w0, [x20, #0x18] G_M000_IG20: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 add x1, x1, #12 mov x0, x20 mov w2, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 add x21, x1, #12 mov x1, x21 mov x0, x20 mov w2, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr d8, [x19, #0x18] mov x0, x22 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x1, x0 fmov d0, d8 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz x0, G_M000_IG22 G_M000_IG21: ldr w2, [x0, #0x08] add x1, x0, #12 mov x0, x20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG22: ldr w0, [x20, #0x18] ldr x1, [x20, #0x08] ldr w2, [x1, #0x08] cmp w2, w0 bls G_M000_IG29 G_M000_IG23: add x1, x1, #16 mov w2, #32 strh w2, [x1, w0, UXTW #2] ldr w0, [x20, #0x18] add w0, w0, #1 str w0, [x20, #0x18] G_M000_IG24: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 add x1, x1, #12 mov x0, x20 mov w2, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x1, x21 mov x0, x20 mov w2, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr d0, [x19, #0x18] ldr x0, [x19, #0x10] scvtf d16, x0 fdiv d0, d0, d16 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x10] mov x2, x22 add x0, fp, #16 mov x1, xzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 mov x4, xzr movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz x0, G_M000_IG26 G_M000_IG25: ldr w2, [x0, #0x08] add x1, x0, #12 mov x0, x20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG26: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 add x1, x1, #12 mov x0, x20 mov w2, #3 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x20 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG27: ldp x21, x22, [sp, #0x30] ldp x19, x20, [sp, #0x20] ldr d8, [sp, #0x18] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG28: mov x0, x20 mov w1, #32 mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG20 G_M000_IG29: mov x0, x20 mov w1, #32 mov w2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG24 ; Total bytes of code 1372 1151: JIT compiled BenchmarkDotNet.Reports.Measurement:ToString() [Tier1, IL size=304, code size=1372] ; Assembly listing for method System.Text.StringBuilder:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! str x19, [sp, #0x18] mov fp, sp mov x19, x0 G_M000_IG02: movn w0, #0xD1FFAB1E LSL #16 str w0, [x19, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, #16 bl CORINFO_HELP_NEWARR_1_VC add x14, x19, #8 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 68 1152: JIT compiled System.Text.StringBuilder:.ctor() [Tier1, IL size=31, code size=68] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:get_IterationMode():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1153: JIT compiled BenchmarkDotNet.Reports.Measurement:get_IterationMode() [Tier1, IL size=7, code size=20] ; Assembly listing for method System.String:Concat(System.String,System.String):System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 88757 ; 7 inlinees with PGO data; 2 single block inlinees; 2 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x40]! stp x19, x20, [sp, #0x10] stp x21, x22, [sp, #0x20] stp x23, x24, [sp, #0x30] mov fp, sp mov x20, x0 mov x19, x1 G_M000_IG02: cbz x20, G_M000_IG06 G_M000_IG03: ldr w21, [x20, #0x08] cbz w21, G_M000_IG06 G_M000_IG04: cbz x19, G_M000_IG10 G_M000_IG05: b G_M000_IG12 G_M000_IG06: cbz x19, G_M000_IG15 G_M000_IG07: ldr w22, [x19, #0x08] cbz w22, G_M000_IG15 G_M000_IG08: mov x0, x19 G_M000_IG09: ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG10: mov x0, x20 G_M000_IG11: ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG12: ldr w22, [x19, #0x08] cbz w22, G_M000_IG10 G_M000_IG13: mov w23, w21 add w0, w22, w23 bl System.String:FastAllocateString(int):System.String mov x24, x0 ldr w2, [x24, #0x08] cmp w2, w21 blt G_M000_IG18 add x0, x24, #12 add x1, x20, #12 mov w2, w21 lsl x2, x2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr w2, [x24, #0x08] sub w2, w2, w23 cmp w2, w22 blt G_M000_IG17 add x2, x24, #12 sbfiz x0, x23, #1, #32 add x0, x2, x0 add x1, x19, #12 mov w2, w22 lsl x2, x2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x24 G_M000_IG14: ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG15: movz x0, #8 movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG16: ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG17: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x0, x19 bl CORINFO_HELP_THROW G_M000_IG18: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x0, x19 bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 396 1154: JIT compiled System.String:Concat(System.String,System.String) [Tier1 with Static PGO, IL size=73, code size=396] ; Assembly listing for method System.String:PadRight(int,ushort):System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; PGO data available, but IL did not match ; 1 inlinees with PGO data; 3 single block inlinees; 3 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x40]! stp x19, x20, [sp, #0x10] stp x21, x22, [sp, #0x20] stp x23, x24, [sp, #0x30] mov fp, sp mov x20, x0 mov w19, w1 mov w21, w2 G_M000_IG02: tbnz w19, #31, G_M000_IG07 ldr w22, [x20, #0x08] sub w23, w19, w22 cmp w23, #0 bgt G_M000_IG05 G_M000_IG03: mov x0, x20 G_M000_IG04: ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG05: mov w0, w19 bl System.String:FastAllocateString(int):System.String mov x19, x0 ldrsb wzr, [x19] add x24, x19, #12 mov x0, x24 add x1, x20, #12 sxtw x2, w22 lsl x20, x2, #1 mov x2, x20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x0, x24, x20 uxth w2, w21 mov w1, w23 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x19 G_M000_IG06: ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG07: mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov w1, w19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 brk_windows #0 ; Total bytes of code 240 1155: JIT compiled System.String:PadRight(int,ushort) [Tier1, IL size=83, code size=240] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:get_IterationIndex():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w0, [x0, #0x0C] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1156: JIT compiled BenchmarkDotNet.Reports.Measurement:get_IterationIndex() [Tier1, IL size=7, code size=20] ; Assembly listing for method System.Int32:ToString(System.IFormatProvider):System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 3 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! str x19, [sp, #0x18] mov fp, sp G_M000_IG02: ldr w19, [x0] tbnz w19, #31, G_M000_IG05 G_M000_IG03: mov w0, w19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] G_M000_IG04: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 br x1 G_M000_IG05: cbnz x1, G_M000_IG09 G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG07: ldr x2, [x0, #0x28] mov w0, w19 movn w1, #0 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG08: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 br x3 G_M000_IG09: mov x0, x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 b G_M000_IG07 ; Total bytes of code 144 1157: JIT compiled System.Int32:ToString(System.IFormatProvider) [Tier1, IL size=11, code size=144] ; Assembly listing for method System.Number:UInt32ToDecStr(uint):System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; PGO data available, but IL did not match G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: cmp w0, #0xD1FFAB1E bhs G_M000_IG05 G_M000_IG03: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] G_M000_IG04: ldp fp, lr, [sp], #0x10 br x1 G_M000_IG05: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] G_M000_IG06: ldp fp, lr, [sp], #0x10 br x1 ; Total bytes of code 64 1158: JIT compiled System.Number:UInt32ToDecStr(uint) [Tier1, IL size=22, code size=64] ; Assembly listing for method System.Number:UInt32ToDecStrForKnownSmallNumber(uint):System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] cmp w0, #0xD1FFAB1E bhs G_M000_IG07 add x1, x1, #16 ldr x1, [x1, w0, UXTW #3] cbnz x1, G_M000_IG05 G_M000_IG03: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] G_M000_IG04: ldp fp, lr, [sp], #0x10 br x1 G_M000_IG05: mov x0, x1 G_M000_IG06: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG07: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 88 1159: JIT compiled System.Number:UInt32ToDecStrForKnownSmallNumber(uint) [Tier1, IL size=18, code size=88] ; Assembly listing for method System.Int64:ToString(System.IFormatProvider):System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 2 inlinees with PGO data; 1 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! str x19, [sp, #0x18] mov fp, sp G_M000_IG02: ldr x19, [x0] tbz x19, #63, G_M000_IG08 G_M000_IG03: cbz x1, G_M000_IG05 G_M000_IG04: mov x0, x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 b G_M000_IG06 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG06: ldr x2, [x0, #0x28] mov x0, x19 movn w1, #0 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG07: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 br x3 G_M000_IG08: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] G_M000_IG09: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 br x1 ; Total bytes of code 144 1160: JIT compiled System.Int64:ToString(System.IFormatProvider) [Tier1, IL size=10, code size=144] ; Assembly listing for method System.Number:UInt64ToDecStr(ulong):System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; PGO data available, but IL did not match ; 1 inlinees with PGO data; 10 single block inlinees; 4 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! stp x19, x20, [sp, #0x20] mov fp, sp str xzr, [fp, #0x18] mov x19, x0 G_M000_IG02: cmp x19, #0xD1FFAB1E bhs G_M000_IG05 G_M000_IG03: mov w0, w19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldp x19, x20, [sp, #0x20] ldp fp, lr, [sp], #0x30 ret lr G_M000_IG05: orr x0, x19, #1 clz x0, x0 eor w0, w0, #63 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldrb w0, [x1, w0, SXTW #2] ubfiz x1, x0, #3, #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x1, [x1, x2] cmp x19, x1 cset x1, lo sub w20, w0, w1 mov w0, w20 bl System.String:FastAllocateString(int):System.String cbnz x0, G_M000_IG06 mov x1, xzr b G_M000_IG07 align [0 bytes for IG08] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG06: add x1, x0, #12 str x1, [fp, #0x18] ldr x1, [fp, #0x18] G_M000_IG07: sbfiz x2, x20, #1, #32 add x1, x1, x2 cmp x19, #10 blo G_M000_IG10 cmp x19, #100 blo G_M000_IG09 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] G_M000_IG08: sub x1, x1, #4 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 movk x3, #0xD1FFAB1E LSL #48 lsr x4, x19, #2 umulh x3, x4, x3 lsr x3, x3, #2 mov x4, #100 msub x4, x3, x4, x19 mov x19, x3 mov x3, x2 add x3, x3, #16 lsl w4, w4, #2 mov w4, w4 add x3, x3, x4 ldr w3, [x3] str w3, [x1] cmp x19, #100 bhs G_M000_IG08 G_M000_IG09: cmp x19, #10 blo G_M000_IG10 sub x1, x1, #4 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] add x2, x2, #16 lsl w3, w19, #2 mov w3, w3 add x2, x2, x3 ldr w2, [x2] str w2, [x1] b G_M000_IG11 G_M000_IG10: add x2, x19, #48 strh w2, [x1, #-0x02] G_M000_IG11: str xzr, [fp, #0x18] G_M000_IG12: ldp x19, x20, [sp, #0x20] ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 356 1161: JIT compiled System.Number:UInt64ToDecStr(ulong) [Tier1, IL size=71, code size=356] ; Assembly listing for method System.Number:UInt64ToDecChars[ushort](ulong,ulong):ulong ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 5 single block inlinees; 2 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: cmp x1, #10 blo G_M000_IG07 G_M000_IG03: cmp x1, #100 blo G_M000_IG05 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] align [0 bytes for IG04] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG04: sub x0, x0, #4 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 movk x3, #0xD1FFAB1E LSL #48 lsr x4, x1, #2 umulh x3, x4, x3 lsr x3, x3, #2 mov x4, #100 msub x4, x3, x4, x1 mov x1, x3 mov x3, x2 add x3, x3, #16 lsl w4, w4, #2 mov w4, w4 add x3, x3, x4 ldr w3, [x3] str w3, [x0] cmp x1, #100 bhs G_M000_IG04 G_M000_IG05: cmp x1, #10 blo G_M000_IG07 sub x0, x0, #4 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] add x2, x2, #16 lsl w1, w1, #2 mov w1, w1 add x1, x2, x1 ldr w1, [x1] str w1, [x0] G_M000_IG06: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG07: sub x0, x0, #2 add x1, x1, #48 strh w1, [x0] G_M000_IG08: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 200 1162: JIT compiled System.Number:UInt64ToDecChars[ushort](ulong,ulong) [Tier1, IL size=121, code size=200] ; Assembly listing for method System.Char:System.IUtfChar.CastFrom(ulong):ushort ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: uxth w0, w0 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1163: JIT compiled System.Char:System.IUtfChar.CastFrom(ulong) [Tier1, IL size=3, code size=20] ; Assembly listing for method System.Number+Grisu3:TryRunDouble(double,int,byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 78 ; 2 inlinees with PGO data; 10 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! stp x19, x20, [sp, #0xE8] stp x21, x22, [sp, #0xF8] str x23, [sp, #0xD1FFAB1E] mov fp, sp mov w20, w0 mov x19, x1 G_M000_IG02: mov x0, v0.d[0] tbnz x0, #63, G_M000_IG11 G_M000_IG03: cmn w20, #1 bne G_M000_IG09 G_M000_IG04: mov x0, v0.d[0] and x21, x0, #0xD1FFAB1E lsr x0, x0, #52 and w0, w0, #0xD1FFAB1E str w0, [fp, #0x98] ldr w0, [fp, #0x98] cbz w0, G_M000_IG12 orr x21, x21, #0xD1FFAB1E ldr w0, [fp, #0x98] sub w0, w0, #0xD1FFAB1E str w0, [fp, #0x98] G_M000_IG05: str x21, [fp, #0x90] add x0, fp, #144 add x3, fp, #176 add x2, fp, #192 mov w1, #52 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x90] ldr w1, [fp, #0x98] clz x2, x0 lsl x0, x0, x2 sub w1, w1, w2 str x0, [fp, #0xD0] str w1, [fp, #0xD8] add x21, x19, #16 mov x0, x21 ldr x20, [x0] ldr w22, [x0, #0x08] ldr w0, [fp, #0xD8] add w0, w0, #64 neg w1, w0 sub w0, w1, #60 sub w1, w1, #32 add x2, fp, #136 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 stp x0, x1, [fp, #0x78] add x0, fp, #208 add x1, fp, #120 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 stp x0, x1, [fp, #0x68] add x0, fp, #192 add x1, fp, #120 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 stp x0, x1, [fp, #0x58] add x0, fp, #176 add x1, fp, #120 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 stp x0, x1, [fp, #0x48] mov x3, x20 mov w4, w22 add x1, fp, #104 add x2, fp, #72 add x0, fp, #88 add x5, fp, #224 add x6, fp, #64 movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 ldr w1, [fp, #0x88] neg w1, w1 ldr w2, [fp, #0x40] add w20, w1, w2 G_M000_IG06: cbz w0, G_M000_IG08 G_M000_IG07: ldr w1, [fp, #0xE0] add w1, w1, w20 str w1, [x19, #0x04] ldr w1, [fp, #0xE0] ldr w2, [x21, #0x08] cmp w1, w2 bhs G_M000_IG14 ldr x1, [x21] ldr w2, [fp, #0xE0] strb wzr, [x1, w2, UXTW #2] ldr w1, [fp, #0xE0] str w1, [x19] G_M000_IG08: ldr x23, [sp, #0xD1FFAB1E] ldp x21, x22, [sp, #0xF8] ldp x19, x20, [sp, #0xE8] ldp fp, lr, [sp], #0xD1FFAB1E ret lr G_M000_IG09: mov x0, v0.d[0] and x22, x0, #0xD1FFAB1E lsr x0, x0, #52 and w23, w0, #0xD1FFAB1E cbz w23, G_M000_IG13 orr x22, x22, #0xD1FFAB1E sub w23, w23, #0xD1FFAB1E G_M000_IG10: clz x0, x22 lsl x1, x22, x0 sub w0, w23, w0 str x1, [fp, #0xA0] str w0, [fp, #0xA8] add x21, x19, #16 mov x0, x21 ldr x23, [x0] ldr w22, [x0, #0x08] ldr w0, [fp, #0xA8] add w0, w0, #64 neg w1, w0 sub w0, w1, #60 sub w1, w1, #32 add x2, fp, #56 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 stp x0, x1, [fp, #0x28] add x0, fp, #160 add x1, fp, #40 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 stp x0, x1, [fp, #0x18] mov x2, x23 mov w3, w22 add x5, fp, #16 add x0, fp, #24 add x4, fp, #224 mov w1, w20 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr w1, [fp, #0x38] neg w1, w1 ldr w2, [fp, #0x10] add w20, w1, w2 b G_M000_IG06 G_M000_IG11: fneg d0, d0 b G_M000_IG03 G_M000_IG12: movn w0, #0xD1FFAB1E str w0, [fp, #0x98] b G_M000_IG05 G_M000_IG13: movn w23, #0xD1FFAB1E b G_M000_IG10 G_M000_IG14: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 696 1164: JIT compiled System.Number+Grisu3:TryRunDouble(double,int,byref) [Tier1 with Static PGO, IL size=134, code size=696] ; Assembly listing for method System.Number+DiyFp:Normalize():System.Number+DiyFp:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp G_M000_IG02: ldr x1, [x0] clz x2, x1 lsl x1, x1, x2 ldr w0, [x0, #0x08] sub w0, w0, w2 str w0, [fp, #0x1C] mov x0, x1 ldr w1, [fp, #0x1C] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 48 1165: JIT compiled System.Number+DiyFp:Normalize() [Tier1, IL size=37, code size=48] ; Assembly listing for method System.Number+Grisu3:TryRunCounted(byref,int,System.Span`1[ubyte],byref,byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x70]! stp x19, x20, [sp, #0x40] stp x21, x22, [sp, #0x50] stp x23, x24, [sp, #0x60] mov fp, sp mov x19, x0 mov w22, w1 mov x23, x2 mov w24, w3 mov x20, x4 mov x21, x5 G_M000_IG02: ldr w0, [x19, #0x08] add w0, w0, #64 neg w1, w0 sub w0, w1, #60 sub w1, w1, #32 add x2, fp, #40 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 stp x0, x1, [fp, #0x30] add x1, fp, #48 mov x0, x19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 stp x0, x1, [fp, #0x18] mov x2, x23 mov w3, w24 add x5, fp, #16 add x0, fp, #24 mov w1, w22 mov x4, x20 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr w1, [fp, #0x28] neg w1, w1 ldr w2, [fp, #0x10] add w1, w1, w2 str w1, [x21] G_M000_IG03: ldp x23, x24, [sp, #0x60] ldp x21, x22, [sp, #0x50] ldp x19, x20, [sp, #0x40] ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 208 1166: JIT compiled System.Number+Grisu3:TryRunCounted(byref,int,System.Span`1[ubyte],byref,byref) [Tier1, IL size=71, code size=208] ; Assembly listing for method System.Number+Grisu3:GetCachedPowerForBinaryExponentRange(int,int,byref):System.Number+DiyFp ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 4 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: add w0, w0, #63 scvtf d16, w0 ldr d17, [@RWD00] fmul d16, d16, d17 frintp d16, d16 fcvtzs w0, d16 add w0, w0, #0xD1FFAB1E asr w1, w0, #31 and w1, w1, #7 add w0, w1, w0 asr w0, w0, #3 add w0, w0, #1 cmp w0, #87 bhs G_M000_IG04 mov w0, w0 lsl x1, x0, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldrsh w3, [x1, x3] str w3, [x2] lsl x0, x0, #3 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x0, [x2, x0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldrsh w1, [x1, x2] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG04: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 RWD00 dq 3FD34413509F79FFh ; 0.301029996 ; Total bytes of code 144 1167: JIT compiled System.Number+Grisu3:GetCachedPowerForBinaryExponentRange(int,int,byref) [Tier1, IL size=91, code size=144] ; Assembly listing for method System.Number+DiyFp:Multiply(byref):System.Number+DiyFp:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr x2, [x0] lsr x2, x2, #32 ldr w3, [x0] ldr x4, [x1] lsr x4, x4, #32 ldr w5, [x1] mov w2, w2 mov w4, w4 mul x6, x2, x4 mov w3, w3 mul x4, x3, x4 mov w5, w5 mul x2, x2, x5 mul x3, x3, x5 lsr x3, x3, #32 add x3, x3, w2, UXTW add x3, x3, w4, UXTW mov x5, #0xD1FFAB1E add x3, x3, x5 ldr w0, [x0, #0x08] ldr w1, [x1, #0x08] add w0, w0, w1 add w1, w0, #64 add x0, x6, x2, LSR #32 add x0, x0, x4, LSR #32 add x0, x0, x3, LSR #32 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 120 1168: JIT compiled System.Number+DiyFp:Multiply(byref) [Tier1, IL size=136, code size=120] ; Assembly listing for method System.Number+Grisu3:TryDigitGenCounted(byref,int,System.Span`1[ubyte],byref,byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 4 ; 0 inlinees with PGO data; 4 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x70]! stp x19, x20, [sp, #0x20] stp x21, x22, [sp, #0x30] stp x23, x24, [sp, #0x40] stp x25, x26, [sp, #0x50] stp x27, x28, [sp, #0x60] mov fp, sp str x2, [fp, #0x10] str w3, [fp, #0x1C] mov w19, w1 mov x20, x4 mov x21, x5 G_M000_IG02: mov x22, #1 ldr w1, [x0, #0x08] neg w2, w1 and w23, w2, #63 mov x2, #1 lsl x24, x2, x23 ldr x0, [x0] lsr x25, x0, x23 sub x2, x24, #1 and x26, x0, x2 cbnz x26, G_M000_IG05 cmp w19, #11 blt G_M000_IG16 G_M000_IG03: str wzr, [x20] str wzr, [x21] mov w0, wzr G_M000_IG04: ldp x27, x28, [sp, #0x60] ldp x25, x26, [sp, #0x50] ldp x23, x24, [sp, #0x40] ldp x21, x22, [sp, #0x30] ldp x19, x20, [sp, #0x20] ldp fp, lr, [sp], #0x70 ret lr G_M000_IG05: neg w1, w1 neg w1, w1 add w1, w1, #64 mov w0, w25 mov x2, x21 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str wzr, [x20] b G_M000_IG07 G_M000_IG06: cmp w0, #0 beq G_M000_IG15 udiv w3, w25, w0 msub w25, w3, w0, w25 ldr w4, [x20] ldr w27, [fp, #0x1C] cmp w4, w27 bhs G_M000_IG17 add w3, w3, #48 ldr x28, [fp, #0x10] strb w3, [x28, w4, UXTW #2] ldr w3, [x20] add w3, w3, #1 str w3, [x20] sub w19, w19, #1 ldr w3, [x21] sub w3, w3, #1 str w3, [x21] cbz w19, G_M000_IG08 movz w3, #0xD1FFAB1E movk w3, #0xD1FFAB1E LSL #16 umull x0, w0, w3 lsr x0, x0, #35 str x28, [fp, #0x10] str w27, [fp, #0x1C] G_M000_IG07: ldr w3, [x21] cmp w3, #0 bgt G_M000_IG06 ldr w27, [fp, #0x1C] ldr x28, [fp, #0x10] G_M000_IG08: cbnz w19, G_M000_IG11 mov w3, w25 lsl x3, x3, x23 add x3, x3, x26 mov w4, w0 lsl x4, x4, x23 mov x0, x28 mov w1, w27 ldr w2, [x20] mov x5, #1 mov x6, x21 movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 G_M000_IG09: ldp x27, x28, [sp, #0x60] ldp x25, x26, [sp, #0x50] ldp x23, x24, [sp, #0x40] ldp x21, x22, [sp, #0x30] ldp x19, x20, [sp, #0x20] ldp fp, lr, [sp], #0x70 ret lr G_M000_IG10: mov x0, #10 mul x26, x26, x0 mul x22, x22, x0 lsr x0, x26, x23 ldr w1, [x20] cmp w1, w27 bhs G_M000_IG17 add w0, w0, #48 strb w0, [x28, w1, UXTW #2] ldr w0, [x20] add w0, w0, #1 str w0, [x20] sub w19, w19, #1 ldr w0, [x21] sub w0, w0, #1 str w0, [x21] sub x0, x24, #1 and x26, x26, x0 G_M000_IG11: cmp x26, x22 ccmp w19, #0, nzc, hi bgt G_M000_IG10 cbz w19, G_M000_IG13 cmp w27, #0 bls G_M000_IG17 strb wzr, [x28] str wzr, [x20] str wzr, [x21] mov w0, wzr G_M000_IG12: ldp x27, x28, [sp, #0x60] ldp x25, x26, [sp, #0x50] ldp x23, x24, [sp, #0x40] ldp x21, x22, [sp, #0x30] ldp x19, x20, [sp, #0x20] ldp fp, lr, [sp], #0x70 ret lr G_M000_IG13: mov x0, x28 mov w1, w27 ldr w2, [x20] mov x3, x26 mov x4, x24 mov x5, x22 mov x6, x21 movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 G_M000_IG14: ldp x27, x28, [sp, #0x60] ldp x25, x26, [sp, #0x50] ldp x23, x24, [sp, #0x40] ldp x21, x22, [sp, #0x30] ldp x19, x20, [sp, #0x20] ldp fp, lr, [sp], #0x70 ret lr G_M000_IG15: bl CORINFO_HELP_THROWDIVZERO G_M000_IG16: sub w0, w19, #1 cmp w0, #10 bhs G_M000_IG17 sub w0, w19, #1 ubfiz x0, x0, #2, #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr w0, [x0, x2] cmp w25, w0 bhs G_M000_IG05 b G_M000_IG03 G_M000_IG17: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 676 1169: JIT compiled System.Number+Grisu3:TryDigitGenCounted(byref,int,System.Span`1[ubyte],byref,byref) [Tier1 with Static PGO, IL size=372, code size=676] ; Assembly listing for method System.Number:FindSection(System.ReadOnlySpan`1[ushort],int):int ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: cbnz w2, G_M000_IG05 G_M000_IG03: mov w0, wzr G_M000_IG04: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG05: str x0, [fp, #0x18] mov w3, wzr align [0 bytes for IG06] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG06: cmp w3, w1 bge G_M000_IG20 add w4, w3, #1 ldrh w3, [x0, w3, SXTW #2] mov w5, w3 cmp w3, #34 bhi G_M000_IG07 cbz w3, G_M000_IG22 cmp w3, #34 beq G_M000_IG10 mov w3, w4 b G_M000_IG06 G_M000_IG07: cmp w3, #39 beq G_M000_IG10 cmp w5, #59 beq G_M000_IG17 cmp w5, #92 mov w3, w4 bne G_M000_IG06 G_M000_IG08: cmp w3, w1 bge G_M000_IG06 G_M000_IG09: b G_M000_IG15 G_M000_IG10: cmp w4, w1 bge G_M000_IG14 mov w5, w3 mov w3, w4 mov w4, w5 ldrh w5, [x0, w3, SXTW #2] cbz w5, G_M000_IG06 G_M000_IG11: add w3, w3, #1 cmp w5, w4 bne G_M000_IG13 G_M000_IG12: mov w4, w3 mov w3, w4 b G_M000_IG06 G_M000_IG13: mov w5, w3 mov w3, w4 mov w4, w5 b G_M000_IG10 G_M000_IG14: mov w3, w4 b G_M000_IG06 G_M000_IG15: ldrh w4, [x0, w3, SXTW #2] cbz w4, G_M000_IG06 G_M000_IG16: add w3, w3, #1 b G_M000_IG06 G_M000_IG17: sub w2, w2, #1 mov w3, w4 cbnz w2, G_M000_IG06 G_M000_IG18: cmp w3, w1 bge G_M000_IG22 ldrh w4, [x0, w3, SXTW #2] cbz w4, G_M000_IG22 cmp w4, #59 beq G_M000_IG22 mov w0, w3 G_M000_IG19: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG20: mov w0, wzr G_M000_IG21: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG22: mov w0, wzr G_M000_IG23: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 288 1170: JIT compiled System.Number:FindSection(System.ReadOnlySpan`1[ushort],int) [Tier1, IL size=190, code size=288] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:GetAverageTime():Perfolizer.Horology.TimeInterval:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 2 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr d0, [x0, #0x18] ldr x0, [x0, #0x10] scvtf d16, x0 fdiv d0, d0, d16 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x10 br x0 ; Total bytes of code 48 1171: JIT compiled BenchmarkDotNet.Reports.Measurement:GetAverageTime() [Tier1, IL size=20, code size=48] ; Assembly listing for method Perfolizer.Horology.TimeInterval:FromNanoseconds(double):Perfolizer.Horology.TimeInterval ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 3 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 16 1172: JIT compiled Perfolizer.Horology.TimeInterval:FromNanoseconds(double) [Tier1, IL size=12, code size=16] ; Assembly listing for method Perfolizer.Horology.TimeInterval:op_Multiply(Perfolizer.Horology.TimeInterval,double):Perfolizer.Horology.TimeInterval ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 2 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: fmul d0, d0, d1 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1173: JIT compiled Perfolizer.Horology.TimeInterval:op_Multiply(Perfolizer.Horology.TimeInterval,double) [Tier1, IL size=15, code size=20] ; Assembly listing for method Perfolizer.Horology.TimeInterval:.ctor(double):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: str d0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1174: JIT compiled Perfolizer.Horology.TimeInterval:.ctor(double) [Tier1, IL size=8, code size=20] ; Assembly listing for method Perfolizer.Horology.TimeInterval:ToString(System.Globalization.CultureInfo,System.String,Perfolizer.Common.UnitPresentation):System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp mov x5, x2 G_M000_IG02: mov x4, x3 mov x2, x1 mov x3, x5 mov x1, xzr movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] G_M000_IG03: ldp fp, lr, [sp], #0x10 br x5 ; Total bytes of code 52 1175: JIT compiled Perfolizer.Horology.TimeInterval:ToString(System.Globalization.CultureInfo,System.String,Perfolizer.Common.UnitPresentation) [Tier1, IL size=11, code size=52] ; Assembly listing for method Perfolizer.Horology.TimeInterval:ToString(Perfolizer.Horology.TimeUnit,System.Globalization.CultureInfo,System.String,Perfolizer.Common.UnitPresentation):System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 24 inlinees with PGO data; 13 single block inlinees; 5 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x70]! stp x19, x20, [sp, #0x38] stp x21, x22, [sp, #0x48] stp x23, x24, [sp, #0x58] str x25, [sp, #0x68] mov fp, sp mov x23, x0 mov x20, x1 mov x19, x2 mov x22, x3 mov x21, x4 G_M000_IG02: cbnz x20, G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, #1 bl CORINFO_HELP_NEWARR_1_VC ldr d16, [x23] str d16, [x0, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x20, x0 G_M000_IG04: cbnz x19, G_M000_IG06 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x19, [x0] G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 cmp x22, #0 csel x22, x22, x0, ne movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] cmp x21, #0 csel x21, x21, x0, ne ldr d0, [x23] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] mov x1, x20 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str d0, [fp, #0x30] ldrb w0, [x21, #0x0C] cbz w0, G_M000_IG16 G_M000_IG07: ldr x0, [x20, #0x08] ldr w1, [x21, #0x08] ldrsb wzr, [x0] mov w2, #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x20, x0 ldr d0, [fp, #0x30] str d0, [fp, #0x28] cbz x19, G_M000_IG15 G_M000_IG08: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] G_M000_IG09: ldr d0, [fp, #0x28] mov x0, x22 ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 mov x21, x0 cbz x21, G_M000_IG18 G_M000_IG10: ldr w23, [x21, #0x08] cbz w23, G_M000_IG18 G_M000_IG11: cbz x20, G_M000_IG20 G_M000_IG12: ldr w24, [x20, #0x08] cbz w24, G_M000_IG20 G_M000_IG13: add w0, w23, w24 add w0, w0, #1 bl System.String:FastAllocateString(int):System.String mov x19, x0 ldr w2, [x19, #0x08] cmp w2, w23 blt G_M000_IG32 add x0, x19, #12 add x1, x21, #12 mov w2, w23 lsl x2, x2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov w1, w23 ldr w0, [x19, #0x08] sub w0, w0, w1 cmp w0, #1 blt G_M000_IG33 add x0, x19, #12 sbfiz x1, x1, #1, #32 add x1, x0, x1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 add x0, x0, #12 ldrh w2, [x0] strh w2, [x1] add w1, w23, #1 mov x0, x19 mov x2, x20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x19 G_M000_IG14: ldr x25, [sp, #0x68] ldp x23, x24, [sp, #0x58] ldp x21, x22, [sp, #0x48] ldp x19, x20, [sp, #0x38] ldp fp, lr, [sp], #0x70 ret lr G_M000_IG15: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x18] b G_M000_IG09 G_M000_IG16: ldr d0, [fp, #0x30] str d0, [fp, #0x20] cbz x19, G_M000_IG26 G_M000_IG17: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] b G_M000_IG27 G_M000_IG18: cbnz x20, G_M000_IG23 G_M000_IG19: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 b G_M000_IG25 G_M000_IG20: mov w19, w23 add w0, w19, #1 bl System.String:FastAllocateString(int):System.String mov x22, x0 ldr w20, [x22, #0x08] cmp w23, w20 bgt G_M000_IG29 G_M000_IG21: add x24, x22, #12 mov x0, x24 add x1, x21, #12 mov w2, w23 lsl x2, x2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 sub w0, w20, w19 cmp w0, #0 ble G_M000_IG30 G_M000_IG22: sbfiz x0, x19, #1, #32 add x0, x24, x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 add x1, x1, #12 ldrh w2, [x1] strh w2, [x0] mov x0, x22 b G_M000_IG14 G_M000_IG23: ldr w24, [x20, #0x08] cbz w24, G_M000_IG19 G_M000_IG24: add w0, w24, #1 bl System.String:FastAllocateString(int):System.String mov x25, x0 ldr w0, [x25, #0x08] cmp w0, #1 blt G_M000_IG31 add x0, x25, #12 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 add x1, x1, #12 ldrh w2, [x1] strh w2, [x0] mov x0, x25 mov w1, #1 mov x2, x20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x25 G_M000_IG25: b G_M000_IG14 G_M000_IG26: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x10] G_M000_IG27: ldr d0, [fp, #0x20] mov x0, x22 ldr x1, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG28: ldr x25, [sp, #0x68] ldp x23, x24, [sp, #0x58] ldp x21, x22, [sp, #0x48] ldp x19, x20, [sp, #0x38] ldp fp, lr, [sp], #0x70 ret lr G_M000_IG29: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x0, x19 bl CORINFO_HELP_THROW G_M000_IG30: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x0, x19 bl CORINFO_HELP_THROW G_M000_IG31: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x0, x19 bl CORINFO_HELP_THROW G_M000_IG32: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x0, x19 bl CORINFO_HELP_THROW G_M000_IG33: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x0, x19 bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 1176 1176: JIT compiled Perfolizer.Horology.TimeInterval:ToString(Perfolizer.Horology.TimeUnit,System.Globalization.CultureInfo,System.String,Perfolizer.Common.UnitPresentation) [Tier1, IL size=141, code size=1176] ; Assembly listing for method Perfolizer.Horology.TimeUnit:GetBestTimeUnit(double[]):Perfolizer.Horology.TimeUnit ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 2 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: ldr w1, [x0, #0x08] cbnz w1, G_M000_IG05 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] G_M000_IG04: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG05: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] mov x2, x1 mov w0, wzr add x2, x2, #16 align [4 bytes for IG06] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG06: ldr x3, [x2, w0, UXTW #3] ldr x4, [x3, #0x18] mov x5, #0xD1FFAB1E mul x4, x4, x5 scvtf d16, x4 fcmp d0, d16 blo G_M000_IG09 add w0, w0, #1 cmp w0, #7 blt G_M000_IG06 G_M000_IG07: add x2, fp, #24 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldrb w1, [fp, #0x18] cbz w1, G_M000_IG11 G_M000_IG08: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG09: mov x0, x3 G_M000_IG10: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG11: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 ; Total bytes of code 224 1177: JIT compiled Perfolizer.Horology.TimeUnit:GetBestTimeUnit(double[]) [Tier1, IL size=71, code size=224] ; Assembly listing for method System.Linq.Enumerable:Min(System.Collections.Generic.IEnumerable`1[double]):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] G_M000_IG03: ldp fp, lr, [sp], #0x10 br x1 ; Total bytes of code 32 1178: JIT compiled System.Linq.Enumerable:Min(System.Collections.Generic.IEnumerable`1[double]) [Tier1, IL size=7, code size=32] ; Assembly listing for method System.Linq.Enumerable:MinFloat[double](System.Collections.Generic.IEnumerable`1[double]):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 9 single block inlinees; 2 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x40]! str d8, [sp, #0x30] str x19, [sp, #0x38] mov fp, sp add x1, sp, #64 str x1, [fp, #0x28] G_M000_IG02: cbz x0, G_M000_IG26 ldr x1, [x0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 cmp x1, x2 bne G_M000_IG03 add x2, x0, #16 ldr w3, [x0, #0x08] b G_M000_IG04 align [0 bytes for IG05] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG03: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 cmp x1, x2 bne G_M000_IG12 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x2, x0 mov w3, w1 G_M000_IG04: cbz w3, G_M000_IG27 ldr d8, [x2] mov w0, #1 cmp w3, #1 bls G_M000_IG09 G_M000_IG05: cmp w0, w3 bhs G_M000_IG28 ldr d0, [x2, w0, UXTW #3] fcmp d0, d8 bhs G_M000_IG07 G_M000_IG06: fmov d8, d0 b G_M000_IG08 G_M000_IG07: fcmp d0, d0 bne G_M000_IG11 G_M000_IG08: add w0, w0, #1 cmp w0, w3 blo G_M000_IG05 G_M000_IG09: mov v0.8b, v8.8b G_M000_IG10: ldr x19, [sp, #0x38] ldr d8, [sp, #0x30] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG11: ldr x19, [sp, #0x38] ldr d8, [sp, #0x30] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG12: movz x19, #0xD1FFAB1E movk x19, #0xD1FFAB1E LSL #16 movk x19, #0xD1FFAB1E LSL #32 mov x11, x19 ldr x1, [x11] blr x1 str x0, [fp, #0x18] G_M000_IG13: add x11, x19, #8 ldr x1, [x11] blr x1 cbz w0, G_M000_IG17 ldr x0, [fp, #0x18] add x11, x19, #16 ldr x1, [x11] blr x1 fmov d8, d0 fcmp d8, d8 beq G_M000_IG18 str d8, [fp, #0x20] b G_M000_IG20 G_M000_IG14: ldr x0, [fp, #0x18] add x11, x19, #32 ldr x1, [x11] blr x1 fcmp d0, d8 bhs G_M000_IG15 fmov d8, d0 b G_M000_IG18 G_M000_IG15: fcmp d0, d0 beq G_M000_IG18 G_M000_IG16: str d0, [fp, #0x20] b G_M000_IG20 G_M000_IG17: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 G_M000_IG18: ldr x0, [fp, #0x18] add x11, x19, #24 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG14 G_M000_IG19: ldr x0, [fp, #0x18] add x11, x19, #40 ldr x1, [x11] blr x1 b G_M000_IG24 G_M000_IG20: ldr x0, [fp, #0x28] bl G_M000_IG29 G_M000_IG21: nop G_M000_IG22: ldr d0, [fp, #0x20] G_M000_IG23: ldr x19, [sp, #0x38] ldr d8, [sp, #0x30] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG24: mov v0.8b, v8.8b G_M000_IG25: ldr x19, [sp, #0x38] ldr d8, [sp, #0x30] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG26: mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 brk_windows #0 G_M000_IG27: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 G_M000_IG28: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 G_M000_IG29: stp fp, lr, [sp, #-0x30]! str d8, [sp, #0x20] str x19, [sp, #0x28] add x3, fp, #64 str x3, [sp, #0x18] G_M000_IG30: ldr x0, [fp, #0x18] cbz x0, G_M000_IG31 movz x19, #0xD1FFAB1E movk x19, #0xD1FFAB1E LSL #16 movk x19, #0xD1FFAB1E LSL #32 add x11, x19, #40 ldr x1, [x11] blr x1 G_M000_IG31: ldr x19, [sp, #0x28] ldr d8, [sp, #0x20] ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 588 1179: JIT compiled System.Linq.Enumerable:MinFloat[double](System.Collections.Generic.IEnumerable`1[double]) [Tier1, IL size=235, code size=588] ; Assembly listing for method System.Linq.Enumerable:TryGetSpan[double](System.Collections.Generic.IEnumerable`1[double],byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 3 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! stp x19, x20, [sp, #0x10] mov fp, sp mov x19, x1 G_M000_IG02: cbz x0, G_M000_IG08 mov w20, #1 ldr x1, [x0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 cmp x1, x2 bne G_M000_IG04 G_M000_IG03: add x1, x0, #16 ldr w0, [x0, #0x08] str x1, [x19] str w0, [x19, #0x08] b G_M000_IG06 G_M000_IG04: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 cmp x1, x2 bne G_M000_IG05 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [x19] str w1, [x19, #0x08] b G_M000_IG06 G_M000_IG05: stp xzr, xzr, [x19] mov w20, wzr G_M000_IG06: mov w0, w20 G_M000_IG07: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG08: mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 brk_windows #0 ; Total bytes of code 172 1180: JIT compiled System.Linq.Enumerable:TryGetSpan[double](System.Collections.Generic.IEnumerable`1[double],byref) [Tier1, IL size=112, code size=172] ; Assembly listing for method System.ReadOnlySpan`1[double]:op_Implicit(double[]):System.ReadOnlySpan`1[double] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 0 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: cbnz x0, G_M000_IG04 G_M000_IG03: mov x0, xzr mov w1, wzr b G_M000_IG05 G_M000_IG04: add x1, x0, #16 ldr w0, [x0, #0x08] mov w2, w0 mov x0, x1 mov w1, w2 G_M000_IG05: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 52 1181: JIT compiled System.ReadOnlySpan`1[double]:op_Implicit(double[]) [Tier1, IL size=7, code size=52] ; Assembly listing for method System.ReadOnlySpan`1[double]:get_IsEmpty():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w0, [x0, #0x08] cmp w0, #0 cset x0, eq G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 28 1182: JIT compiled System.ReadOnlySpan`1[double]:get_IsEmpty() [Tier1, IL size=10, code size=28] ; Assembly listing for method Perfolizer.Horology.TimeUnit:Convert(double,Perfolizer.Horology.TimeUnit,Perfolizer.Horology.TimeUnit):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 2 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! str d8, [sp, #0x18] mov fp, sp G_M000_IG02: ldr x0, [x0, #0x18] scvtf d16, x0 str d0, [fp, #0x10] fmul d8, d0, d16 cbnz x1, G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, #1 bl CORINFO_HELP_NEWARR_1_VC ldr d0, [fp, #0x10] str d0, [x0, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x1, x0 G_M000_IG04: ldr x0, [x1, #0x18] scvtf d0, x0 fdiv d0, d8, d0 G_M000_IG05: ldr d8, [sp, #0x18] ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 108 1183: JIT compiled Perfolizer.Horology.TimeUnit:Convert(double,Perfolizer.Horology.TimeUnit,Perfolizer.Horology.TimeUnit) [Tier1, IL size=37, code size=108] ; Assembly listing for method Perfolizer.Common.UnitPresentation:get_IsVisible():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldrb w0, [x0, #0x0C] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1184: JIT compiled Perfolizer.Common.UnitPresentation:get_IsVisible() [Tier1, IL size=7, code size=20] ; Assembly listing for method Perfolizer.Horology.TimeUnit:get_Name():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1185: JIT compiled Perfolizer.Horology.TimeUnit:get_Name() [Tier1, IL size=7, code size=20] ; Assembly listing for method Perfolizer.Common.UnitPresentation:get_MinUnitWidth():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1186: JIT compiled Perfolizer.Common.UnitPresentation:get_MinUnitWidth() [Tier1, IL size=7, code size=20] ; Assembly listing for method System.String:PadLeft(int):System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov w2, #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG03: ldp fp, lr, [sp], #0x10 br x3 ; Total bytes of code 36 1187: JIT compiled System.String:PadLeft(int) [Tier1, IL size=10, code size=36] ; Assembly listing for method System.Number:NumberToString[ushort](byref,byref,ushort,int,System.Globalization.NumberFormatInfo) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 5 inlinees with PGO data; 29 single block inlinees; 11 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x60]! stp x19, x20, [sp, #0x10] stp x21, x22, [sp, #0x20] stp x23, x24, [sp, #0x30] stp x25, x26, [sp, #0x40] stp x27, x28, [sp, #0x50] mov fp, sp mov x21, x0 mov x20, x1 mov w23, w2 mov w19, w3 mov x22, x4 G_M000_IG02: ldrb w24, [x20, #0x0A] cmp w24, #3 cset x2, eq uxth w25, w23 cmp w25, #82 bhi G_M000_IG05 G_M000_IG03: sub w1, w25, #67 cmp w1, #4 bhi G_M000_IG04 mov w1, w1 adr x0, [@RWD00] ldr w0, [x0, x1, LSL #2] adr x3, [G_M000_IG02] add x0, x0, x3 br x0 G_M000_IG04: sub w26, w25, #78 cmp w26, #4 bhi G_M000_IG42 mov w1, w26 adr x0, [@RWD20] ldr w0, [x0, x1, LSL #2] adr x3, [G_M000_IG02] add x0, x0, x3 br x0 G_M000_IG05: sub w27, w25, #99 cmp w27, #4 bhi G_M000_IG06 mov w0, w27 adr x1, [@RWD40] ldr w1, [x1, x0, LSL #2] adr x3, [G_M000_IG02] add x1, x1, x3 br x1 G_M000_IG06: sub w28, w25, #110 cmp w28, #4 bhi G_M000_IG42 mov w0, w28 adr x1, [@RWD60] ldr w1, [x1, x0, LSL #2] adr x3, [G_M000_IG02] add x1, x1, x3 br x1 G_M000_IG07: tbz w19, #31, G_M000_IG08 ldr w19, [x22, #0xD1FFAB1E] G_M000_IG08: ldr w1, [x20, #0x04] add w1, w1, w19 mov x0, x20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x21 mov x1, x20 mov w2, w19 mov x3, x22 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 b G_M000_IG39 G_M000_IG09: tbz w19, #31, G_M000_IG10 ldr w19, [x22, #0xD1FFAB1E] G_M000_IG10: ldr w1, [x20, #0x04] add w1, w1, w19 mov x0, x20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldrb w1, [x20, #0x08] cbz w1, G_M000_IG15 ldr x1, [x22, #0x28] cbz x1, G_M000_IG13 G_M000_IG11: add x2, x1, #12 ldr w0, [x1, #0x08] G_M000_IG12: mov x1, x2 ldr w2, [x21, #0x08] add x3, x21, #16 ldr x4, [x3] ldr w3, [x3, #0x08] cmp w2, w3 ccmp w0, #1, 0, lo bne G_M000_IG14 ubfiz x0, x2, #1, #32 add x0, x4, x0 ldrh w1, [x1] strh w1, [x0] add w1, w2, #1 str w1, [x21, #0x08] b G_M000_IG15 G_M000_IG13: mov x2, xzr mov w0, wzr b G_M000_IG12 G_M000_IG14: mov w2, w0 mov x0, x21 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG15: ldr x4, [x22, #0x30] cbz x4, G_M000_IG18 G_M000_IG16: add x5, x4, #12 ldr w6, [x4, #0x08] G_M000_IG17: mov x4, x5 mov w5, w6 mov x6, xzr mov w7, wzr mov x0, x21 mov x1, x20 mov w2, w19 mov x3, xzr movz x8, #0xD1FFAB1E movk x8, #0xD1FFAB1E LSL #16 movk x8, #0xD1FFAB1E LSL #32 ldr x8, [x8] blr x8 b G_M000_IG39 G_M000_IG18: mov x5, xzr mov w6, wzr b G_M000_IG17 G_M000_IG19: tbz w19, #31, G_M000_IG20 ldr w19, [x22, #0xD1FFAB1E] G_M000_IG20: ldr w1, [x20, #0x04] add w1, w1, w19 mov x0, x20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x21 mov x1, x20 mov w2, w19 mov x3, x22 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 b G_M000_IG39 G_M000_IG21: mov w0, #6 cmp w19, #0 csel w19, w19, w0, ge add w19, w19, #1 mov x0, x20 mov w1, w19 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldrb w1, [x20, #0x08] cbz w1, G_M000_IG26 ldr x1, [x22, #0x28] cbz x1, G_M000_IG24 G_M000_IG22: add x2, x1, #12 ldr w0, [x1, #0x08] G_M000_IG23: mov x1, x2 ldr w2, [x21, #0x08] add x3, x21, #16 ldr x4, [x3] ldr w3, [x3, #0x08] cmp w2, w3 ccmp w0, #1, 0, lo bne G_M000_IG25 ubfiz x0, x2, #1, #32 add x0, x4, x0 ldrh w1, [x1] strh w1, [x0] add w1, w2, #1 str w1, [x21, #0x08] b G_M000_IG26 G_M000_IG24: mov x2, xzr mov w0, wzr b G_M000_IG23 G_M000_IG25: mov w2, w0 mov x0, x21 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG26: mov w4, w25 mov x0, x21 mov x1, x20 mov w2, w19 mov x3, x22 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 b G_M000_IG39 G_M000_IG27: mov w26, wzr cmp w19, #0 bgt G_M000_IG29 movn w0, #0 cmp w24, #2 ccmp w19, w0, 0, eq bne G_M000_IG28 mov w26, #1 add x0, x20, #16 ldr w1, [x0, #0x08] cmp w1, #0 bls G_M000_IG43 ldr x0, [x0] ldrb w0, [x0] cbnz w0, G_M000_IG30 b G_M000_IG35 G_M000_IG28: ldr w19, [x20] G_M000_IG29: mov x0, x20 mov w1, w19 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG30: ldrb w1, [x20, #0x08] cbz w1, G_M000_IG35 ldr x1, [x22, #0x28] cbz x1, G_M000_IG33 G_M000_IG31: add x2, x1, #12 ldr w0, [x1, #0x08] G_M000_IG32: mov x1, x2 ldr w2, [x21, #0x08] add x3, x21, #16 ldr x4, [x3] ldr w3, [x3, #0x08] cmp w2, w3 ccmp w0, #1, 0, lo bne G_M000_IG34 ubfiz x0, x2, #1, #32 add x0, x4, x0 ldrh w1, [x1] strh w1, [x0] add w1, w2, #1 str w1, [x21, #0x08] b G_M000_IG35 G_M000_IG33: mov x2, xzr mov w0, wzr b G_M000_IG32 G_M000_IG34: mov w2, w0 mov x0, x21 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG35: sub w4, w23, #2 uxth w4, w4 mov x0, x21 mov x1, x20 mov w2, w19 mov x3, x22 mov w5, w26 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 b G_M000_IG39 G_M000_IG36: tbz w19, #31, G_M000_IG37 ldr w19, [x22, #0xD1FFAB1E] G_M000_IG37: add x1, x20, #4 ldr w0, [x1] add w0, w0, #2 str w0, [x1] ldr w1, [x20, #0x04] add w1, w1, w19 mov x0, x20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x21 mov x1, x20 mov w2, w19 mov x3, x22 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 b G_M000_IG39 G_M000_IG38: sub w23, w25, #11 b G_M000_IG27 G_M000_IG39: ldp x27, x28, [sp, #0x50] ldp x25, x26, [sp, #0x40] ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x60 ret lr G_M000_IG40: bl CORINFO_HELP_THROWDIVZERO G_M000_IG41: bl CORINFO_HELP_OVERFLOW G_M000_IG42: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 G_M000_IG43: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 RWD00 dd G_M000_IG07 - G_M000_IG02 dd G_M000_IG42 - G_M000_IG02 dd G_M000_IG21 - G_M000_IG02 dd G_M000_IG09 - G_M000_IG02 dd G_M000_IG27 - G_M000_IG02 RWD20 dd G_M000_IG19 - G_M000_IG02 dd G_M000_IG42 - G_M000_IG02 dd G_M000_IG36 - G_M000_IG02 dd G_M000_IG42 - G_M000_IG02 dd G_M000_IG38 - G_M000_IG02 RWD40 dd G_M000_IG07 - G_M000_IG02 dd G_M000_IG42 - G_M000_IG02 dd G_M000_IG21 - G_M000_IG02 dd G_M000_IG09 - G_M000_IG02 dd G_M000_IG27 - G_M000_IG02 RWD60 dd G_M000_IG19 - G_M000_IG02 dd G_M000_IG42 - G_M000_IG02 dd G_M000_IG36 - G_M000_IG02 dd G_M000_IG42 - G_M000_IG02 dd G_M000_IG38 - G_M000_IG02 ; Total bytes of code 1280 1188: JIT compiled System.Number:NumberToString[ushort](byref,byref,ushort,int,System.Globalization.NumberFormatInfo) [Tier1, IL size=503, code size=1280] ; Assembly listing for method System.Number:FormatNumber[ushort](byref,byref,int,System.Globalization.NumberFormatInfo) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 3 inlinees with PGO data; 20 single block inlinees; 8 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x50]! stp x19, x20, [sp, #0x18] stp x21, x22, [sp, #0x28] stp x23, x24, [sp, #0x38] str x25, [sp, #0x48] mov fp, sp mov x19, x0 mov x21, x1 mov w22, w2 mov x20, x3 G_M000_IG02: ldrb w4, [x21, #0x08] cbnz w4, G_M000_IG04 G_M000_IG03: movz x23, #0xD1FFAB1E movk x23, #0xD1FFAB1E LSL #16 movk x23, #0xD1FFAB1E LSL #32 b G_M000_IG05 G_M000_IG04: movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] ldr w5, [x20, #0xD1FFAB1E] cmp w5, #5 bhs G_M000_IG27 add x4, x4, #16 ldr x23, [x4, w5, UXTW #3] G_M000_IG05: mov w24, wzr ldr w25, [x23, #0x08] cmp w25, #0 ble G_M000_IG24 G_M000_IG06: add x4, x23, #12 ldrh w1, [x4, w24, UXTW #2] cmp w1, #35 beq G_M000_IG08 G_M000_IG07: cmp w1, #45 beq G_M000_IG18 b G_M000_IG23 G_M000_IG08: ldr x3, [x20, #0x08] ldr x4, [x20, #0x30] cbz x4, G_M000_IG14 G_M000_IG09: add x5, x4, #12 ldr w6, [x4, #0x08] G_M000_IG10: mov x4, x5 mov w5, w6 ldr x6, [x20, #0x38] cbz x6, G_M000_IG13 G_M000_IG11: add x7, x6, #12 ldr w0, [x6, #0x08] G_M000_IG12: mov x6, x7 mov w7, w0 mov x0, x19 mov x1, x21 mov w2, w22 movz x8, #0xD1FFAB1E movk x8, #0xD1FFAB1E LSL #16 movk x8, #0xD1FFAB1E LSL #32 ldr x8, [x8] blr x8 b G_M000_IG16 G_M000_IG13: mov x7, xzr mov w0, wzr b G_M000_IG12 G_M000_IG14: mov x5, xzr mov w6, wzr b G_M000_IG10 G_M000_IG15: mov x0, x19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG16: add w24, w24, #1 cmp w25, w24 bgt G_M000_IG06 G_M000_IG17: b G_M000_IG24 G_M000_IG18: ldr x1, [x20, #0x28] cbz x1, G_M000_IG21 G_M000_IG19: add x2, x1, #12 ldr w0, [x1, #0x08] G_M000_IG20: mov x1, x2 ldr w2, [x19, #0x08] add x3, x19, #16 ldr x4, [x3] ldr w3, [x3, #0x08] cmp w2, w3 ccmp w0, #1, 0, lo bne G_M000_IG22 ubfiz x0, x2, #1, #32 add x0, x4, x0 ldrh w1, [x1] strh w1, [x0] add w1, w2, #1 str w1, [x19, #0x08] b G_M000_IG16 G_M000_IG21: mov x2, xzr mov w0, wzr b G_M000_IG20 G_M000_IG22: mov w2, w0 mov x0, x19 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 b G_M000_IG16 G_M000_IG23: ldr w0, [x19, #0x08] add x2, x19, #16 ldr x3, [x2] ldr w2, [x2, #0x08] cmp w0, w2 bhs G_M000_IG15 strh w1, [x3, w0, UXTW #2] add w0, w0, #1 str w0, [x19, #0x08] b G_M000_IG16 G_M000_IG24: ldr x25, [sp, #0x48] ldp x23, x24, [sp, #0x38] ldp x21, x22, [sp, #0x28] ldp x19, x20, [sp, #0x18] ldp fp, lr, [sp], #0x50 ret lr G_M000_IG25: bl CORINFO_HELP_THROWDIVZERO G_M000_IG26: bl CORINFO_HELP_OVERFLOW G_M000_IG27: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 496 1189: JIT compiled System.Number:FormatNumber[ushort](byref,byref,int,System.Globalization.NumberFormatInfo) [Tier1, IL size=128, code size=496] ; Assembly listing for method System.Globalization.NumberFormatInfo:NumberDecimalSeparatorTChar[ushort]():System.ReadOnlySpan`1[ushort]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 1 inlinees with PGO data; 6 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr x0, [x0, #0x30] cbz x0, G_M000_IG06 G_M000_IG03: add x2, x0, #12 ldr w1, [x0, #0x08] G_M000_IG04: mov x0, x2 G_M000_IG05: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG06: mov x2, xzr mov w1, wzr b G_M000_IG04 G_M000_IG07: bl CORINFO_HELP_THROWDIVZERO G_M000_IG08: bl CORINFO_HELP_OVERFLOW brk_windows #0 ; Total bytes of code 60 1190: JIT compiled System.Globalization.NumberFormatInfo:NumberDecimalSeparatorTChar[ushort]() [Tier1, IL size=95, code size=60] ; Assembly listing for method System.Globalization.NumberFormatInfo:NumberGroupSeparatorTChar[ushort]():System.ReadOnlySpan`1[ushort]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 1 inlinees with PGO data; 6 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr x0, [x0, #0x38] cbz x0, G_M000_IG06 G_M000_IG03: add x2, x0, #12 ldr w1, [x0, #0x08] G_M000_IG04: mov x0, x2 G_M000_IG05: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG06: mov x2, xzr mov w1, wzr b G_M000_IG04 G_M000_IG07: bl CORINFO_HELP_THROWDIVZERO G_M000_IG08: bl CORINFO_HELP_OVERFLOW brk_windows #0 ; Total bytes of code 60 1191: JIT compiled System.Globalization.NumberFormatInfo:NumberGroupSeparatorTChar[ushort]() [Tier1, IL size=95, code size=60] ; Assembly listing for method System.Number:FormatFixed[ushort](byref,byref,int,int[],System.ReadOnlySpan`1[ushort],System.ReadOnlySpan`1[ushort]) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 2 inlinees with PGO data; 9 single block inlinees; 6 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x90]! stp x19, x20, [sp, #0x40] stp x21, x22, [sp, #0x50] stp x23, x24, [sp, #0x60] stp x25, x26, [sp, #0x70] stp x27, x28, [sp, #0x80] mov fp, sp str xzr, [fp, #0x28] mov x19, x0 mov w21, w2 mov x23, x3 mov x24, x4 mov w25, w5 mov x22, x6 mov w20, w7 G_M000_IG02: ldr w26, [x1, #0x04] ldr x27, [x1, #0x10] cmp w26, #0 ble G_M000_IG32 G_M000_IG03: cbz x23, G_M000_IG24 mov w28, wzr mov w2, w26 mov w3, wzr ldr w4, [x23, #0x08] str w4, [fp, #0x24] cbz w4, G_M000_IG08 add x5, x23, #16 ldr w0, [x5] mov w6, w0 cmp w2, w6 ble G_M000_IG07 align [4 bytes for IG04] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG04: cmp w28, w4 bhs G_M000_IG53 ldr w3, [x5, w28, UXTW #2] cbz w3, G_M000_IG07 add w2, w2, w20 sub w3, w4, #1 cmp w3, w28 ble G_M000_IG06 G_M000_IG05: add w28, w28, #1 G_M000_IG06: cmp w28, w4 bhs G_M000_IG53 ldr w3, [x5, w28, UXTW #2] add w6, w3, w6 orr w3, w6, w2 tbnz w3, #31, G_M000_IG52 cmp w26, w6 ldr w4, [fp, #0x24] bgt G_M000_IG04 G_M000_IG07: cmp w6, #0 csel w3, wzr, w0, eq str w3, [fp, #0x38] ldr w3, [fp, #0x38] G_M000_IG08: mov w28, wzr str wzr, [fp, #0x34] ldr w0, [x1] cmp w26, w0 csel w7, w26, w0, lt str w7, [fp, #0x30] ldr w0, [x19, #0x08] add x8, x19, #16 str x8, [fp, #0x18] mov x1, x8 ldr x5, [x1] ldr w1, [x1, #0x08] mov w9, w0 add x10, x9, w2, UXTW mov w1, w1 cmp x10, x1 bhi G_M000_IG09 add w0, w0, w2 str w0, [x19, #0x08] lsl x0, x9, #1 add x5, x5, x0 b G_M000_IG10 G_M000_IG09: str w3, [fp, #0x38] mov x0, x19 str w2, [fp, #0x3C] mov w1, w2 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 mov x5, x0 ldp w3, w2, [fp, #0x38] ldr w4, [fp, #0x24] G_M000_IG10: str x5, [fp, #0x28] sbfiz x0, x2, #1, #32 add x0, x5, x0 sub x0, x0, #2 sub w1, w26, #1 tbnz w1, #31, G_M000_IG13 G_M000_IG11: sub x2, x0, #2 ldr w7, [fp, #0x30] cmp w1, w7 blt G_M000_IG14 G_M000_IG12: mov w5, #48 b G_M000_IG15 G_M000_IG13: ldr w7, [fp, #0x30] b G_M000_IG21 G_M000_IG14: ldrb w5, [x27, w1, SXTW #2] G_M000_IG15: strh w5, [x0] cmp w3, #0 ble G_M000_IG20 G_M000_IG16: ldr w6, [fp, #0x34] add w6, w6, #1 cmp w6, w3 bne G_M000_IG23 str w6, [fp, #0x34] cbz w1, G_M000_IG20 sub w6, w20, #1 tbnz w6, #31, G_M000_IG18 align [0 bytes for IG17] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG17: mov x0, x2 sub x2, x0, #2 cmp w6, w20 bhs G_M000_IG53 ldrh w5, [x22, w6, UXTW #2] strh w5, [x0] sub w6, w6, #1 tbz w6, #31, G_M000_IG17 G_M000_IG18: sub w0, w4, #1 cmp w0, w28 ble G_M000_IG19 add w28, w28, #1 cmp w28, w4 bhs G_M000_IG53 add x5, x23, #16 ldr w3, [x5, w28, UXTW #2] G_M000_IG19: mov w0, wzr str w0, [fp, #0x34] G_M000_IG20: sub w1, w1, #1 mov x0, x2 tbz w1, #31, G_M000_IG22 G_M000_IG21: add x27, x27, w7, SXTW str xzr, [fp, #0x28] b G_M000_IG34 G_M000_IG22: str w7, [fp, #0x30] b G_M000_IG11 G_M000_IG23: str w6, [fp, #0x34] b G_M000_IG20 G_M000_IG24: ldrb w8, [x27] cbnz w8, G_M000_IG26 G_M000_IG25: mov w0, #48 b G_M000_IG27 G_M000_IG26: add x0, x27, #1 mov x20, x0 ldrb w0, [x27] mov x27, x20 G_M000_IG27: uxth w1, w0 ldr w0, [x19, #0x08] add x8, x19, #16 mov x20, x8 mov x2, x20 ldr x3, [x2] ldr w2, [x2, #0x08] cmp w0, w2 bhs G_M000_IG29 G_M000_IG28: strh w1, [x3, w0, UXTW #2] add w0, w0, #1 str w0, [x19, #0x08] b G_M000_IG30 G_M000_IG29: mov x0, x19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG30: sub w26, w26, #1 cmp w26, #0 bgt G_M000_IG24 G_M000_IG31: str x20, [fp, #0x18] b G_M000_IG34 G_M000_IG32: ldr w0, [x19, #0x08] add x20, x19, #16 mov x1, x20 ldr x2, [x1] ldr w1, [x1, #0x08] cmp w0, w1 bhs G_M000_IG33 mov w1, #48 strh w1, [x2, w0, UXTW #2] add w0, w0, #1 str w0, [x19, #0x08] str x20, [fp, #0x18] b G_M000_IG34 G_M000_IG33: mov x0, x19 mov w1, #48 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x20, [fp, #0x18] G_M000_IG34: cmp w21, #0 ble G_M000_IG51 G_M000_IG35: mov x1, x24 mov w2, w25 ldr w0, [x19, #0x08] ldr x8, [fp, #0x18] mov x3, x8 ldr x4, [x3] ldr w3, [x3, #0x08] cmp w0, w3 ccmp w2, #1, 0, lo bne G_M000_IG36 ubfiz x2, x0, #1, #32 add x2, x4, x2 ldrh w1, [x1] strh w1, [x2] add w1, w0, #1 str w1, [x19, #0x08] b G_M000_IG37 G_M000_IG36: mov x0, x19 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG37: tbz w26, #31, G_M000_IG43 neg w0, w26 cmp w0, w21 csel w20, w0, w21, le mov w22, wzr cmp w20, #0 ble G_M000_IG42 G_M000_IG38: ldr w0, [x19, #0x08] ldr x8, [fp, #0x18] mov x1, x8 ldr x2, [x1] ldr w1, [x1, #0x08] cmp w0, w1 bhs G_M000_IG40 G_M000_IG39: mov w1, #48 strh w1, [x2, w0, UXTW #2] add w0, w0, #1 str w0, [x19, #0x08] b G_M000_IG41 G_M000_IG40: mov x0, x19 mov w1, #48 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG41: add w22, w22, #1 cmp w22, w20 blt G_M000_IG38 G_M000_IG42: sub w21, w21, w20 G_M000_IG43: cmp w21, #0 ble G_M000_IG51 G_M000_IG44: ldrb w0, [x27] cbnz w0, G_M000_IG46 G_M000_IG45: mov w0, #48 b G_M000_IG47 G_M000_IG46: mov x0, x27 add x27, x0, #1 ldrb w0, [x0] G_M000_IG47: uxth w1, w0 ldr w0, [x19, #0x08] ldr x8, [fp, #0x18] mov x2, x8 ldr x3, [x2] ldr w2, [x2, #0x08] cmp w0, w2 bhs G_M000_IG49 G_M000_IG48: strh w1, [x3, w0, UXTW #2] add w0, w0, #1 str w0, [x19, #0x08] b G_M000_IG50 G_M000_IG49: mov x0, x19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG50: sub w21, w21, #1 cmp w21, #0 bgt G_M000_IG44 G_M000_IG51: ldp x27, x28, [sp, #0x80] ldp x25, x26, [sp, #0x70] ldp x23, x24, [sp, #0x60] ldp x21, x22, [sp, #0x50] ldp x19, x20, [sp, #0x40] ldp fp, lr, [sp], #0x90 ret lr G_M000_IG52: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 G_M000_IG53: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 1180 1192: JIT compiled System.Number:FormatFixed[ushort](byref,byref,int,int[],System.ReadOnlySpan`1[ushort],System.ReadOnlySpan`1[ushort]) [Tier1, IL size=542, code size=1180] ; Assembly listing for method System.Number+NumberBuffer:GetDigitsPointer():ulong:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr x0, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1193: JIT compiled System.Number+NumberBuffer:GetDigitsPointer() [Tier1, IL size=17, code size=20] ; Assembly listing for method System.Collections.Generic.ValueListBuilder`1[ushort]:Append(System.ReadOnlySpan`1[ushort]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w3, [x0, #0x08] add x4, x0, #16 ldr x5, [x4] ldr w4, [x4, #0x08] cmp w3, w4 ccmp w2, #1, 0, lo bne G_M000_IG05 G_M000_IG03: ubfiz x2, x3, #1, #32 add x2, x5, x2 ldrh w1, [x1] strh w1, [x2] add w1, w3, #1 str w1, [x0, #0x08] G_M000_IG04: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG05: movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG06: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 96 1194: JIT compiled System.Collections.Generic.ValueListBuilder`1[ushort]:Append(System.ReadOnlySpan`1[ushort]) [Tier1, IL size=78, code size=96] ; Assembly listing for method System.String:Concat(System.String,System.String,System.String):System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 102020 ; 9 inlinees with PGO data; 3 single block inlinees; 3 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x60]! stp x19, x20, [sp, #0x10] stp x21, x22, [sp, #0x20] stp x23, x24, [sp, #0x30] stp x25, x26, [sp, #0x40] stp x27, x28, [sp, #0x50] mov fp, sp mov x19, x0 mov x20, x1 mov x21, x2 G_M000_IG02: cbz x19, G_M000_IG06 G_M000_IG03: ldr w22, [x19, #0x08] cbz w22, G_M000_IG06 G_M000_IG04: cbz x20, G_M000_IG08 G_M000_IG05: b G_M000_IG10 G_M000_IG06: mov x0, x20 mov x1, x21 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] G_M000_IG07: ldp x27, x28, [sp, #0x50] ldp x25, x26, [sp, #0x40] ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x60 br x2 G_M000_IG08: mov x0, x19 mov x1, x21 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] G_M000_IG09: ldp x27, x28, [sp, #0x50] ldp x25, x26, [sp, #0x40] ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x60 br x2 G_M000_IG10: ldr w23, [x20, #0x08] cbz w23, G_M000_IG08 G_M000_IG11: cbz x21, G_M000_IG15 G_M000_IG12: ldr w24, [x21, #0x08] cbz w24, G_M000_IG15 G_M000_IG13: add w25, w23, w22 add w0, w25, w24 bl System.String:FastAllocateString(int):System.String mov x26, x0 ldr w27, [x26, #0x08] cmp w27, w22 blt G_M000_IG17 add x28, x26, #12 mov x0, x28 add x1, x19, #12 mov w2, w22 lsl x2, x2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 sub w2, w27, w22 cmp w2, w23 blt G_M000_IG18 sbfiz x2, x22, #1, #32 add x0, x28, x2 add x1, x20, #12 mov w2, w23 lsl x2, x2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 sub w2, w27, w25 cmp w2, w24 blt G_M000_IG19 sbfiz x2, x25, #1, #32 add x0, x28, x2 add x1, x21, #12 mov w2, w24 lsl x2, x2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x26 G_M000_IG14: ldp x27, x28, [sp, #0x50] ldp x25, x26, [sp, #0x40] ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x60 ret lr G_M000_IG15: mov x0, x19 mov x1, x20 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] G_M000_IG16: ldp x27, x28, [sp, #0x50] ldp x25, x26, [sp, #0x40] ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x60 br x2 G_M000_IG17: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x0, x19 bl CORINFO_HELP_THROW G_M000_IG18: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x0, x19 bl CORINFO_HELP_THROW G_M000_IG19: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x0, x19 bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 588 1195: JIT compiled System.String:Concat(System.String,System.String,System.String) [Tier1 with Static PGO, IL size=119, code size=588] ; Assembly listing for method BenchmarkDotNet.Helpers.AsciiHelper:ToAscii(System.String):System.String ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: cbnz x0, G_M000_IG05 G_M000_IG03: mov x0, xzr G_M000_IG04: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG05: movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG06: ldp fp, lr, [sp], #0x10 br x3 ; Total bytes of code 72 1196: JIT compiled BenchmarkDotNet.Helpers.AsciiHelper:ToAscii(System.String) [Tier1, IL size=22, code size=72] ; Assembly listing for method System.String:Replace(System.String,System.String):System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 4 inlinees with PGO data; 9 single block inlinees; 3 inlinees without PGO data G_M000_IG01: sub sp, sp, #112 stp x19, x20, [sp, #0x28] stp x21, x22, [sp, #0x38] stp x23, x24, [sp, #0x48] str x25, [sp, #0x58] stp fp, lr, [sp, #0x60] add fp, sp, #96 str xzr, [fp, #-0x58] str xzr, [fp, #-0x48] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 str x3, [fp, #-0x60] mov x19, x0 mov x20, x1 mov x21, x2 G_M000_IG02: cbz x20, G_M000_IG22 G_M000_IG03: ldr w22, [x20, #0x08] cbz w22, G_M000_IG22 G_M000_IG04: movz x1, #8 movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 cmp x21, #0 csel x21, x21, x1, ne ldp x1, xzr, [sp], #0xD1FFAB1E mov x1, sp str x1, [fp, #-0x48] mov w1, #128 str w1, [fp, #-0x40] str xzr, [fp, #-0x58] str wzr, [fp, #-0x50] cmp w22, #1 bne G_M000_IG12 G_M000_IG05: ldr w1, [x21, #0x08] cmp w1, #1 bne G_M000_IG07 ldrh w1, [x20, #0x0C] ldrh w2, [x21, #0x0C] mov x0, x19 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #-0x60] cmp xip0, xip1 beq G_M000_IG06 bl CORINFO_HELP_FAIL_FAST G_M000_IG06: sub sp, fp, #96 ldp fp, lr, [sp, #0x60] ldr x25, [sp, #0x58] ldp x23, x24, [sp, #0x48] ldp x21, x22, [sp, #0x38] ldp x19, x20, [sp, #0x28] add sp, sp, #112 ret lr G_M000_IG07: ldrh w20, [x20, #0x0C] mov w23, wzr add x24, x19, #12 G_M000_IG08: sbfiz x0, x23, #1, #32 add x0, x24, x0 ldr w25, [x19, #0x08] sub w2, w25, w23 sxth w1, w20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 tbnz w0, #31, G_M000_IG17 add w23, w23, w0 mov w1, w23 ldr w0, [fp, #-0x50] ldr x2, [fp, #-0x48] ldr w3, [fp, #-0x40] cmp w0, w3 bhs G_M000_IG10 G_M000_IG09: str w1, [x2, w0, UXTW #2] add w0, w0, #1 str w0, [fp, #-0x50] b G_M000_IG11 G_M000_IG10: sub x0, fp, #88 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG11: add w23, w23, #1 b G_M000_IG08 G_M000_IG12: mov w23, wzr add x24, x19, #12 ldr w25, [x19, #0x08] G_M000_IG13: sbfiz x0, x23, #1, #32 add x0, x24, x0 sub w1, w25, w23 add x2, x20, #12 mov w3, w22 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 tbnz w0, #31, G_M000_IG17 add w23, w23, w0 mov w1, w23 ldr w0, [fp, #-0x50] ldr x2, [fp, #-0x48] ldr w3, [fp, #-0x40] cmp w0, w3 bhs G_M000_IG15 G_M000_IG14: str w1, [x2, w0, UXTW #2] add w0, w0, #1 str w0, [fp, #-0x50] b G_M000_IG16 G_M000_IG15: sub x0, fp, #88 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG16: add w23, w23, w22 b G_M000_IG13 G_M000_IG17: ldr w0, [fp, #-0x50] cbnz w0, G_M000_IG19 mov x0, x19 movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #-0x60] cmp xip0, xip1 beq G_M000_IG18 bl CORINFO_HELP_FAIL_FAST G_M000_IG18: sub sp, fp, #96 ldp fp, lr, [sp, #0x60] ldr x25, [sp, #0x58] ldp x23, x24, [sp, #0x48] ldp x21, x22, [sp, #0x38] ldp x19, x20, [sp, #0x28] add sp, sp, #112 ret lr G_M000_IG19: mov w1, w22 ldr w4, [fp, #-0x50] ldr w3, [fp, #-0x40] cmp w4, w3 bhi G_M000_IG23 ldr x3, [fp, #-0x48] mov x0, x19 mov x2, x21 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 mov x20, x0 ldr x19, [fp, #-0x58] cbz x19, G_M000_IG20 str xzr, [fp, #-0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #55 bl CORINFO_HELP_CLASSINIT_SHARED_DYNAMICCLASS movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] mov x1, x19 mov w2, wzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG20: mov x0, x20 movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #-0x60] cmp xip0, xip1 beq G_M000_IG21 bl CORINFO_HELP_FAIL_FAST G_M000_IG21: sub sp, fp, #96 ldp fp, lr, [sp, #0x60] ldr x25, [sp, #0x58] ldp x23, x24, [sp, #0x48] ldp x21, x22, [sp, #0x38] ldp x19, x20, [sp, #0x28] add sp, sp, #112 ret lr G_M000_IG22: mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov x1, x0 mov x0, x20 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 brk_windows #0 G_M000_IG23: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 ; Total bytes of code 848 1197: JIT compiled System.String:Replace(System.String,System.String) [Tier1, IL size=280, code size=848] ; Assembly listing for method System.String:Replace(ushort,ushort):System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are invalid, and fgCalledCount is 44700 ; 0 inlinees with PGO data; 6 single block inlinees; 2 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x40]! stp x19, x20, [sp, #0x10] stp x21, x22, [sp, #0x20] stp x23, x24, [sp, #0x30] mov fp, sp mov x19, x0 mov w20, w1 mov w21, w2 G_M000_IG02: uxth w0, w20 uxth w2, w21 cmp w0, w2 beq G_M000_IG09 add x0, x19, #12 ldr w2, [x19, #0x08] sxth w1, w20 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov w22, w0 tbz w22, #31, G_M000_IG05 G_M000_IG03: mov x0, x19 G_M000_IG04: ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG05: ldr w0, [x19, #0x08] sub w0, w0, w22 mov w23, w0 ldr w0, [x19, #0x08] bl System.String:FastAllocateString(int):System.String mov x24, x0 cmp w22, #0 ble G_M000_IG06 ldrsb wzr, [x24] add x0, x24, #12 add x1, x19, #12 mov w2, w22 lsl x2, x2, #1 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG06: add x0, x19, #12 ubfiz x2, x22, #1, #32 add x0, x0, x2 ldrsb wzr, [x24] add x2, x24, #12 ubfiz x3, x22, #1, #32 add x1, x2, x3 ldr w2, [x19, #0x08] cmp x2, #8 bhs G_M000_IG11 G_M000_IG07: uxth w2, w20 uxth w3, w21 mov x4, x23 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 mov x0, x24 G_M000_IG08: ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG09: mov x0, x19 G_M000_IG10: ldp x23, x24, [sp, #0x30] ldp x21, x22, [sp, #0x20] ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG11: sub x2, x2, x23 and x2, x2, #7 lsl x3, x2, #1 sub x0, x0, x3 lsl x3, x2, #1 sub x1, x1, x3 add x23, x23, x2 b G_M000_IG07 ; Total bytes of code 336 1198: JIT compiled System.String:Replace(ushort,ushort) [Tier1 with Static PGO, IL size=179, code size=336] ; Assembly listing for method System.Text.StringBuilder:ToString():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; fully interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 73038 ; 1 inlinees with PGO data; 4 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! stp x19, x20, [sp, #0x10] mov fp, sp mov x19, x0 G_M000_IG02: ldp w1, w0, [x19, #0x18] add w0, w0, w1 cbz w0, G_M000_IG08 G_M000_IG03: bl System.String:FastAllocateString(int):System.String mov x20, x0 G_M000_IG04: ldr w2, [x19, #0x18] cmp w2, #0 ble G_M000_IG05 ldr x0, [x19, #0x08] ldr w1, [x19, #0x1C] add w3, w2, w1 ldr w4, [x20, #0x08] cmp w3, w4 bhi G_M000_IG10 ldr w3, [x0, #0x08] cmp w3, w2 blo G_M000_IG10 add x3, x20, #12 sbfiz x1, x1, #1, #32 add x1, x3, x1 add x3, x0, #16 sxtw x2, w2 lsl x2, x2, #1 mov x0, x1 mov x1, x3 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG05: ldr x19, [x19, #0x10] cbnz x19, G_M000_IG04 G_M000_IG06: mov x0, x20 G_M000_IG07: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG08: movz x0, #8 movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG09: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG10: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 movz w0, #0xD1FFAB1E movk w0, #1 LSL #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov x20, x0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 mov x2, x0 mov x1, x20 mov x0, x19 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x19 bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 296 1199: JIT compiled System.Text.StringBuilder:ToString() [Tier1 with Static PGO, IL size=132, code size=296] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:WriteLine(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr x0, [x0, #0x08] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr wzr, [x0] ldr x2, [x11] G_M000_IG03: ldp fp, lr, [sp], #0x10 br x2 ; Total bytes of code 40 1200: JIT compiled BenchmarkDotNet.Engines.Engine:WriteLine(System.String) [Tier1, IL size=13, code size=40] ; Assembly listing for method System.Text.Ascii:NarrowUtf16ToAscii_Intrinsified(ulong,ulong,ulong):ulong ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 0 single block inlinees; 8 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr q16, [x0] umaxp v17.8h, v16.8h, v16.8h umov x3, v17.d[0] tst x3, #0xD1FFAB1E beq G_M000_IG05 G_M000_IG03: mov x0, xzr G_M000_IG04: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG05: mov x3, x1 uzp1 v16.16b, v16.16b, v16.16b str d16, [x3] mov x4, #8 tbnz w1, #3, G_M000_IG06 ldr q16, [x0, #0x10] umaxp v17.8h, v16.8h, v16.8h umov x5, v17.d[0] tst x5, #0xD1FFAB1E bne G_M000_IG08 uzp1 v16.16b, v16.16b, v16.16b str d16, [x3, #0x08] G_M000_IG06: and x4, x1, #15 mov x1, #16 sub x4, x1, x4 sub x1, x2, #16 align [0 bytes for IG07] align [0 bytes] align [0 bytes] align [0 bytes] G_M000_IG07: lsl x2, x4, #1 ldr q16, [x0, x2] add x2, x4, #8 lsl x5, x2, #1 ldr q17, [x0, x5] orr v18.8h, v16.8h, v17.8h umaxp v18.8h, v18.8h, v18.8h umov x5, v18.d[0] tst x5, #0xD1FFAB1E bne G_M000_IG10 uzp1 v16.16b, v16.16b, v17.16b str q16, [x3, x4] add x4, x4, #16 cmp x4, x1 bls G_M000_IG07 G_M000_IG08: mov x0, x4 G_M000_IG09: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG10: umaxp v17.8h, v16.8h, v16.8h umov x0, v17.d[0] tst x0, #0xD1FFAB1E bne G_M000_IG08 uzp1 v16.16b, v16.16b, v16.16b str d16, [x3, x4] mov x4, x2 b G_M000_IG08 ; Total bytes of code 208 1201: JIT compiled System.Text.Ascii:NarrowUtf16ToAscii_Intrinsified(ulong,ulong,ulong) [Tier1, IL size=251, code size=208] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:Consume(byref):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 16 1202: JIT compiled BenchmarkDotNet.Engines.Engine:Consume(byref) [Tier1, IL size=1, code size=16] ; Assembly listing for method BenchmarkDotNet.Engines.EngineStage:RunIteration(int,int,int,long,int):BenchmarkDotNet.Reports.Measurement:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 3 inlinees with PGO data; 7 single block inlinees; 9 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x70]! stp x19, x20, [sp, #0x60] mov fp, sp add x9, fp, #56 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] mov x19, x4 mov w20, w5 G_M000_IG02: sxtw x11, w20 cmp x11, #0 beq G_M000_IG06 cmn x11, #1 bne G_M000_IG03 cmp x19, #1 bvs G_M000_IG05 G_M000_IG03: sdiv x4, x19, x11 msub x11, x4, x11, x19 cbnz x11, G_M000_IG07 stp xzr, xzr, [fp, #0x18] stp xzr, xzr, [fp, #0x28] ldr x0, [x0, #0x08] stp w1, w2, [fp, #0x18] str w3, [fp, #0x20] str x19, [fp, #0x28] str w20, [fp, #0x30] add x1, fp, #24 movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 G_M000_IG04: ldp x19, x20, [sp, #0x60] ldp fp, lr, [sp], #0x70 ret lr G_M000_IG05: bl CORINFO_HELP_OVERFLOW G_M000_IG06: bl CORINFO_HELP_THROWDIVZERO G_M000_IG07: add x0, fp, #56 mov w1, #53 mov w2, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr w0, [fp, #0x48] ldr w1, [fp, #0x58] cmp w0, w1 bhi G_M000_IG12 ldr x1, [fp, #0x50] ubfiz x2, x0, #1, #32 add x1, x1, x2 ldr w2, [fp, #0x58] sub w0, w2, w0 cmp w0, #12 blo G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 add x0, x0, #12 ldr q16, [x0] ldr q17, [x0, #0x08] str q16, [x1] str q17, [x1, #0x08] ldr w0, [fp, #0x48] add w0, w0, #12 str w0, [fp, #0x48] b G_M000_IG09 G_M000_IG08: add x0, fp, #56 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG09: add x0, fp, #56 mov x1, x19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [fp, #0x48] ldr w1, [fp, #0x58] cmp w0, w1 bhi G_M000_IG12 ldr x1, [fp, #0x50] ubfiz x2, x0, #1, #32 add x1, x1, x2 ldr w2, [fp, #0x58] sub w0, w2, w0 cmp w0, #39 blo G_M000_IG10 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 add x2, x0, #12 mov x0, x1 mov x1, x2 mov x2, #78 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr w0, [fp, #0x48] add w0, w0, #39 str w0, [fp, #0x48] b G_M000_IG11 G_M000_IG10: add x0, fp, #56 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG11: add x0, fp, #56 mov w1, w20 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w19, [fp, #0x48] ldr w0, [fp, #0x58] cmp w19, w0 bls G_M000_IG13 G_M000_IG12: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 G_M000_IG13: ldr x0, [fp, #0x50] ubfiz x1, x19, #1, #32 add x0, x0, x1 ldr w1, [fp, #0x58] sub w1, w1, w19 cmp w1, #2 blo G_M000_IG14 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 add x1, x1, #12 ldr w2, [x1] str w2, [x0] ldr w0, [fp, #0x48] add w0, w0, #2 str w0, [fp, #0x48] b G_M000_IG15 G_M000_IG14: add x0, fp, #56 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG15: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 add x0, fp, #56 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x1, x0 mov x0, x19 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 mov x0, x19 bl CORINFO_HELP_THROW brk_windows #0 ; Total bytes of code 736 1203: JIT compiled BenchmarkDotNet.Engines.EngineStage:RunIteration(int,int,int,long,int) [Tier1, IL size=109, code size=736] ; Assembly listing for method BenchmarkDotNet.Engines.IterationData:.ctor(int,int,int,long,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: stp w1, w2, [x0] str w3, [x0, #0x08] str x4, [x0, #0x10] str w5, [x0, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 32 1204: JIT compiled BenchmarkDotNet.Engines.IterationData:.ctor(int,int,int,long,int) [Tier1, IL size=38, code size=32] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:RunIteration(BenchmarkDotNet.Engines.IterationData):BenchmarkDotNet.Reports.Measurement:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 1 inlinees with PGO data; 39 single block inlinees; 3 inlinees without PGO data G_M000_IG01: sub sp, sp, #0xD1FFAB1E stp x19, x20, [sp, #0xD1FFAB1E] stp x21, x22, [sp, #0xD1FFAB1E] stp x23, x24, [sp, #0xD1FFAB1E] stp x25, x26, [sp, #0xD1FFAB1E] stp x27, x28, [sp, #0xD1FFAB1E] stp fp, lr, [sp, #0xD1FFAB1E] add fp, sp, #0xD1FFAB1E sub x9, fp, #152 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] str xzr, [x9, #0x40] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 str x2, [fp, #-0x100] str x8, [fp, #-0xD8] mov x20, x0 mov x19, x1 G_M000_IG02: sub x0, fp, #0xD1FFAB1E mov x1, x12 bl CORINFO_HELP_INIT_PINVOKE_FRAME mov x22, x0 mov x0, sp movn xip1, #0xD1FFAB1E str x0, [fp, xip1] mov x0, fp movn xip1, #0xD1FFAB1E str x0, [fp, xip1] ldr x23, [x19, #0x10] ldr w24, [x19, #0x18] ldr x0, [x20, #0xA8] mul x25, x23, x0 str x19, [fp, #-0xE0] ldr w0, [x19] cmp w0, #0 cset x26, eq cbnz w26, G_M000_IG04 G_M000_IG03: ldrb w0, [x20, #0xBA] b G_M000_IG05 G_M000_IG04: mov w0, wzr G_M000_IG05: uxtb w27, w0 cbnz w26, G_M000_IG07 G_M000_IG06: ldr x28, [x20, #0x10] b G_M000_IG08 G_M000_IG07: ldr x28, [x20, #0x30] G_M000_IG08: str x28, [fp, #-0xE8] cbnz w26, G_M000_IG10 G_M000_IG09: ldr x1, [x20, #0x50] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 G_M000_IG10: str x20, [fp, #-0xD0] ldrb w0, [x20, #0xB8] cbz w0, G_M000_IG24 G_M000_IG11: movn w0, #0 mov w1, #2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movn xip1, #0xD1FFAB1E str x2, [fp, xip1] adr x2, [G_M000_IG14] movn xip1, #0xD1FFAB1E str x2, [fp, xip1] sub x2, fp, #0xD1FFAB1E str x2, [x22, #0x10] strb wzr, [x22, #0x0C] G_M000_IG12: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 G_M000_IG13: blr x2 G_M000_IG14: mov w0, #1 strb w0, [x22, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG15 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG15: movn xip1, #0xD1FFAB1E ldr x0, [fp, xip1] str x0, [x22, #0x10] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movn xip1, #0xD1FFAB1E str x0, [fp, xip1] adr x0, [G_M000_IG18] movn xip1, #0xD1FFAB1E str x0, [fp, xip1] sub x0, fp, #0xD1FFAB1E str x0, [x22, #0x10] strb wzr, [x22, #0x0C] G_M000_IG16: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG17: blr x0 G_M000_IG18: mov w0, #1 strb w0, [x22, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG19 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG19: movn xip1, #0xD1FFAB1E ldr x0, [fp, xip1] str x0, [x22, #0x10] movn w0, #0 mov w1, #2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movn xip1, #0xD1FFAB1E str x2, [fp, xip1] adr x2, [G_M000_IG22] movn xip1, #0xD1FFAB1E str x2, [fp, xip1] sub x2, fp, #0xD1FFAB1E str x2, [x22, #0x10] strb wzr, [x22, #0x0C] G_M000_IG20: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 G_M000_IG21: blr x2 G_M000_IG22: mov w0, #1 strb w0, [x22, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG23 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG23: movn xip1, #0xD1FFAB1E ldr x0, [fp, xip1] str x0, [x22, #0x10] G_M000_IG24: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x4, [x0] str x4, [fp, #-0xF8] ldrb w0, [x4, #0x9D] cbz w0, G_M000_IG26 G_M000_IG25: mov x0, x4 ldr x19, [fp, #-0xE0] ldp w1, w2, [x19] mov x3, x25 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 str x19, [fp, #-0xE0] ldr x4, [fp, #-0xF8] G_M000_IG26: cbz w27, G_M000_IG30 G_M000_IG27: ldr x20, [fp, #-0xD0] ldr x0, [x20, #0xA0] mov w1, #32 ldr x2, [x0] ldr x2, [x2, #0x40] ldr x2, [x2, #0x28] blr x2 mov w11, w0 tst x11, x11 beq G_M000_IG29 add x11, x11, #15 and x11, x11, #-16 G_M000_IG28: stp xzr, xzr, [sp, #-0x10]! subs x11, x11, #16 bne G_M000_IG28 mov x11, sp G_M000_IG29: tbnz w0, #31, G_M000_IG63 b G_M000_IG31 G_M000_IG30: mov x11, xzr mov w0, wzr ldr x20, [fp, #-0xD0] G_M000_IG31: str x11, [fp, #-0x60] str w0, [fp, #-0x58] ldr x1, [x20, #0x78] str x1, [fp, #-0xF0] mov x0, x1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 str x2, [fp, #-0xC8] mov x11, x2 ldr x3, [x11] blr x3 str x0, [fp, #-0xA0] sxtw x1, w24 cmp x1, #0 beq G_M000_IG62 cmn x1, #1 bne G_M000_IG32 cmp x23, #1 bvs G_M000_IG61 G_M000_IG32: sdiv x1, x23, x1 ldr x28, [fp, #-0xE8] ldr x0, [x28, #0x08] ldr x3, [x28, #0x18] blr x3 ldr x0, [fp, #-0xF0] ldr x23, [fp, #-0xC8] add x11, x23, #8 ldr x1, [x11] blr x1 mov x24, x0 ldr x0, [fp, #-0xF0] add x11, x23, #16 ldr x1, [x11] blr x1 ldr x28, [fp, #-0xA0] str x28, [fp, #-0x78] str x24, [fp, #-0x70] str d0, [fp, #-0x68] ldr x24, [fp, #-0xF8] ldrb w0, [x24, #0x9D] cbz w0, G_M000_IG34 G_M000_IG33: mov x0, x24 ldr x19, [fp, #-0xE0] ldr w1, [x19] str x19, [fp, #-0xE0] ldr w2, [x19, #0x04] mov x3, x25 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG34: cbnz w26, G_M000_IG36 G_M000_IG35: ldr x1, [x20, #0x58] ldr x0, [x1, #0x08] ldr x1, [x1, #0x18] blr x1 G_M000_IG36: cbz w27, G_M000_IG38 G_M000_IG37: mov x0, x20 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG38: str x20, [fp, #-0xD0] ldrb w0, [x20, #0xB8] cbz w0, G_M000_IG52 G_M000_IG39: movn w0, #0 mov w1, #2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movn xip1, #0xD1FFAB1E str x2, [fp, xip1] adr x2, [G_M000_IG42] movn xip1, #0xD1FFAB1E str x2, [fp, xip1] sub x2, fp, #0xD1FFAB1E str x2, [x22, #0x10] strb wzr, [x22, #0x0C] G_M000_IG40: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 G_M000_IG41: blr x2 G_M000_IG42: mov w0, #1 strb w0, [x22, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG43 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG43: movn xip1, #0xD1FFAB1E ldr x0, [fp, xip1] str x0, [x22, #0x10] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movn xip1, #0xD1FFAB1E str x0, [fp, xip1] adr x0, [G_M000_IG46] movn xip1, #0xD1FFAB1E str x0, [fp, xip1] sub x0, fp, #0xD1FFAB1E str x0, [x22, #0x10] strb wzr, [x22, #0x0C] G_M000_IG44: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 G_M000_IG45: blr x0 G_M000_IG46: mov w0, #1 strb w0, [x22, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG47 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG47: movn xip1, #0xD1FFAB1E ldr x0, [fp, xip1] str x0, [x22, #0x10] movn w0, #0 mov w1, #2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movn xip1, #0xD1FFAB1E str x2, [fp, xip1] adr x2, [G_M000_IG50] movn xip1, #0xD1FFAB1E str x2, [fp, xip1] sub x2, fp, #0xD1FFAB1E str x2, [x22, #0x10] strb wzr, [x22, #0x0C] G_M000_IG48: movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 G_M000_IG49: blr x2 G_M000_IG50: mov w0, #1 strb w0, [x22, #0x0C] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr w0, [x0] cmp w0, #0 beq G_M000_IG51 bl CORINFO_HELP_STOP_FOR_GC G_M000_IG51: movn xip1, #0xD1FFAB1E ldr x0, [fp, xip1] str x0, [x22, #0x10] G_M000_IG52: ldr x19, [fp, #-0xE0] ldp w22, w24, [x19] ldr w19, [x19, #0x08] sub x0, fp, #120 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x25, [fp, #-0x88] str d0, [fp, #-0x80] str wzr, [fp, #-0x90] str w22, [fp, #-0x98] str w24, [fp, #-0x94] str w19, [fp, #-0x8C] sub x0, fp, #152 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x1, x0 ldr x20, [fp, #-0xD0] ldr x0, [x20, #0x08] add x11, x23, #24 ldr x2, [x11] blr x2 ldr w1, [fp, #-0x94] cbnz w1, G_M000_IG57 G_M000_IG53: ldr x0, [x20, #0x80] G_M000_IG54: add x1, fp, #40 ldp q16, q17, [x1, #-0xC0] stp q16, q17, [fp, #-0xC0] G_M000_IG55: ldr w1, [x0, #0x14] add w1, w1, #1 str w1, [x0, #0x14] ldr x1, [x0, #0x08] ldr w2, [x0, #0x10] ldr w3, [x1, #0x08] cmp w3, w2 bls G_M000_IG56 add w3, w2, #1 str w3, [x0, #0x10] ubfiz x0, x2, #5, #32 add x0, x0, #16 add x1, x1, x0 ldp q16, q17, [fp, #-0xC0] stp q16, q17, [x1] b G_M000_IG57 G_M000_IG56: sub x1, fp, #192 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG57: sub x1, fp, #96 mov x0, x20 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x21, [fp, #-0xD8] G_M000_IG58: sub x0, fp, #152 ldp q16, q17, [x0] stp q16, q17, [x21] G_M000_IG59: movz xip0, #0xD1FFAB1E movk xip0, #0xD1FFAB1E LSL #16 movk xip0, #0xD1FFAB1E LSL #32 ldr xip1, [fp, #-0x100] cmp xip0, xip1 beq G_M000_IG60 bl CORINFO_HELP_FAIL_FAST G_M000_IG60: sub sp, fp, #0xD1FFAB1E ldp fp, lr, [sp, #0xD1FFAB1E] ldp x27, x28, [sp, #0xD1FFAB1E] ldp x25, x26, [sp, #0xD1FFAB1E] ldp x23, x24, [sp, #0xD1FFAB1E] ldp x21, x22, [sp, #0xD1FFAB1E] ldp x19, x20, [sp, #0xD1FFAB1E] add sp, sp, #0xD1FFAB1E ret lr G_M000_IG61: bl CORINFO_HELP_OVERFLOW G_M000_IG62: bl CORINFO_HELP_THROWDIVZERO G_M000_IG63: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 ; Total bytes of code 1696 1205: JIT compiled BenchmarkDotNet.Engines.Engine:RunIteration(BenchmarkDotNet.Engines.IterationData) [Tier1, IL size=361, code size=1696] ; Assembly listing for method BenchmarkDotNet.Engines.IterationData:get_InvokeCount():long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr x0, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1206: JIT compiled BenchmarkDotNet.Engines.IterationData:get_InvokeCount() [Tier1, IL size=7, code size=20] ; Assembly listing for method BenchmarkDotNet.Engines.IterationData:get_UnrollFactor():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w0, [x0, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1207: JIT compiled BenchmarkDotNet.Engines.IterationData:get_UnrollFactor() [Tier1, IL size=7, code size=20] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_OperationsPerInvoke():long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr x0, [x0, #0xA8] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1208: JIT compiled BenchmarkDotNet.Engines.Engine:get_OperationsPerInvoke() [Tier1, IL size=7, code size=20] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:IterationStart(int,int,long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 7 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! stp x19, x20, [sp, #0x10] mov fp, sp mov w19, w2 G_M000_IG02: cmp w19, #3 bhi G_M000_IG18 mov w2, w19 adr x4, [@RWD00] ldr w4, [x4, x2, LSL #2] adr x5, [G_M000_IG02] add x4, x4, x5 br x4 G_M000_IG03: cbnz w1, G_M000_IG05 mov x2, x3 mov w1, #3 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG04: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 br x3 G_M000_IG05: cmp w1, #1 bne G_M000_IG18 mov x2, x3 mov w1, #5 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG06: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 br x3 G_M000_IG07: cmp w1, #1 bne G_M000_IG18 mov x2, x3 mov w1, #7 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG08: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 br x3 G_M000_IG09: cbnz w1, G_M000_IG11 mov x2, x3 mov w1, #9 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG10: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 br x3 G_M000_IG11: cmp w1, #1 bne G_M000_IG18 mov x2, x3 mov w1, #13 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG12: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 br x3 G_M000_IG13: cbnz w1, G_M000_IG15 mov x2, x3 mov w1, #11 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG14: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 br x3 G_M000_IG15: cmp w1, #1 bne G_M000_IG18 mov x2, x3 mov w1, #15 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] G_M000_IG16: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 br x3 G_M000_IG17: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG18: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x20, x0 str w19, [x20, #0x08] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov x1, x0 mov x2, x20 mov x0, x19 mov x3, xzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 mov x0, x19 bl CORINFO_HELP_THROW brk_windows #0 RWD00 dd G_M000_IG03 - G_M000_IG02 dd G_M000_IG07 - G_M000_IG02 dd G_M000_IG09 - G_M000_IG02 dd G_M000_IG13 - G_M000_IG02 ; Total bytes of code 468 1209: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:IterationStart(int,int,long) [Tier1, IL size=125, code size=468] ; Assembly listing for method System.Diagnostics.Tracing.ActivityTracker:OnStart(System.String,System.String,int,byref,byref,int,bool):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 3 inlinees with PGO data; 16 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x90]! stp x19, x20, [sp, #0x40] stp x21, x22, [sp, #0x50] stp x23, x24, [sp, #0x60] stp x25, x26, [sp, #0x70] stp x27, x28, [sp, #0x80] mov fp, sp mov x19, x0 mov x22, x1 mov x23, x2 mov w24, w3 mov x21, x4 mov x20, x5 mov w25, w6 mov w26, w7 G_M000_IG02: ldr x1, [x19, #0x08] cbnz x1, G_M000_IG10 G_M000_IG03: ldrb w1, [x19, #0x10] cbz w1, G_M000_IG05 G_M000_IG04: ldp x27, x28, [sp, #0x80] ldp x25, x26, [sp, #0x70] ldp x23, x24, [sp, #0x60] ldp x21, x22, [sp, #0x50] ldp x19, x20, [sp, #0x40] ldp fp, lr, [sp], #0x90 ret lr G_M000_IG05: mov w1, #1 strb w1, [x19, #0x10] tst w26, #255 beq G_M000_IG08 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x0, [x1] ldrb w1, [x0, #0x9D] cbz w1, G_M000_IG08 G_M000_IG06: ldr x3, [x0, #0x80] ldr w2, [x0, #0x98] mov w4, #4 mov x5, #128 mov w6, wzr movz x7, #0xD1FFAB1E movk x7, #0xD1FFAB1E LSL #16 movk x7, #0xD1FFAB1E LSL #32 ldr x7, [x7] blr x7 cbz w0, G_M000_IG08 G_M000_IG07: mov x0, x19 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG08: ldr x0, [x19, #0x08] cbnz x0, G_M000_IG10 G_M000_IG09: ldp x27, x28, [sp, #0x80] ldp x25, x26, [sp, #0x70] ldp x23, x24, [sp, #0x60] ldp x21, x22, [sp, #0x50] ldp x19, x20, [sp, #0x40] ldp fp, lr, [sp], #0x90 ret lr G_M000_IG10: ldr x0, [x19, #0x08] ldrsb wzr, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x1, x0 mov x27, x1 cbz x27, G_M000_IG12 G_M000_IG11: ldr x0, [x27] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 cmp x0, x3 bne G_M000_IG29 G_M000_IG12: mov x0, x22 mov x1, x23 mov w2, w24 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x28, x0 tst w26, #255 bne G_M000_IG13 mov x26, xzr b G_M000_IG14 G_M000_IG13: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x26, [x0] G_M000_IG14: cbz x26, G_M000_IG15 ldrb w0, [x26, #0xB1] b G_M000_IG16 G_M000_IG15: mov w0, wzr G_M000_IG16: uxtb w4, w0 str w4, [fp, #0x3C] cbz w4, G_M000_IG17 ldrsb wzr, [x26] mov x0, x26 mov x3, x28 mov w1, #23 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 mov x0, x27 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x3, x0 mov x0, x26 mov w1, #23 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 G_M000_IG17: cbz x27, G_M000_IG22 ldr w0, [x27, #0x2C] cmp w0, #100 blt G_M000_IG20 stp xzr, xzr, [x21] stp xzr, xzr, [x20] ldr w4, [fp, #0x3C] cbz w4, G_M000_IG19 ldrsb wzr, [x26] mov x0, x26 mov w1, #23 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] G_M000_IG18: ldp x27, x28, [sp, #0x80] ldp x25, x26, [sp, #0x70] ldp x23, x24, [sp, #0x60] ldp x21, x22, [sp, #0x50] ldp x19, x20, [sp, #0x40] ldp fp, lr, [sp], #0x90 br x4 G_M000_IG19: ldp x27, x28, [sp, #0x80] ldp x25, x26, [sp, #0x70] ldp x23, x24, [sp, #0x60] ldp x21, x22, [sp, #0x50] ldp x19, x20, [sp, #0x40] ldp fp, lr, [sp], #0x90 ret lr G_M000_IG20: tbnz w25, #2, G_M000_IG22 mov x0, x28 mov x1, x27 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz x0, G_M000_IG22 mov x0, x19 mov x1, x22 mov x2, x23 mov w3, w24 mov x4, x21 mov w5, #1 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x0, [x19, #0x08] ldrsb wzr, [x0] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] mov x27, x0 cbz x27, G_M000_IG22 G_M000_IG21: ldr x1, [x27] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 cmp x1, x2 bne G_M000_IG30 G_M000_IG22: cbnz x27, G_M000_IG23 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, #1 ldaddal x1, x0, [x0] add x22, x0, #1 b G_M000_IG24 G_M000_IG23: add x0, x27, #32 mov x1, #1 ldaddal x1, x0, [x0] add x22, x0, #1 G_M000_IG24: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 stp x0, x1, [fp, #0x28] ldr q16, [fp, #0x28] str q16, [x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x23, x0 ldr q16, [x20] str q16, [fp, #0x18] add x14, x23, #8 mov x15, x28 bl CORINFO_HELP_ASSIGN_REF str w25, [x23, #0x30] add x14, x23, #16 mov x15, x27 bl CORINFO_HELP_ASSIGN_REF str x22, [x23, #0x18] cbnz x27, G_M000_IG25 mov w2, wzr b G_M000_IG26 G_M000_IG25: ldr w2, [x27, #0x2C] add w2, w2, #1 G_M000_IG26: str w2, [x23, #0x2C] ldr q16, [fp, #0x18] str q16, [x23, #0x48] add x2, x23, #40 add x1, x23, #56 mov x0, x23 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [x19, #0x08] ldr x2, [x0, #0x08] cmp x2, #0 cset x2, ne mov x1, x23 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr q16, [x23, #0x38] str q16, [x21] ldr w19, [fp, #0x3C] cbz w19, G_M000_IG28 mov x0, x23 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 mov x3, x0 ldrsb wzr, [x26] mov x0, x26 mov w1, #23 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 mov x0, x21 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 mov x2, xzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x19, x0 mov x0, x20 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 mov x2, xzr movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x4, x0 mov x0, x26 mov x3, x19 mov w1, #24 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] G_M000_IG27: ldp x27, x28, [sp, #0x80] ldp x25, x26, [sp, #0x70] ldp x23, x24, [sp, #0x60] ldp x21, x22, [sp, #0x50] ldp x19, x20, [sp, #0x40] ldp fp, lr, [sp], #0x90 br x5 G_M000_IG28: ldp x27, x28, [sp, #0x80] ldp x25, x26, [sp, #0x70] ldp x23, x24, [sp, #0x60] ldp x21, x22, [sp, #0x50] ldp x19, x20, [sp, #0x40] ldp fp, lr, [sp], #0x90 ret lr G_M000_IG29: mov x0, x3 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 brk_windows #0 G_M000_IG30: mov x0, x2 ldr x1, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 brk_windows #0 ; Total bytes of code 1384 1210: JIT compiled System.Diagnostics.Tracing.ActivityTracker:OnStart(System.String,System.String,int,byref,byref,int,bool) [Tier1, IL size=389, code size=1384] ; Assembly listing for method System.Span`1[ubyte]:get_Empty():System.Span`1[ubyte] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov x0, xzr mov w1, wzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 24 1211: JIT compiled System.Span`1[ubyte]:get_Empty() [Tier1, IL size=10, code size=24] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_Clock():Perfolizer.Horology.IClock:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr x0, [x0, #0x78] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1212: JIT compiled BenchmarkDotNet.Engines.Engine:get_Clock() [Tier1, IL size=7, code size=20] ; Assembly listing for method Perfolizer.Horology.ClockExtensions:Start(Perfolizer.Horology.IClock):Perfolizer.Horology.StartedClock ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! str x19, [sp, #0x18] mov fp, sp mov x19, x0 G_M000_IG02: mov x0, x19 movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 mov x1, x0 mov x0, x19 G_M000_IG03: ldr x19, [sp, #0x18] ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 60 1213: JIT compiled Perfolizer.Horology.ClockExtensions:Start(Perfolizer.Horology.IClock) [Tier1, IL size=13, code size=60] ; Assembly listing for method Perfolizer.Horology.StartedClock:.ctor(Perfolizer.Horology.IClock,long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov x14, x0 mov x15, x1 bl CORINFO_HELP_CHECKED_ASSIGN_REF str x2, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 32 1214: JIT compiled Perfolizer.Horology.StartedClock:.ctor(Perfolizer.Horology.IClock,long) [Tier1, IL size=15, code size=32] ; Assembly listing for method System.Math:Abs(double):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov x0, v0.d[0] and x0, x0, #0xD1FFAB1E fmov d0, x0 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 28 1215: JIT compiled System.Math:Abs(double) [Tier1, IL size=24, code size=28] ; Assembly listing for method Perfolizer.Mathematics.Distributions.StudentDistribution:StudentTwoTail(double,double):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; 0 inlinees with PGO data; 3 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x40]! stp d8, d9, [sp, #0x10] stp d10, d11, [sp, #0x20] stp x19, x20, [sp, #0x30] mov fp, sp fmov d8, d1 G_M000_IG02: fcmp d0, #0.0 blo G_M000_IG16 fmov d16, #1.0000 fcmp d8, d16 blo G_M000_IG17 fmul d0, d0, d0 fdiv d16, d0, d8 fmov d17, #1.0000 fadd d9, d16, d17 frintn d17, d8 fcvtzs w19, d17 scvtf d10, w19 fsub d17, d8, d10 fabs d17, d17 ldr d18, [@RWD00] fcmp d17, d18 bgt G_M000_IG04 G_M000_IG03: fmov d17, #20.0000 fcmp d8, d17 bge G_M000_IG04 fcmp d0, d8 bhs G_M000_IG07 ldr d17, [@RWD08] fcmp d8, d17 ble G_M000_IG07 G_M000_IG04: ldr d0, [@RWD16] fcmp d16, d0 ble G_M000_IG05 fmov d0, d9 bl System.Math:Log(double):double fmov d16, d0 G_M000_IG05: fmov d0, #0.5000 fsub d0, d8, d0 fmul d17, d0, d0 ldr d18, [@RWD24] fmul d9, d17, d18 fmul d16, d0, d16 ldr d0, [@RWD32] fmul d0, d16, d0 ldr d17, [@RWD40] fsub d0, d0, d17 fmul d0, d0, d16 fmov d17, #24.0000 fsub d0, d0, d17 fmul d0, d0, d16 ldr d17, [@RWD48] fsub d0, d0, d17 fmul d17, d16, d16 ldr d18, [@RWD56] fmul d17, d17, d18 ldr d18, [@RWD64] fadd d17, d17, d18 fadd d17, d17, d9 fdiv d0, d0, d17 fadd d0, d0, d16 fmov d17, #3.0000 fadd d0, d0, d17 fdiv d0, d0, d9 fmov d17, #1.0000 fadd d0, d0, d17 fsqrt d16, d16 fmul d16, d0, d16 fneg d0, d16 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 fmov d16, #2.0000 fmul d0, d0, d16 G_M000_IG06: ldp x19, x20, [sp, #0x30] ldp d10, d11, [sp, #0x20] ldp d8, d9, [sp, #0x10] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG07: fmov d11, #1.0000 fmov d17, #20.0000 fcmp d8, d17 bhs G_M000_IG08 fmov d17, #4.0000 fcmp d0, d17 bhs G_M000_IG08 fsqrt d16, d16 fmov d8, d16 cmp w19, #1 bne G_M000_IG11 movi v8.16b, #0 b G_M000_IG11 align [4 bytes for IG09] align [4 bytes] align [0 bytes] align [0 bytes] G_M000_IG08: fsqrt d8, d9 fmul d16, d8, d10 mov w0, wzr fmov d0, #1.0000 fsub d0, d8, d0 fabs d0, d0 fcmp d0, #0.0 ble G_M000_IG10 G_M000_IG09: add w0, w0, #2 fmov d11, d8 scvtf d0, w0 fmul d0, d9, d0 sub w1, w0, #1 scvtf d17, w1 fdiv d0, d17, d0 fmul d16, d0, d16 add w1, w19, w0 scvtf d0, w1 fdiv d0, d16, d0 fadd d8, d0, d11 fsub d0, d8, d11 fabs d0, d0 fcmp d0, #0.0 bgt G_M000_IG09 G_M000_IG10: add w19, w19, #2 movi v11.16b, #0 movi v16.16b, #0 fneg d8, d8 G_M000_IG11: sub w19, w19, #2 cmp w19, #1 ble G_M000_IG12 scvtf d0, w19 fmul d0, d9, d0 sub w0, w19, #1 scvtf d17, w0 fdiv d0, d17, d0 fmul d0, d0, d8 fadd d8, d0, d16 b G_M000_IG11 G_M000_IG12: cbz w19, G_M000_IG13 fmov d0, d16 bl System.Math:Atan(double):double fdiv d16, d8, d9 fadd d0, d0, d16 fmov d16, #2.0000 fmul d0, d0, d16 ldr d16, [@RWD72] fdiv d0, d0, d16 b G_M000_IG14 G_M000_IG13: fsqrt d0, d9 fdiv d0, d8, d0 G_M000_IG14: fsub d0, d11, d0 G_M000_IG15: ldp x19, x20, [sp, #0x30] ldp d10, d11, [sp, #0x20] ldp d8, d9, [sp, #0x10] ldp fp, lr, [sp], #0x40 ret lr G_M000_IG16: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov x20, x0 mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov x2, x0 mov x1, x20 mov x0, x19 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x19 bl CORINFO_HELP_THROW G_M000_IG17: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov x20, x0 mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov x2, x0 mov x1, x20 mov x0, x19 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 mov x0, x19 bl CORINFO_HELP_THROW brk_windows #0 RWD00 dq 3E112E0BE826D695h ; 1e-09 RWD08 dq 4069000000000000h ; 200 RWD16 dq 3EB0C6F7A0B5ED8Dh ; 1e-06 RWD24 dq 4048000000000000h ; 48 RWD32 dq BFD999999999999Ah ; -0.4 RWD40 dq 400A666666666666h ; 3.3 RWD48 dq 4055600000000000h ; 85.5 RWD56 dq 3FE999999999999Ah ; 0.8 RWD64 dq 4059000000000000h ; 100 RWD72 dq 400921FB54442D18h ; 3.14159265 ; Total bytes of code 824 1216: JIT compiled Perfolizer.Mathematics.Distributions.StudentDistribution:StudentTwoTail(double,double) [Tier1, IL size=565, code size=824] ; Assembly listing for method Perfolizer.Mathematics.Common.MathExtensions:Sqr(double):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: fmul d0, d0, d0 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1217: JIT compiled Perfolizer.Mathematics.Common.MathExtensions:Sqr(double) [Tier1, IL size=4, code size=20] ; Assembly listing for method System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:MoveNext():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 0 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr x1, [x0] mov x2, x1 ldr w3, [x0, #0x0C] ldr w4, [x2, #0x14] cmp w3, w4 bne G_M000_IG07 G_M000_IG03: ldr w3, [x0, #0x08] ldr w4, [x2, #0x10] cmp w3, w4 bhs G_M000_IG05 ldr x1, [x2, #0x08] ldr w2, [x1, #0x08] cmp w3, w2 bhs G_M000_IG08 ubfiz x2, x3, #5, #32 add x2, x2, #16 add x1, x1, x2 ldp q16, q17, [x1] stp q16, q17, [x0, #0x10] ldr w1, [x0, #0x08] add w1, w1, #1 str w1, [x0, #0x08] mov w0, #1 G_M000_IG04: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG05: ldr w1, [x1, #0x10] add w1, w1, #1 str w1, [x0, #0x08] stp xzr, xzr, [x0, #0x10] stp xzr, xzr, [x0, #0x20] mov w0, wzr G_M000_IG06: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG07: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 G_M000_IG08: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 172 1218: JIT compiled System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:MoveNext() [Tier1, IL size=81, code size=172] ; Assembly listing for method System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:get_Current():BenchmarkDotNet.Reports.Measurement:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldp q16, q17, [x0, #0x10] stp q16, q17, [x8] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 24 1219: JIT compiled System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:get_Current() [Tier1, IL size=7, code size=24] ; Assembly listing for method System.Runtime.InteropServices.MemoryMarshal:GetReference[BenchmarkDotNet.Reports.Measurement](System.Span`1[BenchmarkDotNet.Reports.Measurement]):byref ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 16 1220: JIT compiled System.Runtime.InteropServices.MemoryMarshal:GetReference[BenchmarkDotNet.Reports.Measurement](System.Span`1[BenchmarkDotNet.Reports.Measurement]) [Tier1, IL size=8, code size=16] ; Assembly listing for method BenchmarkDotNet.Mathematics.MeasurementsStatistics:IsOutlier(int,double,double,double):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x20]! stp x19, x20, [sp, #0x10] mov fp, sp mov w19, w0 G_M000_IG02: cmp w19, #3 bhi G_M000_IG11 mov w0, w19 adr x1, [@RWD00] ldr w1, [x1, x0, LSL #2] adr x2, [G_M000_IG02] add x1, x1, x2 br x1 G_M000_IG03: mov w0, wzr G_M000_IG04: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG05: fcmp d0, d2 cset x1, gt b G_M000_IG09 G_M000_IG06: fcmp d0, d1 cset x1, lo b G_M000_IG09 G_M000_IG07: fcmp d0, d1 bhs G_M000_IG05 mov w0, #1 G_M000_IG08: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG09: uxtb w0, w1 G_M000_IG10: ldp x19, x20, [sp, #0x10] ldp fp, lr, [sp], #0x20 ret lr G_M000_IG11: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x20, x0 str w19, [x20, #0x08] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST mov x19, x0 mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS mov x1, x0 mov x2, x20 mov x0, x19 mov x3, xzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 mov x0, x19 bl CORINFO_HELP_THROW brk_windows #0 RWD00 dd G_M000_IG03 - G_M000_IG02 dd G_M000_IG05 - G_M000_IG02 dd G_M000_IG06 - G_M000_IG02 dd G_M000_IG07 - G_M000_IG02 ; Total bytes of code 240 1221: JIT compiled BenchmarkDotNet.Mathematics.MeasurementsStatistics:IsOutlier(int,double,double,double) [Tier1, IL size=65, code size=240] ; Assembly listing for method Perfolizer.Mathematics.Common.ConfidenceInterval:get_Margin():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr d0, [x0, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 20 1222: JIT compiled Perfolizer.Mathematics.Common.ConfidenceInterval:get_Margin() [Tier1, IL size=7, code size=20] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:CompareTo(BenchmarkDotNet.Reports.Measurement):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 4 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr d16, [x0, #0x18] ldr d17, [x1, #0x18] fcmp d16, d17 bhs G_M000_IG04 G_M000_IG03: movn w0, #0 b G_M000_IG08 G_M000_IG04: fcmp d16, d17 bgt G_M000_IG07 fcmp d16, d17 bne G_M000_IG06 G_M000_IG05: mov w0, wzr b G_M000_IG08 G_M000_IG06: fcmp d16, d16 beq G_M000_IG07 fcmp d17, d17 bne G_M000_IG05 b G_M000_IG03 G_M000_IG07: mov w0, #1 G_M000_IG08: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 88 1223: JIT compiled BenchmarkDotNet.Reports.Measurement:CompareTo(BenchmarkDotNet.Reports.Measurement) [Tier1, IL size=22, code size=88] ; Assembly listing for method System.Double:CompareTo(double):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 2 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr d16, [x0] fcmp d16, d0 blo G_M000_IG04 G_M000_IG03: fcmp d16, d0 bgt G_M000_IG08 fcmp d16, d0 beq G_M000_IG06 fcmp d16, d16 beq G_M000_IG08 fcmp d0, d0 bne G_M000_IG06 G_M000_IG04: movn w0, #0 G_M000_IG05: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG06: mov w0, wzr G_M000_IG07: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG08: mov w0, #1 G_M000_IG09: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 88 1224: JIT compiled System.Double:CompareTo(double) [Tier1, IL size=44, code size=88] ; Assembly listing for method System.Collections.Generic.GenericArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:LessThan(byref,byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 5 single block inlinees; 1 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp G_M000_IG02: ldp q16, q17, [x1] stp q16, q17, [fp, #0x10] ldr d16, [x0, #0x18] ldr d17, [fp, #0x28] fcmp d16, d17 blo G_M000_IG06 G_M000_IG03: fcmp d16, d17 bgt G_M000_IG04 fcmp d16, d17 beq G_M000_IG04 fcmp d16, d16 beq G_M000_IG04 fcmp d17, d17 beq G_M000_IG06 G_M000_IG04: mov w0, wzr G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG06: mov w0, #1 G_M000_IG07: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 88 1225: JIT compiled System.Collections.Generic.GenericArraySortHelper`1[BenchmarkDotNet.Reports.Measurement]:LessThan(byref,byref) [Tier1, IL size=834, code size=88] ; Assembly listing for method System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:GetEnumerator():System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] G_M000_IG02: str x0, [fp, #0x10] ldr w14, [x0, #0x14] str w14, [fp, #0x1C] stp xzr, xzr, [fp, #0x20] stp xzr, xzr, [fp, #0x30] mov x14, x8 add x13, fp, #16 bl CORINFO_HELP_ASSIGN_BYREF ldp x12, x15, [x13], #0x10 stp x12, x15, [x14], #0x10 ldp x12, x15, [x13], #0x10 stp x12, x15, [x14], #0x10 ldr x12, [x13], #0x08 str x12, [x14], #0x08 G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 88 1226: JIT compiled System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:GetEnumerator() [Tier1, IL size=7, code size=88] ; Assembly listing for method System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:.ctor(System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: mov x14, x0 mov x15, x1 bl CORINFO_HELP_CHECKED_ASSIGN_REF str wzr, [x0, #0x08] ldr w1, [x1, #0x14] str w1, [x0, #0x0C] stp xzr, xzr, [x0, #0x10] stp xzr, xzr, [x0, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 48 1227: JIT compiled System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:.ctor(System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]) [Tier1, IL size=39, code size=48] ; Assembly listing for method System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:Dispose():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 16 1228: JIT compiled System.Collections.Generic.List`1+Enumerator[BenchmarkDotNet.Reports.Measurement]:Dispose() [Tier1, IL size=1, code size=16] ; Assembly listing for method System.Number+BigInteger:ToUInt32():uint:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w1, [x0] cmp w1, #0 ble G_M000_IG05 G_M000_IG03: ldr w0, [x0, #0x04] G_M000_IG04: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG05: mov w0, wzr G_M000_IG06: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 44 1229: JIT compiled System.Number+BigInteger:ToUInt32() [Tier1, IL size=24, code size=44] ; Assembly listing for method System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:get_Item(int):BenchmarkDotNet.Reports.Measurement:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w2, [x0, #0x10] cmp w1, w2 bhs G_M000_IG04 ldr x0, [x0, #0x08] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG05 ubfiz x1, x1, #5, #32 add x1, x1, #16 add x0, x0, x1 ldp q16, q17, [x0] stp q16, q17, [x8] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 G_M000_IG05: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 96 1230: JIT compiled System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement]:get_Item(int) [Tier1, IL size=27, code size=96] ; Assembly listing for method BenchmarkDotNet.Engines.HostExtensions:AfterMainRun(BenchmarkDotNet.Engines.IHost) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 mov w1, #3 ldr x2, [x11] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 48 1231: JIT compiled BenchmarkDotNet.Engines.HostExtensions:AfterMainRun(BenchmarkDotNet.Engines.IHost) [Tier0, IL size=8, code size=48] ; Assembly listing for method Perfolizer.Mathematics.Common.ConfidenceInterval:.ctor(double,double,int,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data ; 0 inlinees with PGO data; 2 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x30]! str d8, [sp, #0x20] str x19, [sp, #0x28] mov fp, sp mov x19, x0 fmov d8, d0 G_M000_IG02: str w1, [x19] str d8, [x19, #0x08] str d1, [fp, #0x18] str d1, [x19, #0x10] str w2, [x19, #0x18] cmp w1, #2 ble G_M000_IG04 G_M000_IG03: mov w0, w2 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr d1, [fp, #0x18] fmul d16, d0, d1 b G_M000_IG05 G_M000_IG04: ldr d16, [@RWD00] G_M000_IG05: str d16, [x19, #0x20] ldr d16, [x19, #0x20] fsub d16, d8, d16 str d16, [x19, #0x28] ldr d16, [x19, #0x20] fadd d16, d8, d16 str d16, [x19, #0x30] G_M000_IG06: ldr x19, [sp, #0x28] ldr d8, [sp, #0x20] ldp fp, lr, [sp], #0x30 ret lr RWD00 dq FFF8000000000000h ; -nan(ind) ; Total bytes of code 136 1232: JIT compiled Perfolizer.Mathematics.Common.ConfidenceInterval:.ctor(double,double,int,int) [Tier1, IL size=89, code size=136] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:GetExtraStats(BenchmarkDotNet.Engines.IterationData):System.ValueTuple`3[BenchmarkDotNet.Engines.GcStats,BenchmarkDotNet.Engines.ThreadingStats,double]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: sub sp, sp, #0xD1FFAB1E stp fp, lr, [sp] mov fp, sp movi v16.16b, #0 add x9, fp, #80 add x10, fp, #0xD1FFAB1E stp q16, q16, [x9, #-0x40] stp q16, q16, [x9, #-0x20] bfm x9, xzr, #0, #5 dczva x9 add x9, x9, #64 cmp x9, x10 blo pc-16 (-4 instructions) stp q16, q16, [x10] stp q16, q16, [x10, #0x20] str x0, [fp, #0xD1FFAB1E] str x1, [fp, #0xD1FFAB1E] str x8, [fp, #0xD1FFAB1E] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] ldr x1, [fp, #0x18] ldr x1, [x1, #0x18] blr x1 add x8, fp, #0xD1FFAB1E movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 add x8, fp, #0xD1FFAB1E movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 sxtw x1, w0 ldr x0, [fp, #0xD1FFAB1E] cmp x1, #0 beq G_M000_IG12 cmn x1, #1 bne G_M000_IG03 cmp x0, #1 bvs G_M000_IG11 G_M000_IG03: sdiv x1, x0, x1 str x1, [fp, #0xD8] ldr x1, [fp, #0xD8] ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x08] ldr x2, [fp, #0xD1FFAB1E] ldr x2, [x2, #0x18] blr x2 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 add x8, fp, #0xD1FFAB1E movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 add x8, fp, #0xD1FFAB1E movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x08] ldr x1, [fp, #0x10] ldr x1, [x1, #0x18] blr x1 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0xD1FFAB1E] mul x0, x0, x1 str x0, [fp, #0xD1FFAB1E] ldp x0, x1, [fp, #0xD1FFAB1E] stp x0, x1, [fp, #0xB8] ldp x0, x1, [fp, #0xD1FFAB1E] stp x0, x1, [fp, #0xC8] G_M000_IG04: add x0, fp, #0xD1FFAB1E ldp x1, x8, [x0, #0x98] stp x1, x8, [fp, #0x98] ldp x1, x8, [x0, #0xA8] stp x1, x8, [fp, #0xA8] G_M000_IG05: add x0, fp, #184 add x1, fp, #152 add x8, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #0xD1FFAB1E add x8, fp, #0xD1FFAB1E ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldp x0, x1, [fp, #0xD1FFAB1E] stp x0, x1, [fp, #0x80] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x90] G_M000_IG06: add x0, fp, #0xD1FFAB1E ldp x1, x8, [x0, #0x68] stp x1, x8, [fp, #0x68] ldr x1, [x0, #0x78] str x1, [fp, #0x78] G_M000_IG07: add x0, fp, #128 add x1, fp, #104 add x8, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0xD1FFAB1E] mul x1, x0, x1 str x1, [fp, #0x60] ldr x1, [fp, #0x60] add x8, fp, #0xD1FFAB1E add x0, fp, #0xD1FFAB1E movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movi v16.16b, #0 stp q16, q16, [fp, #0xE0] stp q16, q16, [fp, #0xD1FFAB1E] G_M000_IG08: add x0, fp, #232 ldp q16, q17, [x0, #0x40] stp q16, q17, [fp, #0x40] G_M000_IG09: ldp x0, x1, [fp, #0xD1FFAB1E] stp x0, x1, [fp, #0x28] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x38] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 scvtf d0, x0 ldr x1, [fp, #0xD1FFAB1E] scvtf d16, x1 fdiv d0, d0, d16 str d0, [fp, #0x20] ldr d0, [fp, #0x20] add x1, fp, #64 add x2, fp, #40 add x0, fp, #224 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xD1FFAB1E] ldp q16, q17, [fp, #0xE0] stp q16, q17, [x0] ldp q16, q17, [fp, #0xD1FFAB1E] stp q16, q17, [x0, #0x20] G_M000_IG10: ldp fp, lr, [sp] add sp, sp, #0xD1FFAB1E ret lr G_M000_IG11: bl CORINFO_HELP_OVERFLOW G_M000_IG12: bl CORINFO_HELP_THROWDIVZERO brk_windows #0 ; Total bytes of code 1032 1233: JIT compiled BenchmarkDotNet.Engines.Engine:GetExtraStats(BenchmarkDotNet.Engines.IterationData) [Tier0, IL size=179, code size=1032] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:EnableMonitoring() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG04 G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG05 mov w0, #1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG05: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 96 1234: JIT compiled BenchmarkDotNet.Engines.Engine:EnableMonitoring() [Tier0, IL size=22, code size=96] ; Assembly listing for method BenchmarkDotNet.Engines.ThreadingStats:ReadInitial():BenchmarkDotNet.Engines.ThreadingStats ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x40] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x8, [fp, #0x48] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] ldr x1, [fp, #0x18] ldr x1, [x1, #0x18] blr x1 str x0, [fp, #0x40] stp xzr, xzr, [fp, #0x28] str xzr, [fp, #0x38] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x08] ldr x1, [fp, #0x10] ldr x1, [x1, #0x18] blr x1 str x0, [fp, #0x20] ldr x1, [fp, #0x20] add x0, fp, #40 ldr x2, [fp, #0x40] mov x3, xzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x48] ldp x1, x2, [fp, #0x28] stp x1, x2, [x0] ldr x1, [fp, #0x38] str x1, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 224 1235: JIT compiled BenchmarkDotNet.Engines.ThreadingStats:ReadInitial() [Tier0, IL size=30, code size=224] ; Assembly listing for method BenchmarkDotNet.Engines.ThreadingStats:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 144 1236: JIT compiled BenchmarkDotNet.Engines.ThreadingStats:.cctor() [Tier0, IL size=51, code size=144] ; Assembly listing for method BenchmarkDotNet.Engines.ThreadingStats:CreateGetterDelegate(System.Type,System.String):System.Func`1[long] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str xzr, [x9, #0x30] str x0, [fp, #0x58] str x1, [fp, #0x50] G_M000_IG02: ldr x0, [fp, #0x58] ldr x1, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 str x0, [fp, #0x48] ldr x0, [fp, #0x48] mov x1, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x38] ldr x0, [fp, #0x38] str x0, [fp, #0x40] ldr x0, [fp, #0x38] cbnz x0, G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x28] ldr x1, [fp, #0x28] ldr x0, [fp, #0x30] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x30] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x30] G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG04: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x2, [fp, #0x20] ldr x2, [x2] ldr x2, [x2, #0x68] ldr x2, [x2, #0x10] blr x2 str x0, [fp, #0x18] ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x40] G_M000_IG05: ldr x0, [fp, #0x40] G_M000_IG06: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 436 1237: JIT compiled BenchmarkDotNet.Engines.ThreadingStats:CreateGetterDelegate(System.Type,System.String) [Tier0, IL size=76, code size=436] ; Assembly listing for method BenchmarkDotNet.Engines.ThreadingStats:.ctor(long,long,long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] str x3, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] str x1, [x0] ldr x0, [fp, #0x28] ldr x1, [fp, #0x18] str x1, [x0, #0x08] ldr x0, [fp, #0x28] ldr x1, [fp, #0x10] str x1, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 68 1238: JIT compiled BenchmarkDotNet.Engines.ThreadingStats:.ctor(long,long,long) [Tier0, IL size=22, code size=68] ; Assembly listing for method BenchmarkDotNet.Engines.ExceptionsStats:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 1239: JIT compiled BenchmarkDotNet.Engines.ExceptionsStats:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Engines.ExceptionsStats:StartListening():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 144 1240: JIT compiled BenchmarkDotNet.Engines.ExceptionsStats:StartListening() [Tier0, IL size=23, code size=144] ; Assembly listing for method BenchmarkDotNet.Engines.GcStats:ReadInitial():BenchmarkDotNet.Engines.GcStats ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x40] str x8, [fp, #0x48] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x40] mov w0, wzr movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x3C] mov w0, #1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x38] stp xzr, xzr, [fp, #0x18] stp xzr, xzr, [fp, #0x28] mov w0, #2 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x14] ldr w3, [fp, #0x14] add x0, fp, #24 ldr w1, [fp, #0x3C] ldr w2, [fp, #0x38] ldr x4, [fp, #0x40] mov x5, xzr movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x0, [fp, #0x48] G_M000_IG03: add x1, fp, #24 ldp q16, q17, [x1] stp q16, q17, [x0] G_M000_IG04: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 200 1241: JIT compiled BenchmarkDotNet.Engines.GcStats:ReadInitial() [Tier0, IL size=33, code size=200] ; Assembly listing for method BenchmarkDotNet.Engines.GcStats:GetAllocatedBytes():long ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG04 mov x0, xzr G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG06 mov x0, xzr G_M000_IG05: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 G_M000_IG07: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG08: mov w0, #1 bl System.GC:GetTotalAllocatedBytes(bool):long G_M000_IG09: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 192 1242: JIT compiled BenchmarkDotNet.Engines.GcStats:GetAllocatedBytes() [Tier0, IL size=50, code size=192] ; Assembly listing for method BenchmarkDotNet.Engines.ExceptionsStats:Stop():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x18] ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 144 1243: JIT compiled BenchmarkDotNet.Engines.ExceptionsStats:Stop() [Tier0, IL size=23, code size=144] ; Assembly listing for method BenchmarkDotNet.Engines.GcStats:ReadFinal():BenchmarkDotNet.Engines.GcStats ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str x8, [fp, #0x48] G_M000_IG02: mov w0, wzr movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x44] mov w0, #1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x40] mov w0, #2 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x3C] stp xzr, xzr, [fp, #0x18] stp xzr, xzr, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x10] ldr x4, [fp, #0x10] add x0, fp, #24 ldr w1, [fp, #0x44] ldr w2, [fp, #0x40] ldr w3, [fp, #0x3C] mov x5, xzr movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x0, [fp, #0x48] G_M000_IG03: add x1, fp, #24 ldp q16, q17, [x1] stp q16, q17, [x0] G_M000_IG04: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 196 1244: JIT compiled BenchmarkDotNet.Engines.GcStats:ReadFinal() [Tier0, IL size=31, code size=196] ; Assembly listing for method BenchmarkDotNet.Engines.ThreadingStats:ReadFinal():BenchmarkDotNet.Engines.ThreadingStats ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x40] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x8, [fp, #0x48] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] ldr x1, [fp, #0x18] ldr x1, [x1, #0x18] blr x1 str x0, [fp, #0x38] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x08] ldr x1, [fp, #0x10] ldr x1, [x1, #0x18] blr x1 str x0, [fp, #0x40] stp xzr, xzr, [fp, #0x20] str xzr, [fp, #0x30] add x0, fp, #32 ldr x1, [fp, #0x38] ldr x2, [fp, #0x40] mov x3, xzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x48] ldp x1, x2, [fp, #0x20] stp x1, x2, [x0] ldr x1, [fp, #0x30] str x1, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 184 1245: JIT compiled BenchmarkDotNet.Engines.ThreadingStats:ReadFinal() [Tier0, IL size=30, code size=184] ; Assembly listing for method BenchmarkDotNet.Engines.GcStats:op_Subtraction(BenchmarkDotNet.Engines.GcStats,BenchmarkDotNet.Engines.GcStats):BenchmarkDotNet.Engines.GcStats ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! mov fp, sp str x0, [fp, #0x90] str x1, [fp, #0x88] str x8, [fp, #0x98] G_M000_IG02: ldr x0, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x84] ldr x0, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w1, [fp, #0x84] sub w1, w1, w0 str w1, [fp, #0x34] ldr w1, [fp, #0x34] mov w0, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x80] ldr x0, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x7C] ldr x0, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w1, [fp, #0x7C] sub w1, w1, w0 str w1, [fp, #0x30] ldr w1, [fp, #0x30] mov w0, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x78] ldr x0, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x74] ldr x0, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w1, [fp, #0x74] sub w1, w1, w0 str w1, [fp, #0x2C] ldr w1, [fp, #0x2C] mov w0, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x70] ldr x0, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x68] ldr x0, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x68] sub x1, x1, x0 str x1, [fp, #0x20] ldr x1, [fp, #0x20] mov x0, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x60] ldr x0, [fp, #0x90] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x58] stp xzr, xzr, [fp, #0x38] stp xzr, xzr, [fp, #0x48] ldr x0, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x58] sub x1, x1, x0 str x1, [fp, #0x18] ldr x1, [fp, #0x18] mov x0, xzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x10] ldr x5, [fp, #0x10] add x0, fp, #56 ldr w1, [fp, #0x80] ldr w2, [fp, #0x78] ldr w3, [fp, #0x70] ldr x4, [fp, #0x60] movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x0, [fp, #0x98] G_M000_IG03: add x1, fp, #56 ldp q16, q17, [x1] stp q16, q17, [x0] G_M000_IG04: ldp fp, lr, [sp], #0xA0 ret lr ; Total bytes of code 576 1246: JIT compiled BenchmarkDotNet.Engines.GcStats:op_Subtraction(BenchmarkDotNet.Engines.GcStats,BenchmarkDotNet.Engines.GcStats) [Tier0, IL size=113, code size=576] ; Assembly listing for method BenchmarkDotNet.Engines.GcStats:get_Gen0Collections():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1247: JIT compiled BenchmarkDotNet.Engines.GcStats:get_Gen0Collections() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.GcStats:get_Gen1Collections():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x04] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1248: JIT compiled BenchmarkDotNet.Engines.GcStats:get_Gen1Collections() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.GcStats:get_Gen2Collections():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1249: JIT compiled BenchmarkDotNet.Engines.GcStats:get_Gen2Collections() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.GcStats:get_AllocatedBytes():long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1250: JIT compiled BenchmarkDotNet.Engines.GcStats:get_AllocatedBytes() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.GcStats:get_TotalOperations():long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1251: JIT compiled BenchmarkDotNet.Engines.GcStats:get_TotalOperations() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.GcStats:WithTotalOperations(long):BenchmarkDotNet.Engines.GcStats:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xB0]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0xA8] str x1, [fp, #0x98] str x8, [fp, #0xA0] G_M000_IG02: stp xzr, xzr, [fp, #0x78] stp xzr, xzr, [fp, #0x88] ldr x0, [fp, #0xA8] ldp x1, x5, [x0] stp x1, x5, [fp, #0x58] ldp x1, x5, [x0, #0x10] stp x1, x5, [fp, #0x68] add x0, fp, #120 ldr x5, [fp, #0x98] mov w1, wzr mov w2, wzr mov w3, wzr mov x4, xzr movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x8, [fp, #0xA0] str x8, [fp, #0x10] ldp x0, x1, [fp, #0x58] stp x0, x1, [fp, #0x38] ldp x0, x1, [fp, #0x68] stp x0, x1, [fp, #0x48] ldp x0, x1, [fp, #0x78] stp x0, x1, [fp, #0x18] ldp x0, x1, [fp, #0x88] stp x0, x1, [fp, #0x28] ldr x8, [fp, #0x10] add x0, fp, #56 add x1, fp, #24 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0xB0 ret lr ; Total bytes of code 176 1252: JIT compiled BenchmarkDotNet.Engines.GcStats:WithTotalOperations(long) [Tier0, IL size=23, code size=176] ; Assembly listing for method BenchmarkDotNet.Engines.GcStats:op_Addition(BenchmarkDotNet.Engines.GcStats,BenchmarkDotNet.Engines.GcStats):BenchmarkDotNet.Engines.GcStats ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp str x0, [fp, #0x70] str x1, [fp, #0x68] str x8, [fp, #0x78] G_M000_IG02: ldr x0, [fp, #0x70] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x64] ldr x0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w1, [fp, #0x64] add w0, w0, w1 str w0, [fp, #0x60] ldr x0, [fp, #0x70] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x5C] ldr x0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w1, [fp, #0x5C] add w0, w0, w1 str w0, [fp, #0x58] ldr x0, [fp, #0x70] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x54] ldr x0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w1, [fp, #0x54] add w0, w0, w1 str w0, [fp, #0x50] ldr x0, [fp, #0x70] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x48] ldr x0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x48] add x0, x0, x1 str x0, [fp, #0x40] ldr x0, [fp, #0x70] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x38] stp xzr, xzr, [fp, #0x18] stp xzr, xzr, [fp, #0x28] ldr x0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x5, [fp, #0x38] add x5, x0, x5 str x5, [fp, #0x10] ldr x5, [fp, #0x10] add x0, fp, #24 ldr w1, [fp, #0x60] ldr w2, [fp, #0x58] ldr w3, [fp, #0x50] ldr x4, [fp, #0x40] movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x0, [fp, #0x78] G_M000_IG03: add x1, fp, #24 ldp q16, q17, [x1] stp q16, q17, [x0] G_M000_IG04: ldp fp, lr, [sp], #0x80 ret lr ; Total bytes of code 416 1253: JIT compiled BenchmarkDotNet.Engines.GcStats:op_Addition(BenchmarkDotNet.Engines.GcStats,BenchmarkDotNet.Engines.GcStats) [Tier0, IL size=81, code size=416] ; Assembly listing for method BenchmarkDotNet.Engines.ThreadingStats:op_Subtraction(BenchmarkDotNet.Engines.ThreadingStats,BenchmarkDotNet.Engines.ThreadingStats):BenchmarkDotNet.Engines.ThreadingStats ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp str x0, [fp, #0x60] str x1, [fp, #0x58] str x8, [fp, #0x68] G_M000_IG02: ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x50] ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x50] sub x0, x1, x0 str x0, [fp, #0x48] ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x40] ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x40] sub x0, x1, x0 str x0, [fp, #0x38] ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x30] stp xzr, xzr, [fp, #0x18] str xzr, [fp, #0x28] ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x3, [fp, #0x30] sub x3, x3, x0 str x3, [fp, #0x10] ldr x3, [fp, #0x10] add x0, fp, #24 ldr x1, [fp, #0x48] ldr x2, [fp, #0x38] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x68] ldp x1, x2, [fp, #0x18] stp x1, x2, [x0] ldr x1, [fp, #0x28] str x1, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 284 1254: JIT compiled BenchmarkDotNet.Engines.ThreadingStats:op_Subtraction(BenchmarkDotNet.Engines.ThreadingStats,BenchmarkDotNet.Engines.ThreadingStats) [Tier0, IL size=51, code size=284] ; Assembly listing for method BenchmarkDotNet.Engines.ThreadingStats:get_CompletedWorkItemCount():long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1255: JIT compiled BenchmarkDotNet.Engines.ThreadingStats:get_CompletedWorkItemCount() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.ThreadingStats:get_LockContentionCount():long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1256: JIT compiled BenchmarkDotNet.Engines.ThreadingStats:get_LockContentionCount() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.ThreadingStats:get_TotalOperations():long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1257: JIT compiled BenchmarkDotNet.Engines.ThreadingStats:get_TotalOperations() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.ThreadingStats:WithTotalOperations(long):BenchmarkDotNet.Engines.ThreadingStats:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str x0, [fp, #0x48] str x1, [fp, #0x38] str x8, [fp, #0x40] G_M000_IG02: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x30] stp xzr, xzr, [fp, #0x18] str xzr, [fp, #0x28] ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x2, [fp, #0x10] add x0, fp, #24 ldr x1, [fp, #0x30] ldr x3, [fp, #0x38] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x40] ldp x1, x2, [fp, #0x18] stp x1, x2, [x0] ldr x1, [fp, #0x28] str x1, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 148 1258: JIT compiled BenchmarkDotNet.Engines.ThreadingStats:WithTotalOperations(long) [Tier0, IL size=19, code size=148] ; Assembly listing for method BenchmarkDotNet.Engines.ExceptionsStats:get_ExceptionsCount():long:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1259: JIT compiled BenchmarkDotNet.Engines.ExceptionsStats:get_ExceptionsCount() [Tier0, IL size=7, code size=28] ; Assembly listing for method System.ValueTuple`3[BenchmarkDotNet.Engines.GcStats,BenchmarkDotNet.Engines.ThreadingStats,double]:.ctor(BenchmarkDotNet.Engines.GcStats,BenchmarkDotNet.Engines.ThreadingStats,double):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] str d0, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x20] ldr x1, [fp, #0x28] ldp x2, x3, [x0] stp x2, x3, [x1, #0x08] ldp x2, x3, [x0, #0x10] stp x2, x3, [x1, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldp x2, x3, [x0] stp x2, x3, [x1, #0x28] ldr x2, [x0, #0x10] str x2, [x1, #0x38] ldr x0, [fp, #0x28] ldr d16, [fp, #0x10] str d16, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 92 1260: JIT compiled System.ValueTuple`3[BenchmarkDotNet.Engines.GcStats,BenchmarkDotNet.Engines.ThreadingStats,double]:.ctor(BenchmarkDotNet.Engines.GcStats,BenchmarkDotNet.Engines.ThreadingStats,double) [Tier0, IL size=22, code size=92] ; Assembly listing for method BenchmarkDotNet.Engines.EngineEventSource:BenchmarkStop(System.String):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x2, [fp, #0x10] mov w1, #2 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 1261: JIT compiled BenchmarkDotNet.Engines.EngineEventSource:BenchmarkStop(System.String) [Tier0, IL size=9, code size=56] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults:.ctor(System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Reports.Measurement],int,BenchmarkDotNet.Engines.GcStats,BenchmarkDotNet.Engines.ThreadingStats,double):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x1, [fp, #0x30] str w2, [fp, #0x2C] str x3, [fp, #0x20] str x4, [fp, #0x18] str d0, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x38] ldr w15, [fp, #0x2C] str w15, [x14, #0x10] ldr x14, [fp, #0x38] ldr x15, [fp, #0x30] bl CORINFO_HELP_CHECKED_ASSIGN_REF ldr x0, [fp, #0x20] ldr x1, [fp, #0x38] ldp x2, x3, [x0] stp x2, x3, [x1, #0x18] ldp x2, x3, [x0, #0x10] stp x2, x3, [x1, #0x28] ldr x0, [fp, #0x18] ldr x1, [fp, #0x38] ldp x2, x3, [x0] stp x2, x3, [x1, #0x38] ldr x2, [x0, #0x10] str x2, [x1, #0x48] ldr x0, [fp, #0x38] ldr d16, [fp, #0x10] str d16, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 124 1262: JIT compiled BenchmarkDotNet.Engines.RunResults:.ctor(System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Reports.Measurement],int,BenchmarkDotNet.Engines.GcStats,BenchmarkDotNet.Engines.ThreadingStats,double) [Tier0, IL size=38, code size=124] ; Assembly listing for method BenchmarkDotNet.Engines.AnonymousPipesHost:ReportResults(BenchmarkDotNet.Engines.RunResults):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x1, [fp, #0x18] ldr x1, [x1, #0x08] ldr x0, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 1263: JIT compiled BenchmarkDotNet.Engines.AnonymousPipesHost:ReportResults(BenchmarkDotNet.Engines.RunResults) [Tier0, IL size=14, code size=56] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults:Print(System.IO.TextWriter):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! mov fp, sp movi v16.16b, #0 sub x9, fp, #16 mov x10, #168 stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40]! subs x10, x10, #64 bge pc-16 (-4 instructions) stp q16, q16, [x9, #0x20] str xzr, [x9, #0x40] add x2, sp, #0xD1FFAB1E str x2, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] str x1, [fp, #0xF8] G_M000_IG02: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x70] ldr x0, [fp, #0x70] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0xF0] mov w0, #0xD1FFAB1E str w0, [fp, #0x78] G_M000_IG03: b G_M000_IG05 G_M000_IG04: add x8, fp, #208 ldr x0, [fp, #0xF0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 add x0, fp, #208 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x68] ldr x1, [fp, #0x68] ldr x0, [fp, #0xF8] ldr x2, [fp, #0xF8] ldr x2, [x2] ldr x2, [x2, #0x68] ldr x2, [x2, #0x30] blr x2 G_M000_IG05: ldr w0, [fp, #0x78] sub w0, w0, #1 str w0, [fp, #0x78] ldr w0, [fp, #0x78] cmp w0, #0 bgt G_M000_IG07 G_M000_IG06: add x0, fp, #120 mov w1, #40 bl CORINFO_HELP_PATCHPOINT G_M000_IG07: ldr x0, [fp, #0xF0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG04 b G_M000_IG08 G_M000_IG08: ldr x0, [fp, #0xD1FFAB1E] bl G_M000_IG15 G_M000_IG09: nop G_M000_IG10: add x8, fp, #176 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldp x0, x2, [x1] stp x0, x2, [fp, #0x48] ldp x0, x2, [x1, #0x10] stp x0, x2, [fp, #0x58] add x1, fp, #72 add x0, fp, #176 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG11 add x8, fp, #176 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 add x0, fp, #176 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x40] ldr x1, [fp, #0x40] ldr x0, [fp, #0xF8] ldr x2, [fp, #0xF8] ldr x2, [x2] ldr x2, [x2, #0x68] ldr x2, [x2, #0x30] blr x2 G_M000_IG11: add x8, fp, #152 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 add x8, fp, #128 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldp x0, x1, [fp, #0x80] stp x0, x1, [fp, #0x28] ldr x0, [fp, #0x90] str x0, [fp, #0x38] add x1, fp, #40 add x0, fp, #152 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG12 add x8, fp, #152 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 add x0, fp, #152 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0xF8] ldr x2, [fp, #0xF8] ldr x2, [x2] ldr x2, [x2, #0x68] ldr x2, [x2, #0x30] blr x2 G_M000_IG12: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 fcmp d0, #0.0 ble G_M000_IG13 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x18] ldr d0, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0xF8] ldr x2, [fp, #0xF8] ldr x2, [x2] ldr x2, [x2, #0x68] ldr x2, [x2, #0x30] blr x2 G_M000_IG13: ldr x0, [fp, #0xF8] ldr x1, [fp, #0xF8] ldr x1, [x1] ldr x1, [x1, #0x60] ldr x1, [x1, #0x08] blr x1 G_M000_IG14: ldp fp, lr, [sp], #0xD1FFAB1E ret lr G_M000_IG15: stp fp, lr, [sp, #-0x20]! add x3, fp, #0xD1FFAB1E str x3, [sp, #0x18] G_M000_IG16: ldr x0, [fp, #0xF0] cbz x0, G_M000_IG17 ldr x0, [fp, #0xF0] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG17: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 848 1264: JIT compiled BenchmarkDotNet.Engines.RunResults:Print(System.IO.TextWriter) [Tier0, IL size=183, code size=848] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults:GetWorkloadResultMeasurements():System.Collections.Generic.IEnumerable`1[BenchmarkDotNet.Reports.Measurement]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] movn w1, #1 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x13, [fp, #0x18] ldr x14, [fp, #0x10] add x14, x14, #160 bl CORINFO_HELP_ASSIGN_BYREF ldp x12, x15, [x13], #0x10 stp x12, x15, [x14], #0x10 ldp x12, x15, [x13], #0x10 stp x12, x15, [x14], #0x10 ldp x12, x15, [x13], #0x10 stp x12, x15, [x14], #0x10 ldp x12, x15, [x13], #0x10 stp x12, x15, [x14], #0x10 ldr x12, [x13], #0x08 str x12, [x14], #0x08 ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 132 1265: JIT compiled BenchmarkDotNet.Engines.RunResults:GetWorkloadResultMeasurements() [Tier0, IL size=20, code size=132] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults+d__18:.ctor(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x18] ldr w1, [fp, #0x14] str w1, [x0, #0x20] bl System.Environment:get_CurrentManagedThreadId():int ldr x1, [fp, #0x18] str w0, [x1, #0x24] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 72 1266: JIT compiled BenchmarkDotNet.Engines.RunResults+d__18:.ctor(int) [Tier0, IL size=25, code size=72] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults+d__18:System.Collections.Generic.IEnumerable.GetEnumerator():System.Collections.Generic.IEnumerator`1[BenchmarkDotNet.Reports.Measurement]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] ldr w0, [x0, #0x20] cmn w0, #2 bne G_M000_IG03 ldr x0, [fp, #0x28] ldr w0, [x0, #0x24] str w0, [fp, #0x14] bl System.Environment:get_CurrentManagedThreadId():int ldr w1, [fp, #0x14] cmp w0, w1 bne G_M000_IG03 ldr x0, [fp, #0x28] str wzr, [x0, #0x20] ldr x0, [fp, #0x28] str x0, [fp, #0x20] b G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] mov w1, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x13, [fp, #0x18] str x13, [fp, #0x20] G_M000_IG04: ldr x13, [fp, #0x28] add x13, x13, #160 ldr x14, [fp, #0x20] add x14, x14, #80 bl CORINFO_HELP_ASSIGN_BYREF ldp x12, x15, [x13], #0x10 stp x12, x15, [x14], #0x10 ldp x12, x15, [x13], #0x10 stp x12, x15, [x14], #0x10 ldp x12, x15, [x13], #0x10 stp x12, x15, [x14], #0x10 ldp x12, x15, [x13], #0x10 stp x12, x15, [x14], #0x10 ldr x12, [x13], #0x08 str x12, [x14], #0x08 ldr x0, [fp, #0x20] G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 212 1267: JIT compiled BenchmarkDotNet.Engines.RunResults+d__18:System.Collections.Generic.IEnumerable.GetEnumerator() [Tier0, IL size=55, code size=212] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults+d__18:MoveNext():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! mov fp, sp movi v16.16b, #0 add x9, fp, #104 add x10, fp, #0xD1FFAB1E stp q16, q16, [x9, #-0x40] stp q16, q16, [x9, #-0x20] bfm x9, xzr, #0, #5 dczva x9 add x9, x9, #64 cmp x9, x10 blo pc-16 (-4 instructions) stp q16, q16, [x10] stp q16, q16, [x10, #0x20] add x1, sp, #0xD1FFAB1E str x1, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] G_M000_IG02: ldr x0, [fp, #0xD1FFAB1E] ldr w0, [x0, #0x20] str w0, [fp, #0xD1FFAB1E] mov w0, #0xD1FFAB1E str w0, [fp, #0x48] ldr w0, [fp, #0xD1FFAB1E] cbz w0, G_M000_IG03 ldr w0, [fp, #0xD1FFAB1E] cmp w0, #1 beq G_M000_IG14 str wzr, [fp, #0xD1FFAB1E] b G_M000_IG18 G_M000_IG03: ldr x0, [fp, #0xD1FFAB1E] movn w1, #0 str w1, [x0, #0x20] ldr x0, [fp, #0xD1FFAB1E] ldrsb wzr, [x0] ldr x0, [fp, #0xD1FFAB1E] add x0, x0, #80 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xF8] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0xF8] G_M000_IG04: ldr x0, [fp, #0xF8] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] ldrsb wzr, [x0] ldr x0, [fp, #0xD1FFAB1E] add x0, x0, #80 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG05 str wzr, [fp, #0xD1FFAB1E] b G_M000_IG18 G_M000_IG05: ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xF0] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG07 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x78] ldr x0, [fp, #0xF0] str x0, [fp, #0x70] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x68] ldr x0, [fp, #0x78] str x0, [fp, #0x60] ldr x0, [fp, #0x78] cbnz x0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x50] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x40] ldr x1, [fp, #0x40] ldr x0, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x50] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x50] str x0, [fp, #0x60] G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x58] ldr x0, [fp, #0x68] ldr x1, [fp, #0x60] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x38] ldr x1, [fp, #0x38] ldr x0, [fp, #0x58] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x70] str x0, [fp, #0xE8] ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0xE0] b G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0xF0] str x0, [fp, #0xE8] str xzr, [fp, #0xE0] G_M000_IG08: ldr x0, [fp, #0xE8] ldr d16, [fp, #0xE0] str d16, [x0, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD8] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD0] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xC8] ldr x0, [fp, #0xD8] str x0, [fp, #0xC0] ldr x0, [fp, #0xD8] cbnz x0, G_M000_IG09 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x80] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x30] ldr x1, [fp, #0x30] ldr x0, [fp, #0x80] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x80] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x80] str x0, [fp, #0xC0] G_M000_IG09: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xB8] ldr x0, [fp, #0xC8] ldr x1, [fp, #0xC0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x28] ldr x1, [fp, #0x28] ldr x0, [fp, #0xB8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0xD0] add x14, x14, #8 ldr x15, [fp, #0xB8] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0xD1FFAB1E] str wzr, [x0, #0x28] ldr x0, [fp, #0xD1FFAB1E] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 ldr x14, [fp, #0xD1FFAB1E] add x14, x14, #16 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0xD1FFAB1E] movn w1, #2 str w1, [x0, #0x20] b G_M000_IG15 G_M000_IG10: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] add x8, fp, #0xD1FFAB1E movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x08] str x0, [fp, #0xB0] add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x20] ldr d0, [fp, #0x20] ldr x1, [fp, #0xD1FFAB1E] add x1, x1, #80 ldr w1, [x1, #0x10] ldr x0, [fp, #0xB0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 cbnz w0, G_M000_IG15 add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] ldr d1, [x0, #0x18] fsub d1, d0, d1 str d1, [fp, #0x18] ldr d1, [fp, #0x18] movi v0.16b, #0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0xD1FFAB1E] ldr d0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cbz w0, G_M000_IG11 str xzr, [fp, #0xD1FFAB1E] G_M000_IG11: add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0xAC] ldr x0, [fp, #0xD1FFAB1E] ldr w0, [x0, #0x28] add w0, w0, #1 str w0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] ldr w1, [fp, #0xD1FFAB1E] str w1, [x0, #0x28] stp xzr, xzr, [fp, #0x88] stp xzr, xzr, [fp, #0x98] add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x5, [fp, #0x10] add x0, fp, #136 ldr w1, [fp, #0xAC] ldr d0, [fp, #0xD1FFAB1E] ldr w4, [fp, #0xD1FFAB1E] mov w2, #1 mov w3, #4 movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x0, [fp, #0xD1FFAB1E] G_M000_IG12: add x1, fp, #88 ldp q16, q17, [x1, #0x30] stp q16, q17, [x0, #0x30] G_M000_IG13: ldr x0, [fp, #0xD1FFAB1E] mov w1, #1 str w1, [x0, #0x20] mov w1, #1 str w1, [fp, #0xD1FFAB1E] b G_M000_IG18 G_M000_IG14: ldr x0, [fp, #0xD1FFAB1E] movn w1, #2 str w1, [x0, #0x20] G_M000_IG15: ldr w0, [fp, #0x48] sub w0, w0, #1 str w0, [fp, #0x48] ldr w0, [fp, #0x48] cmp w0, #0 bgt G_M000_IG17 G_M000_IG16: add x0, fp, #72 mov w1, #0xD1FFAB1E bl CORINFO_HELP_PATCHPOINT G_M000_IG17: ldr x0, [fp, #0xD1FFAB1E] ldr x0, [x0, #0x10] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG10 ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] str xzr, [x0, #0x10] str wzr, [fp, #0xD1FFAB1E] b G_M000_IG18 G_M000_IG18: ldr w0, [fp, #0xD1FFAB1E] G_M000_IG19: ldp fp, lr, [sp], #0xD1FFAB1E ret lr G_M000_IG20: stp fp, lr, [sp, #-0x20]! add x3, fp, #0xD1FFAB1E str x3, [sp, #0x18] G_M000_IG21: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG22: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 1652 1268: JIT compiled BenchmarkDotNet.Engines.RunResults+d__18:MoveNext() [Tier0, IL size=435, code size=1652] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults:get_Overhead():System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Reports.Measurement]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x0, [fp, #0x48] G_M000_IG02: ldr x0, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x38] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x40] ldr x0, [fp, #0x38] str x0, [fp, #0x30] ldr x0, [fp, #0x40] str x0, [fp, #0x28] ldr x0, [fp, #0x40] cbnz x0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x20] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x20] str x0, [fp, #0x28] G_M000_IG03: ldr x0, [fp, #0x30] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 324 1269: JIT compiled BenchmarkDotNet.Engines.RunResults:get_Overhead() [Tier0, IL size=48, code size=324] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults:get_EngineMeasurements():System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Reports.Measurement]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1270: JIT compiled BenchmarkDotNet.Engines.RunResults:get_EngineMeasurements() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults+<>c:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 1271: JIT compiled BenchmarkDotNet.Engines.RunResults+<>c:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults+<>c:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 1272: JIT compiled BenchmarkDotNet.Engines.RunResults+<>c:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Linq.Enumerable:Where[BenchmarkDotNet.Reports.Measurement](System.Collections.Generic.IEnumerable`1[BenchmarkDotNet.Reports.Measurement],System.Func`2[BenchmarkDotNet.Reports.Measurement,bool]):System.Collections.Generic.IEnumerable`1[BenchmarkDotNet.Reports.Measurement] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] str x0, [fp, #0x58] str x1, [fp, #0x50] G_M000_IG02: ldr x0, [fp, #0x58] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x50] cbnz x0, G_M000_IG04 mov w0, #12 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldr x1, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x48] ldr x0, [fp, #0x48] cbz x0, G_M000_IG05 ldr x0, [fp, #0x48] ldr x1, [fp, #0x50] ldr x2, [fp, #0x48] ldr x2, [x2] ldr x2, [x2, #0x48] ldr x2, [x2, #0x10] blr x2 str x0, [fp, #0x10] b G_M000_IG09 G_M000_IG05: ldr x1, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x40] ldr x0, [fp, #0x40] cbz x0, G_M000_IG07 ldr x0, [fp, #0x40] ldr w0, [x0, #0x08] cbz w0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x40] ldr x2, [fp, #0x50] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] str x0, [fp, #0x30] ldr x0, [fp, #0x30] str x0, [fp, #0x10] b G_M000_IG09 G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x10] b G_M000_IG09 G_M000_IG07: ldr x1, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x38] ldr x0, [fp, #0x38] cbz x0, G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x38] ldr x2, [fp, #0x50] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x20] str x0, [fp, #0x10] b G_M000_IG09 G_M000_IG08: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x1, [fp, #0x58] ldr x2, [fp, #0x50] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x28] str x0, [fp, #0x10] b G_M000_IG09 G_M000_IG09: ldr x0, [fp, #0x10] G_M000_IG10: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 528 1273: JIT compiled System.Linq.Enumerable:Where[BenchmarkDotNet.Reports.Measurement](System.Collections.Generic.IEnumerable`1[BenchmarkDotNet.Reports.Measurement],System.Func`2[BenchmarkDotNet.Reports.Measurement,bool]) [Tier0, IL size=94, code size=528] ; Assembly listing for method System.Linq.Enumerable+WhereListIterator`1[BenchmarkDotNet.Reports.Measurement]:.ctor(System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement],System.Func`2[BenchmarkDotNet.Reports.Measurement,bool]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] add x14, x14, #48 ldr x15, [fp, #0x20] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x28] add x14, x14, #56 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 1274: JIT compiled System.Linq.Enumerable+WhereListIterator`1[BenchmarkDotNet.Reports.Measurement]:.ctor(System.Collections.Generic.List`1[BenchmarkDotNet.Reports.Measurement],System.Func`2[BenchmarkDotNet.Reports.Measurement,bool]) [Tier0, IL size=21, code size=84] ; Assembly listing for method System.Linq.Enumerable+Iterator`1[BenchmarkDotNet.Reports.Measurement]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 bl System.Environment:get_CurrentManagedThreadId():int ldr x1, [fp, #0x18] str w0, [x1, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 1275: JIT compiled System.Linq.Enumerable+Iterator`1[BenchmarkDotNet.Reports.Measurement]:.ctor() [Tier0, IL size=18, code size=56] ; Assembly listing for method System.Linq.Enumerable:ToArray[BenchmarkDotNet.Reports.Measurement](System.Collections.Generic.IEnumerable`1[BenchmarkDotNet.Reports.Measurement]):BenchmarkDotNet.Reports.Measurement[] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x10] ldr x0, [fp, #0x10] cbnz x0, G_M000_IG05 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG05: ldr x0, [fp, #0x10] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG06: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 160 1276: JIT compiled System.Linq.Enumerable:ToArray[BenchmarkDotNet.Reports.Measurement](System.Collections.Generic.IEnumerable`1[BenchmarkDotNet.Reports.Measurement]) [Tier0, IL size=34, code size=160] ; Assembly listing for method System.Linq.Enumerable+WhereListIterator`1[BenchmarkDotNet.Reports.Measurement]:ToArray():BenchmarkDotNet.Reports.Measurement[]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xD0]! mov fp, sp add x9, fp, #56 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] stp xzr, xzr, [x9, #0x80] str x0, [fp, #0xC8] G_M000_IG02: ldr x0, [fp, #0xC8] ldr x0, [x0, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 str w0, [fp, #0x64] ldr w1, [fp, #0x64] add x0, fp, #152 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str wzr, [fp, #0x94] mov w0, #0xD1FFAB1E str w0, [fp, #0x68] b G_M000_IG05 G_M000_IG03: ldr x0, [fp, #0xC8] ldr x0, [x0, #0x30] add x8, fp, #112 ldr w1, [fp, #0x94] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 ldr x0, [fp, #0xC8] ldr x0, [x0, #0x38] str x0, [fp, #0x38] ldp q16, q17, [fp, #0x70] stp q16, q17, [fp, #0x40] ldr x0, [fp, #0x38] ldr x0, [x0, #0x08] add x1, fp, #64 ldr x2, [fp, #0x38] ldr x2, [x2, #0x18] blr x2 cbz w0, G_M000_IG04 ldp x0, x1, [fp, #0x70] stp x0, x1, [fp, #0x18] ldp x0, x1, [fp, #0x80] stp x0, x1, [fp, #0x28] add x1, fp, #24 add x0, fp, #152 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG04: ldr w0, [fp, #0x94] add w0, w0, #1 str w0, [fp, #0x94] G_M000_IG05: ldr w0, [fp, #0x68] sub w0, w0, #1 str w0, [fp, #0x68] ldr w0, [fp, #0x68] cmp w0, #0 bgt G_M000_IG07 G_M000_IG06: add x0, fp, #104 mov w1, #61 bl CORINFO_HELP_PATCHPOINT G_M000_IG07: ldr x0, [fp, #0xC8] ldr x0, [x0, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 ldr w8, [fp, #0x94] cmp w0, w8 bgt G_M000_IG03 add x0, fp, #152 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG08: ldp fp, lr, [sp], #0xD0 ret lr ; Total bytes of code 376 1277: JIT compiled System.Linq.Enumerable+WhereListIterator`1[BenchmarkDotNet.Reports.Measurement]:ToArray() [Tier0, IL size=83, code size=376] ; Assembly listing for method System.Collections.Generic.LargeArrayBuilder`1[BenchmarkDotNet.Reports.Measurement]:.ctor(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: ldr x0, [fp, #0x28] stp xzr, xzr, [x0] stp xzr, xzr, [x0, #0x10] stp xzr, xzr, [x0, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x10] ldr x14, [fp, #0x10] str x14, [fp, #0x18] ldr x14, [fp, #0x28] add x14, x14, #8 ldr x15, [fp, #0x10] bl CORINFO_HELP_CHECKED_ASSIGN_REF ldr x14, [fp, #0x28] ldr x15, [fp, #0x18] bl CORINFO_HELP_CHECKED_ASSIGN_REF ldr x0, [fp, #0x28] ldr w1, [fp, #0x24] str w1, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 120 1278: JIT compiled System.Collections.Generic.LargeArrayBuilder`1[BenchmarkDotNet.Reports.Measurement]:.ctor(int) [Tier0, IL size=35, code size=120] ; Assembly listing for method System.Array:Empty[BenchmarkDotNet.Reports.Measurement]():BenchmarkDotNet.Reports.Measurement[] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #58 bl CORINFO_HELP_CLASSINIT_SHARED_DYNAMICCLASS movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 52 1279: JIT compiled System.Array:Empty[BenchmarkDotNet.Reports.Measurement]() [Tier0, IL size=6, code size=52] ; Assembly listing for method System.Array+EmptyArray`1[BenchmarkDotNet.Reports.Measurement]:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, xzr bl CORINFO_HELP_NEWARR_1_VC movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 56 1280: JIT compiled System.Array+EmptyArray`1[BenchmarkDotNet.Reports.Measurement]:.cctor() [Tier0, IL size=12, code size=56] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults+<>c:b__5_0(BenchmarkDotNet.Reports.Measurement):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x1, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x30] ldp q16, q17, [x0] stp q16, q17, [fp, #0x10] add x0, fp, #16 mov w1, wzr mov w2, #3 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 68 1281: JIT compiled BenchmarkDotNet.Engines.RunResults+<>c:b__5_0(BenchmarkDotNet.Reports.Measurement) [Tier0, IL size=9, code size=68] ; Assembly listing for method BenchmarkDotNet.Reports.MeasurementExtensions:Is(BenchmarkDotNet.Reports.Measurement,int,int):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] str w2, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w1, [fp, #0x14] cmp w0, w1 bne G_M000_IG04 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w1, [fp, #0x10] cmp w0, w1 cset x0, eq G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: mov w0, wzr G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 112 1282: JIT compiled BenchmarkDotNet.Reports.MeasurementExtensions:Is(BenchmarkDotNet.Reports.Measurement,int,int) [Tier0, IL size=23, code size=112] ; Assembly listing for method System.Collections.Generic.LargeArrayBuilder`1[BenchmarkDotNet.Reports.Measurement]:Add(BenchmarkDotNet.Reports.Measurement):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str xzr, [fp, #0x40] str xzr, [fp, #0x18] str x0, [fp, #0x58] str x1, [fp, #0x50] G_M000_IG02: ldr x0, [fp, #0x58] ldr w0, [x0, #0x14] str w0, [fp, #0x4C] ldr x0, [fp, #0x58] ldr x0, [x0, #0x08] str x0, [fp, #0x40] ldr w0, [fp, #0x4C] ldr x1, [fp, #0x40] ldr w1, [x1, #0x08] cmp w0, w1 blo G_M000_IG03 ldr x0, [fp, #0x58] str x0, [fp, #0x18] ldr x0, [fp, #0x50] ldp q16, q17, [x0] stp q16, q17, [fp, #0x20] ldr x0, [fp, #0x18] add x1, fp, #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 b G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x40] ldr w1, [fp, #0x4C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG06 add x0, x0, x1, LSL #5 add x0, x0, #16 ldr x1, [fp, #0x50] ldp q16, q17, [x1] stp q16, q17, [x0] ldr w0, [fp, #0x4C] add w0, w0, #1 ldr x1, [fp, #0x58] str w0, [x1, #0x14] G_M000_IG04: ldr x0, [fp, #0x58] ldr w0, [x0, #0x18] add w0, w0, #1 ldr x1, [fp, #0x58] str w0, [x1, #0x18] G_M000_IG05: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG06: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 212 1283: JIT compiled System.Collections.Generic.LargeArrayBuilder`1[BenchmarkDotNet.Reports.Measurement]:Add(BenchmarkDotNet.Reports.Measurement) [Tier0, IL size=61, code size=212] ; Assembly listing for method System.Collections.Generic.LargeArrayBuilder`1[BenchmarkDotNet.Reports.Measurement]:AddWithBufferAllocation(BenchmarkDotNet.Reports.Measurement):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] str x0, [fp, #0x10] ldr x0, [fp, #0x28] ldr w0, [x0, #0x14] str w0, [fp, #0x1C] ldr w0, [fp, #0x1C] add w0, w0, #1 ldr x1, [fp, #0x28] str w0, [x1, #0x14] ldr x0, [fp, #0x10] ldr w1, [fp, #0x1C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG04 add x0, x0, x1, LSL #5 add x0, x0, #16 ldr x1, [fp, #0x20] ldp q16, q17, [x1] stp q16, q17, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 140 1284: JIT compiled System.Collections.Generic.LargeArrayBuilder`1[BenchmarkDotNet.Reports.Measurement]:AddWithBufferAllocation(BenchmarkDotNet.Reports.Measurement) [Tier0, IL size=36, code size=140] ; Assembly listing for method System.Collections.Generic.LargeArrayBuilder`1[BenchmarkDotNet.Reports.Measurement]:AllocateBuffer():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] G_M000_IG02: ldr x1, [fp, #0x28] ldr w1, [x1, #0x18] cmp w1, #8 bhs G_M000_IG06 ldr x1, [fp, #0x28] ldr w1, [x1, #0x18] cbz w1, G_M000_IG03 ldr x1, [fp, #0x28] ldr w1, [x1, #0x18] lsl w1, w1, #1 str w1, [fp, #0x1C] b G_M000_IG04 G_M000_IG03: mov w1, #4 str w1, [fp, #0x1C] G_M000_IG04: ldr x1, [fp, #0x28] ldr w1, [x1, #0x10] ldr w0, [fp, #0x1C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x24] ldr w1, [fp, #0x24] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC ldr x14, [fp, #0x28] add x14, x14, #8 mov x15, x0 bl CORINFO_HELP_CHECKED_ASSIGN_REF ldr x0, [fp, #0x28] ldr x0, [x0] ldr x1, [fp, #0x28] ldr x1, [x1, #0x08] ldr x2, [fp, #0x28] ldr w2, [x2, #0x18] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x14, [fp, #0x28] ldr x15, [x14, #0x08] ldr x14, [fp, #0x28] bl CORINFO_HELP_CHECKED_ASSIGN_REF G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG06: ldr x0, [fp, #0x28] ldr w0, [x0, #0x18] cmp w0, #8 bne G_M000_IG07 mov w0, #8 str w0, [fp, #0x20] b G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x28] ldrsb wzr, [x0] ldr x0, [fp, #0x28] add x0, x0, #32 ldr x2, [fp, #0x28] ldr x2, [x2, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x1, [fp, #0x28] ldr w1, [x1, #0x10] ldr x0, [fp, #0x28] ldr w0, [x0, #0x18] sub w1, w1, w0 ldr x0, [fp, #0x28] ldr w0, [x0, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x20] G_M000_IG08: ldr w1, [fp, #0x20] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC ldr x14, [fp, #0x28] add x14, x14, #8 mov x15, x0 bl CORINFO_HELP_CHECKED_ASSIGN_REF ldr x0, [fp, #0x28] str wzr, [x0, #0x14] G_M000_IG09: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 404 1285: JIT compiled System.Collections.Generic.LargeArrayBuilder`1[BenchmarkDotNet.Reports.Measurement]:AllocateBuffer() [Tier0, IL size=163, code size=404] ; Assembly listing for method System.Collections.Generic.LargeArrayBuilder`1[BenchmarkDotNet.Reports.Measurement]:ToArray():BenchmarkDotNet.Reports.Measurement[]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: add x1, fp, #16 ldr x0, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG04 ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: ldr x1, [fp, #0x18] ldr w1, [x1, #0x18] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x10] ldr x3, [fp, #0x18] ldr w3, [x3, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] mov w2, wzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x10] G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 144 1286: JIT compiled System.Collections.Generic.LargeArrayBuilder`1[BenchmarkDotNet.Reports.Measurement]:ToArray() [Tier0, IL size=40, code size=144] ; Assembly listing for method System.Collections.Generic.LargeArrayBuilder`1[BenchmarkDotNet.Reports.Measurement]:TryMove(byref):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] ldr x15, [x14] ldr x14, [fp, #0x10] bl CORINFO_HELP_CHECKED_ASSIGN_REF ldr x0, [fp, #0x18] ldr w0, [x0, #0x18] ldr x1, [fp, #0x18] ldr x1, [x1] ldr w1, [x1, #0x08] cmp w0, w1 cset x0, eq G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 68 1287: JIT compiled System.Collections.Generic.LargeArrayBuilder`1[BenchmarkDotNet.Reports.Measurement]:TryMove(byref) [Tier0, IL size=25, code size=68] ; Assembly listing for method System.Collections.Generic.LargeArrayBuilder`1[BenchmarkDotNet.Reports.Measurement]:CopyTo(BenchmarkDotNet.Reports.Measurement[],int,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x28] str x0, [fp, #0x48] str x1, [fp, #0x40] str w2, [fp, #0x3C] str w3, [fp, #0x38] G_M000_IG02: str wzr, [fp, #0x34] mov w0, #0xD1FFAB1E str w0, [fp, #0x18] b G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x48] ldr w1, [fp, #0x34] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x28] ldr x1, [fp, #0x28] ldr w1, [x1, #0x08] ldr w0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x24] ldr x0, [fp, #0x28] ldr w4, [fp, #0x24] ldr x2, [fp, #0x40] ldr w3, [fp, #0x3C] mov w1, wzr movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 ldr w0, [fp, #0x38] ldr w1, [fp, #0x24] sub w0, w0, w1 str w0, [fp, #0x38] ldr w0, [fp, #0x3C] ldr w1, [fp, #0x24] add w0, w0, w1 str w0, [fp, #0x3C] ldr w0, [fp, #0x34] add w0, w0, #1 str w0, [fp, #0x34] G_M000_IG04: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG06 G_M000_IG05: add x0, fp, #24 mov w1, #46 bl CORINFO_HELP_PATCHPOINT G_M000_IG06: ldr w0, [fp, #0x38] cmp w0, #0 bgt G_M000_IG03 G_M000_IG07: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 252 1288: JIT compiled System.Collections.Generic.LargeArrayBuilder`1[BenchmarkDotNet.Reports.Measurement]:CopyTo(BenchmarkDotNet.Reports.Measurement[],int,int) [Tier0, IL size=51, code size=252] ; Assembly listing for method System.Collections.Generic.LargeArrayBuilder`1[BenchmarkDotNet.Reports.Measurement]:GetBuffer(int):BenchmarkDotNet.Reports.Measurement[]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr w0, [fp, #0x14] cbz w0, G_M000_IG06 ldr x0, [fp, #0x18] ldrsb wzr, [x0] ldr x0, [fp, #0x18] add x0, x0, #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w2, [fp, #0x14] cmp w0, w2 bge G_M000_IG04 ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: ldr x0, [fp, #0x18] ldrsb wzr, [x0] ldr x0, [fp, #0x18] add x0, x0, #32 ldr w2, [fp, #0x14] sub w2, w2, #1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG06: ldr x0, [fp, #0x18] ldr x0, [x0] G_M000_IG07: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 180 1289: JIT compiled System.Collections.Generic.LargeArrayBuilder`1[BenchmarkDotNet.Reports.Measurement]:GetBuffer(int) [Tier0, IL size=46, code size=180] ; Assembly listing for method System.Collections.Generic.ArrayBuilder`1[System.__Canon]:get_Count():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 32 1290: JIT compiled System.Collections.Generic.ArrayBuilder`1[System.__Canon]:get_Count() [Tier0, IL size=7, code size=32] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults:get_Workload():System.Collections.Generic.IReadOnlyList`1[BenchmarkDotNet.Reports.Measurement]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] str x0, [fp, #0x38] G_M000_IG02: ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x30] ldr x0, [fp, #0x28] str x0, [fp, #0x20] ldr x0, [fp, #0x30] str x0, [fp, #0x18] ldr x0, [fp, #0x30] cbnz x0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr x0, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x15, [fp, #0x10] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG03: ldr x0, [fp, #0x20] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 256 1291: JIT compiled BenchmarkDotNet.Engines.RunResults:get_Workload() [Tier0, IL size=48, code size=256] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults+<>c:b__7_0(BenchmarkDotNet.Reports.Measurement):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x1, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x30] ldp q16, q17, [x0] stp q16, q17, [fp, #0x10] add x0, fp, #16 mov w1, #1 mov w2, #3 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 68 1292: JIT compiled BenchmarkDotNet.Engines.RunResults+<>c:b__7_0(BenchmarkDotNet.Reports.Measurement) [Tier0, IL size=9, code size=68] ; Assembly listing for method BenchmarkDotNet.Extensions.CommonExtensions:IsEmpty[BenchmarkDotNet.Reports.Measurement](System.Collections.Generic.IReadOnlyCollection`1[BenchmarkDotNet.Reports.Measurement]):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cmp w0, #0 cset x0, eq G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 52 1293: JIT compiled BenchmarkDotNet.Extensions.CommonExtensions:IsEmpty[BenchmarkDotNet.Reports.Measurement](System.Collections.Generic.IReadOnlyCollection`1[BenchmarkDotNet.Reports.Measurement]) [Tier0, IL size=10, code size=52] ; Assembly listing for method System.SZArrayHelper:get_Count[BenchmarkDotNet.Reports.Measurement]():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr w0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 1294: JIT compiled System.SZArrayHelper:get_Count[BenchmarkDotNet.Reports.Measurement]() [Tier0, IL size=11, code size=40] ; Assembly listing for method System.Linq.Enumerable:Select[BenchmarkDotNet.Reports.Measurement,double](System.Collections.Generic.IEnumerable`1[BenchmarkDotNet.Reports.Measurement],System.Func`2[BenchmarkDotNet.Reports.Measurement,double]):System.Collections.Generic.IEnumerable`1[double] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x90]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] str xzr, [x9, #0x60] str x0, [fp, #0x88] str x1, [fp, #0x80] G_M000_IG02: ldr x0, [fp, #0x88] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x80] cbnz x0, G_M000_IG04 mov w0, #15 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldr x1, [fp, #0x88] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x78] ldr x0, [fp, #0x78] cbz x0, G_M000_IG05 ldr x0, [fp, #0x78] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x20] ldr x0, [fp, #0x78] ldr x1, [fp, #0x80] ldr x2, [fp, #0x20] blr x2 str x0, [fp, #0x18] b G_M000_IG11 G_M000_IG05: ldr x1, [fp, #0x88] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x70] ldr x1, [fp, #0x70] cbz x1, G_M000_IG09 ldr x1, [fp, #0x88] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x60] ldr x0, [fp, #0x60] cbz x0, G_M000_IG07 ldr x0, [fp, #0x60] ldr w0, [x0, #0x08] cbz w0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x1, [fp, #0x60] ldr x2, [fp, #0x80] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x28] str x0, [fp, #0x50] ldr x0, [fp, #0x50] str x0, [fp, #0x18] b G_M000_IG11 G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x18] b G_M000_IG11 G_M000_IG07: ldr x1, [fp, #0x88] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x58] ldr x0, [fp, #0x58] cbz x0, G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] ldr x0, [fp, #0x30] ldr x1, [fp, #0x58] ldr x2, [fp, #0x80] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x30] str x0, [fp, #0x18] b G_M000_IG11 G_M000_IG08: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] ldr x0, [fp, #0x38] ldr x1, [fp, #0x70] ldr x2, [fp, #0x80] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x1, [fp, #0x38] str x1, [fp, #0x18] b G_M000_IG11 G_M000_IG09: ldr x1, [fp, #0x88] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x68] ldr x2, [fp, #0x68] cbz x2, G_M000_IG10 str xzr, [fp, #0x48] add x2, fp, #72 ldr x0, [fp, #0x80] ldr x1, [fp, #0x68] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x48] cbz x0, G_M000_IG10 ldr x0, [fp, #0x48] str x0, [fp, #0x18] b G_M000_IG11 G_M000_IG10: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x40] ldr x0, [fp, #0x40] ldr x1, [fp, #0x88] ldr x2, [fp, #0x80] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x40] str x0, [fp, #0x18] b G_M000_IG11 G_M000_IG11: ldr x0, [fp, #0x18] G_M000_IG12: ldp fp, lr, [sp], #0x90 ret lr ; Total bytes of code 776 1295: JIT compiled System.Linq.Enumerable:Select[BenchmarkDotNet.Reports.Measurement,double](System.Collections.Generic.IEnumerable`1[BenchmarkDotNet.Reports.Measurement],System.Func`2[BenchmarkDotNet.Reports.Measurement,double]) [Tier0, IL size=146, code size=776] ; Assembly listing for method System.Linq.Enumerable+SelectArrayIterator`2[BenchmarkDotNet.Reports.Measurement,double]:.ctor(BenchmarkDotNet.Reports.Measurement[],System.Func`2[BenchmarkDotNet.Reports.Measurement,double]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] add x14, x14, #24 ldr x15, [fp, #0x20] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x28] add x14, x14, #32 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 1296: JIT compiled System.Linq.Enumerable+SelectArrayIterator`2[BenchmarkDotNet.Reports.Measurement,double]:.ctor(BenchmarkDotNet.Reports.Measurement[],System.Func`2[BenchmarkDotNet.Reports.Measurement,double]) [Tier0, IL size=21, code size=84] ; Assembly listing for method System.Linq.Enumerable+Iterator`1[double]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 bl System.Environment:get_CurrentManagedThreadId():int ldr x1, [fp, #0x18] str w0, [x1, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 1297: JIT compiled System.Linq.Enumerable+Iterator`1[double]:.ctor() [Tier0, IL size=18, code size=56] ; Assembly listing for method BenchmarkDotNet.Mathematics.Statistics:.ctor(System.Collections.Generic.IEnumerable`1[double]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #0xD1FFAB1E]! mov fp, sp movi v16.16b, #0 add x9, fp, #88 add x10, fp, #0xD1FFAB1E stp q16, q16, [x9, #-0x40] stp q16, q16, [x9, #-0x20] bfm x9, xzr, #0, #5 dczva x9 add x9, x9, #64 cmp x9, x10 blo pc-16 (-4 instructions) stp q16, q16, [x10] stp q16, q16, [x10, #0x20] str x0, [fp, #0xD1FFAB1E] str x1, [fp, #0xD1FFAB1E] G_M000_IG02: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x90] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x88] ldr x1, [fp, #0x88] ldr x0, [fp, #0x90] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x90] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x90] str x0, [fp, #0xD1FFAB1E] G_M000_IG03: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0xD1FFAB1E] add x14, x14, #8 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD1FFAB1E] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] cbnz x0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x98] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x80] ldr x1, [fp, #0x80] ldr x0, [fp, #0x98] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #0xD1FFAB1E bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ldr x15, [fp, #0x98] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x98] str x0, [fp, #0xD1FFAB1E] G_M000_IG04: ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0xD1FFAB1E] add x14, x14, #16 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x78] ldr x0, [fp, #0x78] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 ldr x1, [fp, #0xD1FFAB1E] str w0, [x1, #0xB0] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbnz w0, G_M000_IG06 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xA0] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x70] ldr x1, [fp, #0x70] ldr x0, [fp, #0xA0] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0xA0] bl CORINFO_HELP_THROW G_M000_IG06: ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x68] ldr x0, [fp, #0x68] add x8, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] str d0, [x0, #0x40] add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] str d0, [x0, #0x50] add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] str d0, [x0, #0x58] add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] str d0, [x0, #0x68] add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] str d0, [x0, #0x78] add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] str d0, [x0, #0x80] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x60] ldr x0, [fp, #0x60] add x8, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] str d0, [x0, #0x60] add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] str d0, [x0, #0x98] add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] str d0, [x0, #0x90] add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] str d0, [x0, #0xA0] add x0, fp, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0xD1FFAB1E] str d0, [x0, #0xA8] ldr x0, [fp, #0xD1FFAB1E] str x0, [fp, #0x38] ldp q0, q16, [fp, #0xD1FFAB1E] stp q0, q16, [fp, #0x40] add x0, fp, #56 fmov d0, #1.5000 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 ldr x0, [fp, #0xD1FFAB1E] str d0, [x0, #0x48] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 ldr x0, [fp, #0xD1FFAB1E] str d0, [x0, #0x70] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0xD1FFAB1E] add x14, x14, #40 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST G_M000_IG07: str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x30] ldr x2, [fp, #0x30] ldr x1, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0xD1FFAB1E] add x14, x14, #24 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x28] ldr x2, [fp, #0x28] ldr x1, [fp, #0xD1FFAB1E] ldr x0, [fp, #0xD1FFAB1E] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xD1FFAB1E] ldr x1, [fp, #0xD1FFAB1E] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0xD1FFAB1E] add x14, x14, #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0xD1FFAB1E] add x14, x14, #56 ldr x15, [fp, #0xD1FFAB1E] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0xF8] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 scvtf d0, w0 bl System.Math:Sqrt(double):double ldr d16, [fp, #0xF8] fdiv d16, d16, d0 ldr x0, [fp, #0xD1FFAB1E] str d16, [x0, #0x88] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0xF0] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0xE8] stp xzr, xzr, [fp, #0xB0] stp xzr, xzr, [fp, #0xC0] stp xzr, xzr, [fp, #0xD0] str xzr, [fp, #0xE0] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x24] ldr w1, [fp, #0x24] add x0, fp, #176 ldr d0, [fp, #0xF0] ldr d1, [fp, #0xE8] mov w2, #12 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0xD1FFAB1E] G_M000_IG08: sub x1, fp, #8 ldr x2, [x1, #0xB8] str x2, [x0, #0xB8] ldp q16, q17, [x1, #0xC0] stp q16, q17, [x0, #0xC0] ldr q16, [x1, #0xE0] str q16, [x0, #0xE0] G_M000_IG09: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0xA8] ldr x0, [fp, #0xD1FFAB1E] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0xA8] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0xD1FFAB1E] add x14, x14, #48 ldr x15, [fp, #0xA8] bl CORINFO_HELP_ASSIGN_REF G_M000_IG10: ldp fp, lr, [sp], #0xD1FFAB1E ret lr ; Total bytes of code 2312 1298: JIT compiled BenchmarkDotNet.Mathematics.Statistics:.ctor(System.Collections.Generic.IEnumerable`1[double]) [Tier0, IL size=535, code size=2312] ; Assembly listing for method BenchmarkDotNet.Mathematics.Statistics+<>c:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 1299: JIT compiled BenchmarkDotNet.Mathematics.Statistics+<>c:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method BenchmarkDotNet.Mathematics.Statistics+<>c:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 1300: JIT compiled BenchmarkDotNet.Mathematics.Statistics+<>c:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Linq.Enumerable:Where[double](System.Collections.Generic.IEnumerable`1[double],System.Func`2[double,bool]):System.Collections.Generic.IEnumerable`1[double] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] str x0, [fp, #0x58] str x1, [fp, #0x50] G_M000_IG02: ldr x0, [fp, #0x58] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x50] cbnz x0, G_M000_IG04 mov w0, #12 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldr x1, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x48] ldr x0, [fp, #0x48] cbz x0, G_M000_IG05 ldr x0, [fp, #0x48] ldr x1, [fp, #0x50] ldr x2, [fp, #0x48] ldr x2, [x2] ldr x2, [x2, #0x48] ldr x2, [x2, #0x10] blr x2 str x0, [fp, #0x10] b G_M000_IG09 G_M000_IG05: ldr x1, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x40] ldr x0, [fp, #0x40] cbz x0, G_M000_IG07 ldr x0, [fp, #0x40] ldr w0, [x0, #0x08] cbz w0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x40] ldr x2, [fp, #0x50] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] str x0, [fp, #0x30] ldr x0, [fp, #0x30] str x0, [fp, #0x10] b G_M000_IG09 G_M000_IG06: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x10] b G_M000_IG09 G_M000_IG07: ldr x1, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x38] ldr x0, [fp, #0x38] cbz x0, G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x38] ldr x2, [fp, #0x50] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x20] str x0, [fp, #0x10] b G_M000_IG09 G_M000_IG08: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x1, [fp, #0x58] ldr x2, [fp, #0x50] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x28] str x0, [fp, #0x10] b G_M000_IG09 G_M000_IG09: ldr x0, [fp, #0x10] G_M000_IG10: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 528 1301: JIT compiled System.Linq.Enumerable:Where[double](System.Collections.Generic.IEnumerable`1[double],System.Func`2[double,bool]) [Tier0, IL size=94, code size=528] ; Assembly listing for method System.Linq.Enumerable+Iterator`1[double]:Where(System.Func`2[double,bool]):System.Collections.Generic.IEnumerable`1[double]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 1302: JIT compiled System.Linq.Enumerable+Iterator`1[double]:Where(System.Func`2[double,bool]) [Tier0, IL size=8, code size=84] ; Assembly listing for method System.Linq.Enumerable+WhereEnumerableIterator`1[double]:.ctor(System.Collections.Generic.IEnumerable`1[double],System.Func`2[double,bool]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] add x14, x14, #24 ldr x15, [fp, #0x20] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x28] add x14, x14, #32 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 1303: JIT compiled System.Linq.Enumerable+WhereEnumerableIterator`1[double]:.ctor(System.Collections.Generic.IEnumerable`1[double],System.Func`2[double,bool]) [Tier0, IL size=21, code size=84] ; Assembly listing for method System.Linq.Enumerable:ToArray[double](System.Collections.Generic.IEnumerable`1[double]):double[] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x1, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x10] ldr x0, [fp, #0x10] cbnz x0, G_M000_IG05 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG05: ldr x0, [fp, #0x10] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG06: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 160 1304: JIT compiled System.Linq.Enumerable:ToArray[double](System.Collections.Generic.IEnumerable`1[double]) [Tier0, IL size=34, code size=160] ; Assembly listing for method System.Linq.Enumerable+WhereEnumerableIterator`1[double]:ToArray():double[]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] add x1, sp, #112 str x1, [fp, #0x68] str x0, [fp, #0x60] G_M000_IG02: add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x60] ldr x0, [x0, #0x18] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x28] mov w0, #0xD1FFAB1E str w0, [fp, #0x18] G_M000_IG03: b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x28] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str d0, [fp, #0x20] ldr x0, [fp, #0x60] ldr x0, [x0, #0x20] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x08] ldr d0, [fp, #0x20] ldr x1, [fp, #0x10] ldr x1, [x1, #0x18] blr x1 cbz w0, G_M000_IG05 add x0, fp, #48 ldr d0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG05: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG07 G_M000_IG06: add x0, fp, #24 mov w1, #50 bl CORINFO_HELP_PATCHPOINT G_M000_IG07: ldr x0, [fp, #0x28] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG04 b G_M000_IG08 G_M000_IG08: ldr x0, [fp, #0x68] bl G_M000_IG12 G_M000_IG09: nop G_M000_IG10: add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG11: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG12: stp fp, lr, [sp, #-0x20]! add x3, fp, #112 str x3, [sp, #0x18] G_M000_IG13: ldr x0, [fp, #0x28] cbz x0, G_M000_IG14 ldr x0, [fp, #0x28] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG14: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 368 1305: JIT compiled System.Linq.Enumerable+WhereEnumerableIterator`1[double]:ToArray() [Tier0, IL size=78, code size=368] ; Assembly listing for method System.Collections.Generic.LargeArrayBuilder`1[double]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movn w1, #0xD1FFAB1E LSL #16 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 48 1306: JIT compiled System.Collections.Generic.LargeArrayBuilder`1[double]:.ctor() [Tier0, IL size=12, code size=48] ; Assembly listing for method System.Collections.Generic.LargeArrayBuilder`1[double]:.ctor(int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: ldr x0, [fp, #0x28] stp xzr, xzr, [x0] stp xzr, xzr, [x0, #0x10] stp xzr, xzr, [x0, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x10] ldr x14, [fp, #0x10] str x14, [fp, #0x18] ldr x14, [fp, #0x28] add x14, x14, #8 ldr x15, [fp, #0x10] bl CORINFO_HELP_CHECKED_ASSIGN_REF ldr x14, [fp, #0x28] ldr x15, [fp, #0x18] bl CORINFO_HELP_CHECKED_ASSIGN_REF ldr x0, [fp, #0x28] ldr w1, [fp, #0x24] str w1, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 120 1307: JIT compiled System.Collections.Generic.LargeArrayBuilder`1[double]:.ctor(int) [Tier0, IL size=35, code size=120] ; Assembly listing for method System.Array:Empty[double]():double[] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #59 bl CORINFO_HELP_CLASSINIT_SHARED_DYNAMICCLASS movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 52 1308: JIT compiled System.Array:Empty[double]() [Tier0, IL size=6, code size=52] ; Assembly listing for method System.Linq.Enumerable+Iterator`1[double]:GetEnumerator():System.Collections.Generic.IEnumerator`1[double]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] ldr w0, [x0, #0x14] cbnz w0, G_M000_IG03 ldr x0, [fp, #0x28] ldr w0, [x0, #0x10] str w0, [fp, #0x14] bl System.Environment:get_CurrentManagedThreadId():int ldr w1, [fp, #0x14] cmp w0, w1 beq G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x28] ldr x1, [fp, #0x28] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x28] blr x1 str x0, [fp, #0x18] b G_M000_IG05 G_M000_IG04: ldr x0, [fp, #0x28] str x0, [fp, #0x18] G_M000_IG05: ldr x0, [fp, #0x18] str x0, [fp, #0x20] ldr x0, [fp, #0x20] mov w1, #1 str w1, [x0, #0x14] ldr x0, [fp, #0x20] G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 132 1309: JIT compiled System.Linq.Enumerable+Iterator`1[double]:GetEnumerator() [Tier0, IL size=40, code size=132] ; Assembly listing for method System.Linq.Enumerable+SelectArrayIterator`2[BenchmarkDotNet.Reports.Measurement,double]:MoveNext():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! str x19, [sp, #0x48] mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x40] G_M000_IG02: ldr x0, [fp, #0x40] ldr w0, [x0, #0x14] cmp w0, #0 cset x0, le ldr x1, [fp, #0x40] ldr w1, [x1, #0x14] ldr x2, [fp, #0x40] ldr x2, [x2, #0x18] ldr w2, [x2, #0x08] add w2, w2, #1 cmp w1, w2 cset x1, eq orr w0, w0, w1 cbz w0, G_M000_IG04 ldr x0, [fp, #0x40] ldr x1, [fp, #0x40] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x30] blr x1 mov w0, wzr G_M000_IG03: ldr x19, [sp, #0x48] ldp fp, lr, [sp], #0x50 ret lr G_M000_IG04: ldr x0, [fp, #0x40] ldr w0, [x0, #0x14] str w0, [fp, #0x38] ldr w0, [fp, #0x38] add w0, w0, #1 ldr x1, [fp, #0x40] str w0, [x1, #0x14] ldr w0, [fp, #0x38] sub w0, w0, #1 str w0, [fp, #0x3C] ldr x19, [fp, #0x40] ldr x0, [fp, #0x40] ldr x0, [x0, #0x20] str x0, [fp, #0x10] ldr x0, [fp, #0x40] ldr x0, [x0, #0x18] ldr w1, [fp, #0x3C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG06 add x0, x0, x1, LSL #5 add x0, x0, #16 ldp x1, x2, [x0] stp x1, x2, [fp, #0x18] ldp x1, x2, [x0, #0x10] stp x1, x2, [fp, #0x28] ldr x0, [fp, #0x10] ldr x0, [x0, #0x08] add x1, fp, #24 ldr x2, [fp, #0x10] ldr x2, [x2, #0x18] blr x2 str d0, [x19, #0x08] mov w0, #1 G_M000_IG05: ldr x19, [sp, #0x48] ldp fp, lr, [sp], #0x50 ret lr G_M000_IG06: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 272 1310: JIT compiled System.Linq.Enumerable+SelectArrayIterator`2[BenchmarkDotNet.Reports.Measurement,double]:MoveNext() [Tier0, IL size=89, code size=272] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults+<>c:b__18_0(BenchmarkDotNet.Reports.Measurement):double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 48 1311: JIT compiled BenchmarkDotNet.Engines.RunResults+<>c:b__18_0(BenchmarkDotNet.Reports.Measurement) [Tier0, IL size=8, code size=48] ; Assembly listing for method System.Linq.Enumerable+Iterator`1[double]:get_Current():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1312: JIT compiled System.Linq.Enumerable+Iterator`1[double]:get_Current() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Mathematics.Statistics+<>c:<.ctor>b__69_0(double):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str d0, [fp, #0x10] G_M000_IG02: ldr d0, [fp, #0x10] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 cmp w0, #0 cset x0, eq G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 56 1313: JIT compiled BenchmarkDotNet.Mathematics.Statistics+<>c:<.ctor>b__69_0(double) [Tier0, IL size=10, code size=56] ; Assembly listing for method System.Collections.Generic.LargeArrayBuilder`1[double]:Add(double):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str d0, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] ldr w0, [x0, #0x14] str w0, [fp, #0x1C] ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] str x0, [fp, #0x10] ldr w0, [fp, #0x1C] ldr x1, [fp, #0x10] ldr w1, [x1, #0x08] cmp w0, w1 blo G_M000_IG03 ldr x0, [fp, #0x28] ldr d0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 b G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x10] ldr w1, [fp, #0x1C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG06 add x0, x0, x1, LSL #3 add x0, x0, #16 ldr d16, [fp, #0x20] str d16, [x0] ldr w0, [fp, #0x1C] add w0, w0, #1 ldr x1, [fp, #0x28] str w0, [x1, #0x14] G_M000_IG04: ldr x0, [fp, #0x28] ldr w0, [x0, #0x18] add w0, w0, #1 ldr x1, [fp, #0x28] str w0, [x1, #0x18] G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG06: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 184 1314: JIT compiled System.Collections.Generic.LargeArrayBuilder`1[double]:Add(double) [Tier0, IL size=61, code size=184] ; Assembly listing for method System.Collections.Generic.LargeArrayBuilder`1[double]:AddWithBufferAllocation(double):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str d0, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] str x0, [fp, #0x10] ldr x0, [fp, #0x28] ldr w0, [x0, #0x14] str w0, [fp, #0x1C] ldr w0, [fp, #0x1C] add w0, w0, #1 ldr x1, [fp, #0x28] str w0, [x1, #0x14] ldr x0, [fp, #0x10] ldr w1, [fp, #0x1C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG04 add x0, x0, x1, LSL #3 add x0, x0, #16 ldr d16, [fp, #0x20] str d16, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 136 1315: JIT compiled System.Collections.Generic.LargeArrayBuilder`1[double]:AddWithBufferAllocation(double) [Tier0, IL size=36, code size=136] ; Assembly listing for method System.Collections.Generic.LargeArrayBuilder`1[double]:AllocateBuffer():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] G_M000_IG02: ldr x1, [fp, #0x28] ldr w1, [x1, #0x18] cmp w1, #8 bhs G_M000_IG06 ldr x1, [fp, #0x28] ldr w1, [x1, #0x18] cbz w1, G_M000_IG03 ldr x1, [fp, #0x28] ldr w1, [x1, #0x18] lsl w1, w1, #1 str w1, [fp, #0x1C] b G_M000_IG04 G_M000_IG03: mov w1, #4 str w1, [fp, #0x1C] G_M000_IG04: ldr x1, [fp, #0x28] ldr w1, [x1, #0x10] ldr w0, [fp, #0x1C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x24] ldr w1, [fp, #0x24] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC ldr x14, [fp, #0x28] add x14, x14, #8 mov x15, x0 bl CORINFO_HELP_CHECKED_ASSIGN_REF ldr x0, [fp, #0x28] ldr x0, [x0] ldr x1, [fp, #0x28] ldr x1, [x1, #0x08] ldr x2, [fp, #0x28] ldr w2, [x2, #0x18] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x14, [fp, #0x28] ldr x15, [x14, #0x08] ldr x14, [fp, #0x28] bl CORINFO_HELP_CHECKED_ASSIGN_REF G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG06: ldr x0, [fp, #0x28] ldr w0, [x0, #0x18] cmp w0, #8 bne G_M000_IG07 mov w0, #8 str w0, [fp, #0x20] b G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x28] ldrsb wzr, [x0] ldr x0, [fp, #0x28] add x0, x0, #32 ldr x2, [fp, #0x28] ldr x2, [x2, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x1, [fp, #0x28] ldr w1, [x1, #0x10] ldr x0, [fp, #0x28] ldr w0, [x0, #0x18] sub w1, w1, w0 ldr x0, [fp, #0x28] ldr w0, [x0, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x20] G_M000_IG08: ldr w1, [fp, #0x20] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC ldr x14, [fp, #0x28] add x14, x14, #8 mov x15, x0 bl CORINFO_HELP_CHECKED_ASSIGN_REF ldr x0, [fp, #0x28] str wzr, [x0, #0x14] G_M000_IG09: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 404 1316: JIT compiled System.Collections.Generic.LargeArrayBuilder`1[double]:AllocateBuffer() [Tier0, IL size=163, code size=404] ; Assembly listing for method System.Linq.Enumerable+Iterator`1[double]:Dispose():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] str xzr, [x0, #0x08] ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x14] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 1317: JIT compiled System.Linq.Enumerable+Iterator`1[double]:Dispose() [Tier0, IL size=20, code size=40] ; Assembly listing for method System.Collections.Generic.LargeArrayBuilder`1[double]:ToArray():double[]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: add x1, fp, #16 ldr x0, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG04 ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: ldr x1, [fp, #0x18] ldr w1, [x1, #0x18] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x10] ldr x3, [fp, #0x18] ldr w3, [x3, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] mov w2, wzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x10] G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 144 1318: JIT compiled System.Collections.Generic.LargeArrayBuilder`1[double]:ToArray() [Tier0, IL size=40, code size=144] ; Assembly listing for method System.Collections.Generic.LargeArrayBuilder`1[double]:TryMove(byref):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x14, [fp, #0x18] ldr x15, [x14] ldr x14, [fp, #0x10] bl CORINFO_HELP_CHECKED_ASSIGN_REF ldr x0, [fp, #0x18] ldr w0, [x0, #0x18] ldr x1, [fp, #0x18] ldr x1, [x1] ldr w1, [x1, #0x08] cmp w0, w1 cset x0, eq G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 68 1319: JIT compiled System.Collections.Generic.LargeArrayBuilder`1[double]:TryMove(byref) [Tier0, IL size=25, code size=68] ; Assembly listing for method System.Collections.Generic.LargeArrayBuilder`1[double]:CopyTo(double[],int,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x28] str x0, [fp, #0x48] str x1, [fp, #0x40] str w2, [fp, #0x3C] str w3, [fp, #0x38] G_M000_IG02: str wzr, [fp, #0x34] mov w0, #0xD1FFAB1E str w0, [fp, #0x18] b G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x48] ldr w1, [fp, #0x34] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x28] ldr x1, [fp, #0x28] ldr w1, [x1, #0x08] ldr w0, [fp, #0x38] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str w0, [fp, #0x24] ldr x0, [fp, #0x28] ldr w4, [fp, #0x24] ldr x2, [fp, #0x40] ldr w3, [fp, #0x3C] mov w1, wzr movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 ldr w0, [fp, #0x38] ldr w1, [fp, #0x24] sub w0, w0, w1 str w0, [fp, #0x38] ldr w0, [fp, #0x3C] ldr w1, [fp, #0x24] add w0, w0, w1 str w0, [fp, #0x3C] ldr w0, [fp, #0x34] add w0, w0, #1 str w0, [fp, #0x34] G_M000_IG04: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG06 G_M000_IG05: add x0, fp, #24 mov w1, #46 bl CORINFO_HELP_PATCHPOINT G_M000_IG06: ldr w0, [fp, #0x38] cmp w0, #0 bgt G_M000_IG03 G_M000_IG07: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 252 1320: JIT compiled System.Collections.Generic.LargeArrayBuilder`1[double]:CopyTo(double[],int,int) [Tier0, IL size=51, code size=252] ; Assembly listing for method System.Collections.Generic.LargeArrayBuilder`1[double]:GetBuffer(int):double[]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str w1, [fp, #0x14] G_M000_IG02: ldr w0, [fp, #0x14] cbz w0, G_M000_IG06 ldr x0, [fp, #0x18] ldrsb wzr, [x0] ldr x0, [fp, #0x18] add x0, x0, #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w2, [fp, #0x14] cmp w0, w2 bge G_M000_IG04 ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: ldr x0, [fp, #0x18] ldrsb wzr, [x0] ldr x0, [fp, #0x18] add x0, x0, #32 ldr w2, [fp, #0x14] sub w2, w2, #1 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG06: ldr x0, [fp, #0x18] ldr x0, [x0] G_M000_IG07: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 180 1321: JIT compiled System.Collections.Generic.LargeArrayBuilder`1[double]:GetBuffer(int) [Tier0, IL size=46, code size=180] ; Assembly listing for method BenchmarkDotNet.Mathematics.Statistics:get_OriginalValues():System.Collections.Generic.IReadOnlyList`1[double]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1322: JIT compiled BenchmarkDotNet.Mathematics.Statistics:get_OriginalValues() [Tier0, IL size=7, code size=28] ; Assembly listing for method System.Linq.Enumerable:OrderBy[double,double](System.Collections.Generic.IEnumerable`1[double],System.Func`2[double,double]):System.Linq.IOrderedEnumerable`1[double] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr x2, [fp, #0x20] mov x3, xzr mov w4, wzr mov x5, xzr movz x6, #0xD1FFAB1E movk x6, #0xD1FFAB1E LSL #16 movk x6, #0xD1FFAB1E LSL #32 ldr x6, [x6] blr x6 ldr x0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 1323: JIT compiled System.Linq.Enumerable:OrderBy[double,double](System.Collections.Generic.IEnumerable`1[double],System.Func`2[double,double]) [Tier0, IL size=11, code size=96] ; Assembly listing for method System.Linq.OrderedEnumerable`2[double,double]:.ctor(System.Collections.Generic.IEnumerable`1[double],System.Func`2[double,double],System.Collections.Generic.IComparer`1[double],bool,System.Linq.OrderedEnumerable`1[double]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x48] str x1, [fp, #0x40] str x2, [fp, #0x38] str x3, [fp, #0x30] str w4, [fp, #0x2C] str x5, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x48] ldr x1, [fp, #0x40] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x40] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x38] cbnz x0, G_M000_IG04 mov w0, #9 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldr x14, [fp, #0x48] add x14, x14, #16 ldr x15, [fp, #0x20] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x48] add x14, x14, #24 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x48] str x0, [fp, #0x18] ldr x0, [fp, #0x30] str x0, [fp, #0x10] ldr x0, [fp, #0x30] cbnz x0, G_M000_IG05 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x10] G_M000_IG05: ldr x14, [fp, #0x18] add x14, x14, #32 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x48] ldr w1, [fp, #0x2C] strb w1, [x0, #0x28] G_M000_IG06: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 248 1324: JIT compiled System.Linq.OrderedEnumerable`2[double,double]:.ctor(System.Collections.Generic.IEnumerable`1[double],System.Func`2[double,double],System.Collections.Generic.IComparer`1[double],bool,System.Linq.OrderedEnumerable`1[double]) [Tier0, IL size=67, code size=248] ; Assembly listing for method System.Linq.OrderedEnumerable`1[double]:.ctor(System.Collections.Generic.IEnumerable`1[double]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x18] add x14, x14, #8 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 64 1325: JIT compiled System.Linq.OrderedEnumerable`1[double]:.ctor(System.Collections.Generic.IEnumerable`1[double]) [Tier0, IL size=14, code size=64] ; Assembly listing for method System.Linq.OrderedEnumerable`1[double]:ToArray():double[]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str xzr, [fp, #0x48] str xzr, [fp, #0x38] str xzr, [fp, #0x30] str x0, [fp, #0x58] G_M000_IG02: ldr x1, [fp, #0x58] ldr x1, [x1, #0x08] add x0, fp, #72 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [fp, #0x50] str w0, [fp, #0x44] mov w0, #0xD1FFAB1E str w0, [fp, #0x18] ldr w0, [fp, #0x44] cbnz w0, G_M000_IG04 ldr x0, [fp, #0x48] G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG04: ldr w1, [fp, #0x44] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x38] ldr x1, [fp, #0x48] ldr x2, [fp, #0x50] ldr x0, [fp, #0x58] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x30] str wzr, [fp, #0x2C] b G_M000_IG06 G_M000_IG05: ldr x0, [fp, #0x48] ldr x1, [fp, #0x30] ldr w2, [fp, #0x2C] ldr w3, [x1, #0x08] cmp w2, w3 bhs G_M000_IG10 add x1, x1, x2, LSL #2 add x1, x1, #16 ldr w1, [x1] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG10 add x0, x0, x1, LSL #3 add x0, x0, #16 ldr d16, [x0] str d16, [fp, #0x20] ldr x0, [fp, #0x38] ldr w1, [fp, #0x2C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG10 add x0, x0, x1, LSL #3 add x0, x0, #16 ldr d16, [fp, #0x20] str d16, [x0] ldr w0, [fp, #0x2C] add w0, w0, #1 str w0, [fp, #0x2C] G_M000_IG06: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG08 G_M000_IG07: add x0, fp, #24 mov w1, #79 bl CORINFO_HELP_PATCHPOINT G_M000_IG08: ldr w0, [fp, #0x2C] ldr x1, [fp, #0x38] ldr w1, [x1, #0x08] cmp w0, w1 blt G_M000_IG05 ldr x0, [fp, #0x38] G_M000_IG09: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG10: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 352 1326: JIT compiled System.Linq.OrderedEnumerable`1[double]:ToArray() [Tier0, IL size=88, code size=352] ; Assembly listing for method System.Linq.Buffer`1[double]:.ctor(System.Collections.Generic.IEnumerable`1[double]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] G_M000_IG02: ldr x1, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x18] ldr x0, [fp, #0x18] cbz x0, G_M000_IG04 ldr x0, [fp, #0x18] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x10] ldr x14, [fp, #0x28] ldr x15, [fp, #0x10] bl CORINFO_HELP_CHECKED_ASSIGN_REF ldr x1, [fp, #0x10] ldr w1, [x1, #0x08] ldr x0, [fp, #0x28] str w1, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: ldr x1, [fp, #0x28] ldrsb wzr, [x1] ldr x1, [fp, #0x28] add x1, x1, #8 ldr x0, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x28] mov x15, x0 bl CORINFO_HELP_CHECKED_ASSIGN_REF G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 196 1327: JIT compiled System.Linq.Buffer`1[double]:.ctor(System.Collections.Generic.IEnumerable`1[double]) [Tier0, IL size=53, code size=196] ; Assembly listing for method System.Collections.Generic.EnumerableHelpers:ToArray[double](System.Collections.Generic.IEnumerable`1[double],byref):double[] ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! mov fp, sp add x9, fp, #48 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str xzr, [x9, #0x50] add x2, sp, #160 str x2, [fp, #0x98] str x0, [fp, #0x90] str x1, [fp, #0x88] G_M000_IG02: ldr x1, [fp, #0x90] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str x0, [fp, #0x80] mov w0, #0xD1FFAB1E str w0, [fp, #0x18] ldr x0, [fp, #0x80] cbz x0, G_M000_IG04 ldr x0, [fp, #0x80] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str w0, [fp, #0x7C] ldr w1, [fp, #0x7C] cbz w1, G_M000_IG20 ldr w1, [fp, #0x7C] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x70] ldr x0, [fp, #0x80] ldr x1, [fp, #0x70] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 mov w2, wzr ldr x3, [x11] blr x3 ldr x0, [fp, #0x88] ldr w11, [fp, #0x7C] str w11, [x0] ldr x0, [fp, #0x70] G_M000_IG03: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG04: ldr x0, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x68] G_M000_IG05: ldr x0, [fp, #0x68] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbz w0, G_M000_IG15 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov x1, #4 bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x60] ldr x0, [fp, #0x60] str x0, [fp, #0x48] ldr x0, [fp, #0x68] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str d0, [fp, #0x40] ldr x0, [fp, #0x48] mov w1, wzr ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG06 add x0, x0, x1, LSL #3 add x0, x0, #16 ldr d16, [fp, #0x40] str d16, [x0] mov w0, #1 str w0, [fp, #0x5C] b G_M000_IG12 G_M000_IG06: bl CORINFO_HELP_RNGCHKFAIL G_M000_IG07: ldr w0, [fp, #0x5C] ldr x1, [fp, #0x60] ldr w1, [x1, #0x08] cmp w0, w1 bne G_M000_IG11 ldr w0, [fp, #0x5C] lsl w0, w0, #1 str w0, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 sxtw x0, w0 ldr w1, [fp, #0x58] mov w1, w1 cmp x0, x1 bge G_M000_IG10 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr w1, [fp, #0x5C] cmp w0, w1 ble G_M000_IG08 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str w0, [fp, #0x24] b G_M000_IG09 G_M000_IG08: ldr w0, [fp, #0x5C] add w0, w0, #1 str w0, [fp, #0x24] G_M000_IG09: ldr w0, [fp, #0x24] str w0, [fp, #0x58] G_M000_IG10: add x0, fp, #96 ldr w1, [fp, #0x58] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG11: ldr w0, [fp, #0x5C] str w0, [fp, #0x3C] ldr w0, [fp, #0x5C] add w0, w0, #1 str w0, [fp, #0x5C] ldr x0, [fp, #0x60] str x0, [fp, #0x30] ldr x0, [fp, #0x68] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str d0, [fp, #0x28] ldr x0, [fp, #0x30] ldr w11, [fp, #0x3C] ldr w1, [x0, #0x08] cmp w11, w1 bhs G_M000_IG06 add x0, x0, x11, LSL #3 add x0, x0, #16 ldr d16, [fp, #0x28] str d16, [x0] G_M000_IG12: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG14 G_M000_IG13: add x0, fp, #24 mov w1, #161 bl CORINFO_HELP_PATCHPOINT G_M000_IG14: ldr x0, [fp, #0x68] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG07 ldr x0, [fp, #0x88] ldr w11, [fp, #0x5C] str w11, [x0] ldr x0, [fp, #0x60] str x0, [fp, #0x50] b G_M000_IG16 G_M000_IG15: b G_M000_IG18 G_M000_IG16: ldr x0, [fp, #0x98] bl G_M000_IG24 G_M000_IG17: b G_M000_IG22 G_M000_IG18: ldr x0, [fp, #0x98] bl G_M000_IG24 G_M000_IG19: nop G_M000_IG20: ldr x0, [fp, #0x88] str wzr, [x0] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG21: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG22: ldr x0, [fp, #0x50] G_M000_IG23: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG24: stp fp, lr, [sp, #-0x20]! add x3, fp, #160 str x3, [sp, #0x18] G_M000_IG25: ldr x0, [fp, #0x68] cbz x0, G_M000_IG26 ldr x0, [fp, #0x68] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG26: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 880 1328: JIT compiled System.Collections.Generic.EnumerableHelpers:ToArray[double](System.Collections.Generic.IEnumerable`1[double],byref) [Tier0, IL size=203, code size=880] ; Assembly listing for method System.SZArrayHelper:get_Count[double]():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr w0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 1329: JIT compiled System.SZArrayHelper:get_Count[double]() [Tier0, IL size=11, code size=40] ; Assembly listing for method System.SZArrayHelper:CopyTo[double](double[],int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] G_M000_IG02: ldr x4, [fp, #0x28] str x4, [fp, #0x10] ldr x4, [fp, #0x10] ldr w4, [x4, #0x08] ldr x0, [fp, #0x10] ldr x2, [fp, #0x20] ldr w3, [fp, #0x1C] mov w1, wzr movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 1330: JIT compiled System.SZArrayHelper:CopyTo[double](double[],int) [Tier0, IL size=20, code size=84] ; Assembly listing for method System.Linq.OrderedEnumerable`1[double]:SortedMap(System.Linq.Buffer`1[double]):int[]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x18] str x2, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] ldr w2, [fp, #0x20] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] ldr wzr, [x0] blr x3 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 96 1331: JIT compiled System.Linq.OrderedEnumerable`1[double]:SortedMap(System.Linq.Buffer`1[double]) [Tier0, IL size=24, code size=96] ; Assembly listing for method System.Linq.OrderedEnumerable`1[double]:GetEnumerableSorter():System.Linq.EnumerableSorter`1[double]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] mov x1, xzr ldr x2, [fp, #0x18] ldr x2, [x2] ldr x2, [x2, #0x48] ldr x2, [x2, #0x28] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 48 1332: JIT compiled System.Linq.OrderedEnumerable`1[double]:GetEnumerableSorter() [Tier0, IL size=8, code size=48] ; Assembly listing for method System.Linq.OrderedEnumerable`2[double,double]:GetEnumerableSorter(System.Linq.EnumerableSorter`1[double]):System.Linq.EnumerableSorter`1[double]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str x1, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x38] ldr x0, [x0, #0x20] str x0, [fp, #0x28] b G_M000_IG03 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x3, [fp, #0x38] ldrb w3, [x3, #0x28] ldr x1, [fp, #0x38] ldr x1, [x1, #0x18] ldr x0, [fp, #0x18] ldr x2, [fp, #0x28] ldr x4, [fp, #0x30] movz x5, #0xD1FFAB1E movk x5, #0xD1FFAB1E LSL #16 movk x5, #0xD1FFAB1E LSL #32 ldr x5, [x5] blr x5 ldr x0, [fp, #0x18] str x0, [fp, #0x20] ldr x0, [fp, #0x38] ldr x0, [x0, #0x10] cbz x0, G_M000_IG04 ldr x0, [fp, #0x38] ldr x0, [x0, #0x10] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x1, [fp, #0x20] ldr x2, [fp, #0x10] ldr x2, [x2] ldr x2, [x2, #0x48] ldr x2, [x2, #0x28] blr x2 str x0, [fp, #0x20] G_M000_IG04: ldr x0, [fp, #0x20] G_M000_IG05: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 192 1333: JIT compiled System.Linq.OrderedEnumerable`2[double,double]:GetEnumerableSorter(System.Linq.EnumerableSorter`1[double]) [Tier0, IL size=96, code size=192] ; Assembly listing for method System.Linq.EnumerableSorter`2[double,double]:.ctor(System.Func`2[double,double],System.Collections.Generic.IComparer`1[double],bool,System.Linq.EnumerableSorter`1[double]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x1, [fp, #0x30] str x2, [fp, #0x28] str w3, [fp, #0x24] str x4, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x38] add x14, x14, #8 ldr x15, [fp, #0x30] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x38] add x14, x14, #16 ldr x15, [fp, #0x28] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x38] ldr w15, [fp, #0x24] strb w15, [x14, #0x28] ldr x14, [fp, #0x38] add x14, x14, #24 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 120 1334: JIT compiled System.Linq.EnumerableSorter`2[double,double]:.ctor(System.Func`2[double,double],System.Collections.Generic.IComparer`1[double],bool,System.Linq.EnumerableSorter`1[double]) [Tier0, IL size=36, code size=120] ; Assembly listing for method System.Linq.EnumerableSorter`1[double]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 1335: JIT compiled System.Linq.EnumerableSorter`1[double]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Linq.EnumerableSorter`1[double]:Sort(double[],int):int[]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str x1, [fp, #0x20] str w2, [fp, #0x1C] G_M000_IG02: ldr x0, [fp, #0x28] ldr x1, [fp, #0x20] ldr w2, [fp, #0x1C] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x10] ldr w3, [fp, #0x1C] sub w3, w3, #1 ldr x0, [fp, #0x28] ldr x1, [fp, #0x10] mov w2, wzr ldr x4, [fp, #0x28] ldr x4, [x4] ldr x4, [x4, #0x40] ldr x4, [x4, #0x30] blr x4 ldr x0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 112 1336: JIT compiled System.Linq.EnumerableSorter`1[double]:Sort(double[],int) [Tier0, IL size=22, code size=112] ; Assembly listing for method System.Linq.EnumerableSorter`1[double]:ComputeMap(double[],int):int[]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x20] str x0, [fp, #0x38] str x1, [fp, #0x30] str w2, [fp, #0x2C] G_M000_IG02: ldr x0, [fp, #0x38] ldr x1, [fp, #0x30] ldr w2, [fp, #0x2C] ldr x3, [fp, #0x38] ldr x3, [x3] ldr x3, [x3, #0x40] ldr x3, [x3, #0x20] blr x3 ldr w1, [fp, #0x2C] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x20] str wzr, [fp, #0x1C] mov w0, #0xD1FFAB1E str w0, [fp, #0x10] b G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x20] ldr w1, [fp, #0x1C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG08 add x0, x0, x1, LSL #2 add x0, x0, #16 ldr w1, [fp, #0x1C] str w1, [x0] ldr w0, [fp, #0x1C] add w0, w0, #1 str w0, [fp, #0x1C] G_M000_IG04: ldr w0, [fp, #0x10] sub w0, w0, #1 str w0, [fp, #0x10] ldr w0, [fp, #0x10] cmp w0, #0 bgt G_M000_IG06 G_M000_IG05: add x0, fp, #16 mov w1, #27 bl CORINFO_HELP_PATCHPOINT G_M000_IG06: ldr w0, [fp, #0x1C] ldr x1, [fp, #0x20] ldr w1, [x1, #0x08] cmp w0, w1 blt G_M000_IG03 ldr x0, [fp, #0x20] G_M000_IG07: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG08: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 224 1337: JIT compiled System.Linq.EnumerableSorter`1[double]:ComputeMap(double[],int) [Tier0, IL size=35, code size=224] ; Assembly listing for method System.Linq.EnumerableSorter`2[double,double]:ComputeKeys(double[],int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! str x19, [sp, #0x68] mov fp, sp str xzr, [fp, #0x48] str xzr, [fp, #0x40] str xzr, [fp, #0x30] str xzr, [fp, #0x28] str x0, [fp, #0x60] str x1, [fp, #0x58] str w2, [fp, #0x54] G_M000_IG02: ldr x0, [fp, #0x60] ldr x0, [x0, #0x08] str x0, [fp, #0x48] mov w0, #0xD1FFAB1E str w0, [fp, #0x18] ldr x19, [fp, #0x48] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #4 bl CORINFO_HELP_CLASSINIT_SHARED_DYNAMICCLASS movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] cmp x19, x1 beq G_M000_IG07 ldr w1, [fp, #0x54] sxtw x1, w1 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWARR_1_VC str x0, [fp, #0x40] str wzr, [fp, #0x3C] b G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x58] ldr w1, [fp, #0x3C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG12 add x0, x0, x1, LSL #3 add x0, x0, #16 ldr d0, [x0] ldr x0, [fp, #0x48] ldr x0, [x0, #0x08] ldr x1, [fp, #0x48] ldr x1, [x1, #0x18] blr x1 str d0, [fp, #0x20] ldr x14, [fp, #0x40] ldr w15, [fp, #0x3C] ldr w12, [x14, #0x08] cmp w15, w12 bhs G_M000_IG12 add x14, x14, x15, LSL #3 add x14, x14, #16 ldr d16, [fp, #0x20] str d16, [x14] ldr w14, [fp, #0x3C] add w14, w14, #1 str w14, [fp, #0x3C] G_M000_IG04: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG06 G_M000_IG05: add x0, fp, #24 mov w1, #50 bl CORINFO_HELP_PATCHPOINT G_M000_IG06: ldr w0, [fp, #0x3C] ldr x1, [fp, #0x40] ldr w1, [x1, #0x08] cmp w0, w1 blt G_M000_IG03 ldr x14, [fp, #0x60] add x14, x14, #32 ldr x15, [fp, #0x40] bl CORINFO_HELP_ASSIGN_REF b G_M000_IG08 G_M000_IG07: ldr x1, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x14, [fp, #0x60] add x14, x14, #32 mov x15, x0 bl CORINFO_HELP_ASSIGN_REF G_M000_IG08: ldr x0, [fp, #0x60] ldr x0, [x0, #0x18] str x0, [fp, #0x30] ldr x0, [fp, #0x30] str x0, [fp, #0x28] ldr x0, [fp, #0x30] cbnz x0, G_M000_IG10 G_M000_IG09: ldr x19, [sp, #0x68] ldp fp, lr, [sp], #0x70 ret lr G_M000_IG10: ldr x0, [fp, #0x28] ldr x1, [fp, #0x58] ldr w2, [fp, #0x54] ldr x3, [fp, #0x28] ldr x3, [x3] ldr x3, [x3, #0x40] ldr x3, [x3, #0x20] blr x3 G_M000_IG11: ldr x19, [sp, #0x68] ldp fp, lr, [sp], #0x70 ret lr G_M000_IG12: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 468 1338: JIT compiled System.Linq.EnumerableSorter`2[double,double]:ComputeKeys(double[],int) [Tier0, IL size=96, code size=468] ; Assembly listing for method System.Linq.EnumerableSorter`1[double]:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] str xzr, [fp, #0x10] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #5 bl CORINFO_HELP_CLASSINIT_SHARED_DYNAMICCLASS movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] str x1, [fp, #0x10] ldr x1, [fp, #0x10] ldr x0, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 144 1339: JIT compiled System.Linq.EnumerableSorter`1[double]:.cctor() [Tier0, IL size=22, code size=144] ; Assembly listing for method System.Linq.EnumerableSorter`1+<>c[double]:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 1340: JIT compiled System.Linq.EnumerableSorter`1+<>c[double]:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method System.Linq.EnumerableSorter`1+<>c[double]:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 1341: JIT compiled System.Linq.EnumerableSorter`1+<>c[double]:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Mathematics.Statistics+<>c:<.ctor>b__69_1(double):double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str d0, [fp, #0x10] G_M000_IG02: ldr d0, [fp, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1342: JIT compiled BenchmarkDotNet.Mathematics.Statistics+<>c:<.ctor>b__69_1(double) [Tier0, IL size=2, code size=28] ; Assembly listing for method System.Linq.EnumerableSorter`2[double,double]:QuickSort(int[],int,int):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp add x9, fp, #32 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str xzr, [x9, #0x30] str x0, [fp, #0x68] str x1, [fp, #0x60] str w2, [fp, #0x5C] str w3, [fp, #0x58] G_M000_IG02: ldr x0, [fp, #0x68] ldr x0, [x0, #0x18] cbnz x0, G_M000_IG04 ldr x0, [fp, #0x68] ldr x0, [x0, #0x10] str x0, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr x1, [fp, #0x30] cmp x0, x1 bne G_M000_IG04 ldr x0, [fp, #0x68] ldrb w0, [x0, #0x28] cbnz w0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr x1, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x20] str x0, [fp, #0x50] b G_M000_IG05 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] ldr x0, [fp, #0x28] ldr x1, [fp, #0x68] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x28] str x0, [fp, #0x50] b G_M000_IG05 G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] ldr x0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_VIRTUAL_FUNC_PTR str x0, [fp, #0x18] ldr x2, [fp, #0x18] ldr x1, [fp, #0x68] ldr x0, [fp, #0x48] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x3, [fp, #0x48] str x3, [fp, #0x50] G_M000_IG05: stp xzr, xzr, [fp, #0x38] ldr w3, [fp, #0x58] ldr w0, [fp, #0x5C] sub w3, w3, w0 add w3, w3, #1 add x0, fp, #56 ldr x1, [fp, #0x60] ldr w2, [fp, #0x5C] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x38] ldr x1, [fp, #0x40] ldr x2, [fp, #0x50] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 G_M000_IG06: ldp fp, lr, [sp], #0x70 ret lr ; Total bytes of code 444 1343: JIT compiled System.Linq.EnumerableSorter`2[double,double]:QuickSort(int[],int,int) [Tier0, IL size=109, code size=444] ; Assembly listing for method System.Linq.EnumerableSorter`2[double,double]:CompareAnyKeys_DefaultComparer_NoNext_Ascending(int,int):int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x18] str x0, [fp, #0x38] str w1, [fp, #0x34] str w2, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x38] ldr x0, [x0, #0x20] str x0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] ldr w2, [fp, #0x34] ldr w3, [x1, #0x08] cmp w2, w3 bhs G_M000_IG06 add x1, x1, x2, LSL #3 add x1, x1, #16 ldr d0, [x1] ldr x1, [fp, #0x28] ldr w2, [fp, #0x30] ldr w3, [x1, #0x08] cmp w2, w3 bhs G_M000_IG06 add x1, x1, x2, LSL #3 add x1, x1, #16 ldr d1, [x1] ldr x1, [fp, #0x18] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x20] blr x1 str w0, [fp, #0x24] ldr w0, [fp, #0x24] cbz w0, G_M000_IG04 ldr w0, [fp, #0x24] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG04: ldr w0, [fp, #0x34] ldr w1, [fp, #0x30] sub w0, w0, w1 G_M000_IG05: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG06: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 204 1344: JIT compiled System.Linq.EnumerableSorter`2[double,double]:CompareAnyKeys_DefaultComparer_NoNext_Ascending(int,int) [Tier0, IL size=41, code size=204] ; Assembly listing for method BenchmarkDotNet.Mathematics.Statistics:get_SortedValues():System.Collections.Generic.IReadOnlyList`1[double]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1345: JIT compiled BenchmarkDotNet.Mathematics.Statistics:get_SortedValues() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Mathematics.Statistics:get_N():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0xB0] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1346: JIT compiled BenchmarkDotNet.Mathematics.Statistics:get_N() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Mathematics.QuantileEstimators.Quartiles:FromSorted(System.Collections.Generic.IReadOnlyList`1[double]):Perfolizer.Mathematics.QuantileEstimators.Quartiles ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp add x9, fp, #72 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] str x0, [fp, #0x70] str x8, [fp, #0x78] G_M000_IG02: ldr x0, [fp, #0x70] str x0, [fp, #0x68] movi v0.16b, #0 ldr x0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 add x0, fp, #104 movi v0.16b, #0 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x40] add x0, fp, #104 fmov d0, #0.2500 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x60] add x0, fp, #104 fmov d0, #0.5000 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x58] add x0, fp, #104 fmov d0, #0.7500 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x50] add x0, fp, #104 fmov d0, #1.0000 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x48] stp xzr, xzr, [fp, #0x18] stp xzr, xzr, [fp, #0x28] str xzr, [fp, #0x38] add x0, fp, #24 ldr d0, [fp, #0x40] ldr d1, [fp, #0x60] ldr d2, [fp, #0x58] ldr d3, [fp, #0x50] ldr d4, [fp, #0x48] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x78] G_M000_IG03: add x1, fp, #24 ldp q16, q17, [x1] stp q16, q17, [x0] ldr x2, [x1, #0x20] str x2, [x0, #0x20] G_M000_IG04: ldp fp, lr, [sp], #0x80 ret lr ; Total bytes of code 316 1347: JIT compiled Perfolizer.Mathematics.QuantileEstimators.Quartiles:FromSorted(System.Collections.Generic.IReadOnlyList`1[double]) [Tier0, IL size=124, code size=316] ; Assembly listing for method Perfolizer.Mathematics.QuantileEstimators.QuantileEstimatorHelper:CheckArguments(System.Collections.Generic.IReadOnlyList`1[double],double) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x80]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str xzr, [x9, #0x50] str x0, [fp, #0x78] str d0, [fp, #0x70] G_M000_IG02: ldr x0, [fp, #0x78] cbnz x0, G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x50] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x48] ldr x1, [fp, #0x48] ldr x0, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x50] bl CORINFO_HELP_THROW G_M000_IG04: ldr x0, [fp, #0x78] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG06 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x58] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x40] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x38] ldr x1, [fp, #0x40] ldr x2, [fp, #0x38] ldr x0, [fp, #0x58] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x58] bl CORINFO_HELP_THROW G_M000_IG06: ldr d16, [fp, #0x70] fcmp d16, #0.0 blo G_M000_IG07 ldr d16, [fp, #0x70] fmov d17, #1.0000 fcmp d16, d17 ble G_M000_IG08 G_M000_IG07: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x68] ldr x0, [fp, #0x68] ldr d16, [fp, #0x70] str d16, [x0, #0x08] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x60] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x20] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x30] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x28] ldr x0, [fp, #0x30] ldr x1, [fp, #0x28] ldr x2, [fp, #0x68] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 str x0, [fp, #0x18] ldr x1, [fp, #0x20] ldr x2, [fp, #0x18] ldr x0, [fp, #0x60] movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x60] bl CORINFO_HELP_THROW G_M000_IG08: ldp fp, lr, [sp], #0x80 ret lr ; Total bytes of code 500 1348: JIT compiled Perfolizer.Mathematics.QuantileEstimators.QuantileEstimatorHelper:CheckArguments(System.Collections.Generic.IReadOnlyList`1[double],double) [Tier0, IL size=95, code size=500] ; Assembly listing for method Perfolizer.Mathematics.QuantileEstimators.Quartiles:g__GetQuantile|24_0(double,byref):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x20] str d0, [fp, #0x28] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #37 bl CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x20] ldr x1, [x1] ldr d0, [fp, #0x28] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 104 1349: JIT compiled Perfolizer.Mathematics.QuantileEstimators.Quartiles:g__GetQuantile|24_0(double,byref) [Tier0, IL size=18, code size=104] ; Assembly listing for method Perfolizer.Mathematics.QuantileEstimators.SimpleQuantileEstimator:.cctor() ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x15, [fp, #0x18] movz x14, #0xD1FFAB1E movk x14, #0xD1FFAB1E LSL #16 movk x14, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 1350: JIT compiled Perfolizer.Mathematics.QuantileEstimators.SimpleQuantileEstimator:.cctor() [Tier0, IL size=11, code size=84] ; Assembly listing for method Perfolizer.Mathematics.QuantileEstimators.SimpleQuantileEstimator:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 1351: JIT compiled Perfolizer.Mathematics.QuantileEstimators.SimpleQuantileEstimator:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method Perfolizer.Mathematics.QuantileEstimators.SimpleQuantileEstimator:GetQuantileFromSorted(System.Collections.Generic.IReadOnlyList`1[double],double):double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp str wzr, [fp, #0x34] str xzr, [fp, #0x28] str x0, [fp, #0x48] str x1, [fp, #0x40] str d0, [fp, #0x38] G_M000_IG02: ldr x0, [fp, #0x40] ldr d0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x40] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 sub w0, w0, #1 scvtf d16, w0 ldr d17, [fp, #0x38] fmul d16, d16, d17 str d16, [fp, #0x20] ldr d16, [fp, #0x20] fcvtzs w0, d16 str w0, [fp, #0x34] ldr d16, [fp, #0x20] ldr w0, [fp, #0x34] scvtf d17, w0 fsub d16, d16, d17 str d16, [fp, #0x28] ldr x0, [fp, #0x40] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 ldr w1, [fp, #0x34] add w1, w1, #1 cmp w0, w1 ble G_M000_IG04 ldr x0, [fp, #0x40] ldr w1, [fp, #0x34] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 ldr d16, [fp, #0x28] fmov d17, #1.0000 fsub d16, d17, d16 fmul d16, d0, d16 str d16, [fp, #0x18] ldr w1, [fp, #0x34] add w1, w1, #1 ldr x0, [fp, #0x40] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 ldr d16, [fp, #0x28] fmul d0, d0, d16 ldr d16, [fp, #0x18] fadd d0, d0, d16 G_M000_IG03: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG04: ldr x0, [fp, #0x40] ldr w1, [fp, #0x34] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 G_M000_IG05: ldp fp, lr, [sp], #0x50 ret lr ; Total bytes of code 312 1352: JIT compiled Perfolizer.Mathematics.QuantileEstimators.SimpleQuantileEstimator:GetQuantileFromSorted(System.Collections.Generic.IReadOnlyList`1[double],double) [Tier0, IL size=76, code size=312] ; Assembly listing for method System.SZArrayHelper:get_Item[double](int):double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: ldr x0, [fp, #0x28] str x0, [fp, #0x18] ldr w0, [fp, #0x24] ldr x1, [fp, #0x18] ldr w1, [x1, #0x08] cmp w0, w1 blo G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG03: ldr x0, [fp, #0x18] ldr w1, [fp, #0x24] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG05 add x0, x0, x1, LSL #3 add x0, x0, #16 ldr d0, [x0] G_M000_IG04: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG05: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 116 1353: JIT compiled System.SZArrayHelper:get_Item[double](int) [Tier0, IL size=26, code size=116] ; Assembly listing for method Perfolizer.Mathematics.QuantileEstimators.Quartiles:.ctor(double,double,double,double,double):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str d0, [fp, #0x30] str d1, [fp, #0x28] str d2, [fp, #0x20] str d3, [fp, #0x18] str d4, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x38] ldr d16, [fp, #0x30] str d16, [x0] ldr x0, [fp, #0x38] ldr d16, [fp, #0x28] str d16, [x0, #0x08] ldr x0, [fp, #0x38] ldr d16, [fp, #0x20] str d16, [x0, #0x10] ldr x0, [fp, #0x38] ldr d16, [fp, #0x18] str d16, [x0, #0x18] ldr x0, [fp, #0x38] ldr d16, [fp, #0x10] str d16, [x0, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 100 1354: JIT compiled Perfolizer.Mathematics.QuantileEstimators.Quartiles:.ctor(double,double,double,double,double) [Tier0, IL size=38, code size=100] ; Assembly listing for method Perfolizer.Mathematics.QuantileEstimators.Quartiles:get_Min():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 1355: JIT compiled Perfolizer.Mathematics.QuantileEstimators.Quartiles:get_Min() [Tier0, IL size=7, code size=44] ; Assembly listing for method Perfolizer.Mathematics.QuantileEstimators.Quartiles:get_Q0():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1356: JIT compiled Perfolizer.Mathematics.QuantileEstimators.Quartiles:get_Q0() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Mathematics.QuantileEstimators.Quartiles:get_Q1():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1357: JIT compiled Perfolizer.Mathematics.QuantileEstimators.Quartiles:get_Q1() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Mathematics.QuantileEstimators.Quartiles:get_Median():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 1358: JIT compiled Perfolizer.Mathematics.QuantileEstimators.Quartiles:get_Median() [Tier0, IL size=7, code size=44] ; Assembly listing for method Perfolizer.Mathematics.QuantileEstimators.Quartiles:get_Q2():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1359: JIT compiled Perfolizer.Mathematics.QuantileEstimators.Quartiles:get_Q2() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Mathematics.QuantileEstimators.Quartiles:get_Q3():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1360: JIT compiled Perfolizer.Mathematics.QuantileEstimators.Quartiles:get_Q3() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Mathematics.QuantileEstimators.Quartiles:get_Max():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 1361: JIT compiled Perfolizer.Mathematics.QuantileEstimators.Quartiles:get_Max() [Tier0, IL size=7, code size=44] ; Assembly listing for method Perfolizer.Mathematics.QuantileEstimators.Quartiles:get_Q4():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1362: JIT compiled Perfolizer.Mathematics.QuantileEstimators.Quartiles:get_Q4() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Mathematics.QuantileEstimators.Quartiles:get_InterquartileRange():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x10] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0x10] fsub d0, d16, d0 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 80 1363: JIT compiled Perfolizer.Mathematics.QuantileEstimators.Quartiles:get_InterquartileRange() [Tier0, IL size=14, code size=80] ; Assembly listing for method Perfolizer.Mathematics.Common.Moments:Create(System.Collections.Generic.IReadOnlyList`1[double]):Perfolizer.Mathematics.Common.Moments ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp q16, q16, [x9, #0x40] stp q16, q16, [x9, #0x60] str x0, [fp, #0x90] str x8, [fp, #0x98] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x60] ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x60] str x14, [fp, #0x88] ldr x14, [fp, #0x88] add x14, x14, #8 ldr x15, [fp, #0x90] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x88] ldr x0, [x0, #0x08] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str w0, [fp, #0x84] ldr x0, [fp, #0x88] ldr x0, [x0, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x88] str d0, [x0, #0x10] ldr w0, [fp, #0x84] cmp w0, #1 beq G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x88] ldr x0, [x0, #0x08] str x0, [fp, #0x10] ldr x0, [fp, #0x18] ldr x1, [fp, #0x88] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr w0, [fp, #0x84] sub w0, w0, #1 scvtf d16, w0 fdiv d16, d0, d16 str d16, [fp, #0x58] b G_M000_IG04 G_M000_IG03: str xzr, [fp, #0x58] G_M000_IG04: ldr d16, [fp, #0x58] str d16, [fp, #0x78] ldr x0, [fp, #0x88] mov w1, #3 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 str d0, [fp, #0x50] fmov d1, #1.5000 ldr d0, [fp, #0x78] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr d16, [fp, #0x50] fdiv d16, d16, d0 str d16, [fp, #0x70] ldr x0, [fp, #0x88] mov w1, #4 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] ldr wzr, [x0] blr x2 str d0, [fp, #0x48] fmov d1, #2.0000 ldr d0, [fp, #0x78] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 ldr d1, [fp, #0x48] fdiv d0, d1, d0 str d0, [fp, #0x68] stp xzr, xzr, [fp, #0x20] stp xzr, xzr, [fp, #0x30] str xzr, [fp, #0x40] ldr x0, [fp, #0x88] ldr d0, [x0, #0x10] add x0, fp, #32 ldr d1, [fp, #0x78] ldr d2, [fp, #0x70] ldr d3, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x98] ldp q16, q17, [fp, #0x20] stp q16, q17, [x0] ldr x1, [fp, #0x40] str x1, [x0, #0x20] G_M000_IG05: ldp fp, lr, [sp], #0xA0 ret lr ; Total bytes of code 560 1364: JIT compiled Perfolizer.Mathematics.Common.Moments:Create(System.Collections.Generic.IReadOnlyList`1[double]) [Tier0, IL size=151, code size=560] ; Assembly listing for method Perfolizer.Mathematics.Common.Moments+<>c__DisplayClass16_0:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 1365: JIT compiled Perfolizer.Mathematics.Common.Moments+<>c__DisplayClass16_0:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Linq.Enumerable:Average(System.Collections.Generic.IEnumerable`1[double]):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 1366: JIT compiled System.Linq.Enumerable:Average(System.Collections.Generic.IEnumerable`1[double]) [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Linq.Enumerable:Average[double,double,double](System.Collections.Generic.IEnumerable`1[double]):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0xA0]! mov fp, sp str xzr, [fp, #0x80] str xzr, [fp, #0x78] add x1, sp, #160 str x1, [fp, #0x98] str x0, [fp, #0x90] G_M000_IG02: mov w1, #0xD1FFAB1E str w1, [fp, #0x48] add x1, fp, #128 ldr x0, [fp, #0x90] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbz w0, G_M000_IG05 add x0, fp, #128 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 cbz w0, G_M000_IG03 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG03: ldr x0, [fp, #0x80] ldr x1, [fp, #0x88] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 str d0, [fp, #0x40] ldr d0, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x50] ldr w0, [fp, #0x88] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x38] ldr d1, [fp, #0x38] ldr d0, [fp, #0x50] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG04: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG05: ldr x0, [fp, #0x90] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x78] G_M000_IG06: ldr x0, [fp, #0x78] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG07 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG07: ldr x0, [fp, #0x78] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str d0, [fp, #0x30] ldr d0, [fp, #0x30] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x70] mov x0, #1 str x0, [fp, #0x68] b G_M000_IG09 G_M000_IG08: ldr x0, [fp, #0x78] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str d0, [fp, #0x28] ldr d0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x20] ldr d1, [fp, #0x20] ldr d0, [fp, #0x70] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x70] ldr x0, [fp, #0x68] add x0, x0, #1 str x0, [fp, #0x68] G_M000_IG09: ldr w0, [fp, #0x48] sub w0, w0, #1 str w0, [fp, #0x48] ldr w0, [fp, #0x48] cmp w0, #0 bgt G_M000_IG11 G_M000_IG10: add x0, fp, #72 mov w1, #149 bl CORINFO_HELP_PATCHPOINT G_M000_IG11: ldr x0, [fp, #0x78] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG08 ldr d0, [fp, #0x70] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x58] ldr x0, [fp, #0x68] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x18] ldr d1, [fp, #0x18] ldr d0, [fp, #0x58] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x60] b G_M000_IG12 G_M000_IG12: ldr x0, [fp, #0x98] bl G_M000_IG16 G_M000_IG13: nop G_M000_IG14: ldr d0, [fp, #0x60] G_M000_IG15: ldp fp, lr, [sp], #0xA0 ret lr G_M000_IG16: stp fp, lr, [sp, #-0x20]! add x3, fp, #160 str x3, [sp, #0x18] G_M000_IG17: ldr x0, [fp, #0x78] cbz x0, G_M000_IG18 ldr x0, [fp, #0x78] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG18: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 716 1367: JIT compiled System.Linq.Enumerable:Average[double,double,double](System.Collections.Generic.IEnumerable`1[double]) [Tier0, IL size=209, code size=716] ; Assembly listing for method System.Linq.Enumerable:Sum[double,double](System.ReadOnlySpan`1[double]):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str xzr, [fp, #0x38] str x0, [fp, #0x50] str x1, [fp, #0x58] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x48] G_M000_IG03: ldp x0, x1, [fp, #0x50] stp x0, x1, [fp, #0x38] G_M000_IG04: str wzr, [fp, #0x34] mov w0, #0xD1FFAB1E str w0, [fp, #0x20] b G_M000_IG06 G_M000_IG05: ldr w0, [fp, #0x34] ldr w1, [fp, #0x40] cmp w0, w1 bhs G_M000_IG10 ldr x0, [fp, #0x38] ldr w1, [fp, #0x34] mov w1, w1 lsl x1, x1, #3 ldr d0, [x0, x1] str d0, [fp, #0x28] ldr d0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x18] ldr d1, [fp, #0x18] ldr d0, [fp, #0x48] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x48] ldr w0, [fp, #0x34] add w0, w0, #1 str w0, [fp, #0x34] G_M000_IG06: ldr w0, [fp, #0x20] sub w0, w0, #1 str w0, [fp, #0x20] ldr w0, [fp, #0x20] cmp w0, #0 bgt G_M000_IG08 G_M000_IG07: add x0, fp, #32 mov w1, #61 bl CORINFO_HELP_PATCHPOINT G_M000_IG08: ldr w0, [fp, #0x34] ldr w1, [fp, #0x40] cmp w0, w1 blt G_M000_IG05 ldr d0, [fp, #0x48] G_M000_IG09: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG10: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 252 1368: JIT compiled System.Linq.Enumerable:Sum[double,double](System.ReadOnlySpan`1[double]) [Tier0, IL size=73, code size=252] ; Assembly listing for method System.Double:CreateChecked[double](double):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str d0, [fp, #0x18] G_M000_IG02: ldr d0, [fp, #0x18] str d0, [fp, #0x10] b G_M000_IG03 G_M000_IG03: ldr d0, [fp, #0x10] G_M000_IG04: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 36 1369: JIT compiled System.Double:CreateChecked[double](double) [Tier0, IL size=74, code size=36] ; Assembly listing for method System.Numerics.IAdditionOperators`3[double,double,double]:op_CheckedAddition(double,double):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str d0, [fp, #0x18] str d1, [fp, #0x10] G_M000_IG02: ldr d0, [fp, #0x18] ldr d1, [fp, #0x10] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 52 1370: JIT compiled System.Numerics.IAdditionOperators`3[double,double,double]:op_CheckedAddition(double,double) [Tier0, IL size=14, code size=52] ; Assembly listing for method System.Double:CreateChecked[int](int):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str w0, [fp, #0x1C] G_M000_IG02: b G_M000_IG03 G_M000_IG03: add x1, fp, #16 ldr w0, [fp, #0x1C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG04 add x1, fp, #16 ldr w0, [fp, #0x1C] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG04: ldr d0, [fp, #0x10] G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 112 1371: JIT compiled System.Double:CreateChecked[int](int) [Tier0, IL size=74, code size=112] ; Assembly listing for method System.Double:TryConvertFrom[int](int,byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str w0, [fp, #0x5C] str x1, [fp, #0x50] G_M000_IG02: b G_M000_IG03 G_M000_IG03: b G_M000_IG04 G_M000_IG04: ldr w0, [fp, #0x5C] str w0, [fp, #0x40] ldr w0, [fp, #0x40] scvtf d16, w0 ldr x0, [fp, #0x50] str d16, [x0] mov w0, #1 G_M000_IG05: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 60 1372: JIT compiled System.Double:TryConvertFrom[int](int,byref) [Tier0, IL size=391, code size=60] ; Assembly listing for method System.Linq.Enumerable:Sum[double](System.Collections.Generic.IEnumerable`1[double],System.Func`2[double,double]):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 52 1373: JIT compiled System.Linq.Enumerable:Sum[double](System.Collections.Generic.IEnumerable`1[double],System.Func`2[double,double]) [Tier0, IL size=8, code size=52] ; Assembly listing for method System.Linq.Enumerable:Sum[double,double,double](System.Collections.Generic.IEnumerable`1[double],System.Func`2[double,double]):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str xzr, [fp, #0x38] add x2, sp, #96 str x2, [fp, #0x58] str x0, [fp, #0x50] str x1, [fp, #0x48] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x28] ldr x0, [fp, #0x50] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x48] cbnz x0, G_M000_IG04 mov w0, #15 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x40] ldr x0, [fp, #0x50] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x38] G_M000_IG05: b G_M000_IG07 G_M000_IG06: ldr x0, [fp, #0x38] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str d0, [fp, #0x30] ldr x0, [fp, #0x48] ldr x0, [x0, #0x08] ldr d0, [fp, #0x30] ldr x1, [fp, #0x48] ldr x1, [x1, #0x18] blr x1 str d0, [fp, #0x20] ldr d0, [fp, #0x20] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x18] ldr d1, [fp, #0x18] ldr d0, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x40] G_M000_IG07: ldr w0, [fp, #0x28] sub w0, w0, #1 str w0, [fp, #0x28] ldr w0, [fp, #0x28] cmp w0, #0 bgt G_M000_IG09 G_M000_IG08: add x0, fp, #40 mov w1, #79 bl CORINFO_HELP_PATCHPOINT G_M000_IG09: ldr x0, [fp, #0x38] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG06 b G_M000_IG10 G_M000_IG10: ldr x0, [fp, #0x58] bl G_M000_IG14 G_M000_IG11: nop G_M000_IG12: ldr d0, [fp, #0x40] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG13: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG14: stp fp, lr, [sp, #-0x20]! add x3, fp, #96 str x3, [sp, #0x18] G_M000_IG15: ldr x0, [fp, #0x38] cbz x0, G_M000_IG16 ldr x0, [fp, #0x38] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG16: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 436 1374: JIT compiled System.Linq.Enumerable:Sum[double,double,double](System.Collections.Generic.IEnumerable`1[double],System.Func`2[double,double]) [Tier0, IL size=112, code size=436] ; Assembly listing for method System.SZArrayHelper:GetEnumerator[double]():System.Collections.Generic.IEnumerator`1[double]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr w0, [x0, #0x08] cbz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #61 bl CORINFO_HELP_CLASSINIT_SHARED_DYNAMICCLASS movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 144 1375: JIT compiled System.SZArrayHelper:GetEnumerator[double]() [Tier0, IL size=24, code size=144] ; Assembly listing for method System.SZGenericArrayEnumerator`1[double]:.ctor(double[]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 52 1376: JIT compiled System.SZGenericArrayEnumerator`1[double]:.ctor(double[]) [Tier0, IL size=8, code size=52] ; Assembly listing for method System.SZGenericArrayEnumeratorBase:.ctor(System.Array):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x18] add x14, x14, #8 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x18] movn w1, #0 str w1, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 76 1377: JIT compiled System.SZGenericArrayEnumeratorBase:.ctor(System.Array) [Tier0, IL size=21, code size=76] ; Assembly listing for method System.SZGenericArrayEnumerator`1[double]:get_Current():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] ldr w0, [x0, #0x10] str w0, [fp, #0x24] ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] str x0, [fp, #0x18] ldr w0, [fp, #0x24] ldr x1, [fp, #0x18] ldr w1, [x1, #0x08] cmp w0, w1 blo G_M000_IG03 ldr w0, [fp, #0x24] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x18] ldr w1, [fp, #0x24] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG05 add x0, x0, x1, LSL #3 add x0, x0, #16 ldr d0, [x0] G_M000_IG04: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG05: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 132 1378: JIT compiled System.SZGenericArrayEnumerator`1[double]:get_Current() [Tier0, IL size=39, code size=132] ; Assembly listing for method Perfolizer.Mathematics.Common.Moments+<>c__DisplayClass16_0:b__0(double):double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str d0, [fp, #0x10] G_M000_IG02: ldr d0, [fp, #0x10] ldr x0, [fp, #0x18] ldr d1, [x0, #0x10] fsub d0, d0, d1 fmov d1, #2.0000 bl System.Math:Pow(double,double):double G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 48 1379: JIT compiled Perfolizer.Mathematics.Common.Moments+<>c__DisplayClass16_0:b__0(double) [Tier0, IL size=23, code size=48] ; Assembly listing for method System.Double:CreateTruncating[double](double):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str d0, [fp, #0x18] G_M000_IG02: ldr d0, [fp, #0x18] str d0, [fp, #0x10] b G_M000_IG03 G_M000_IG03: ldr d0, [fp, #0x10] G_M000_IG04: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 36 1380: JIT compiled System.Double:CreateTruncating[double](double) [Tier0, IL size=74, code size=36] ; Assembly listing for method Perfolizer.Mathematics.Common.Moments+<>c__DisplayClass16_0:g__CalcCentralMoment|1(int):double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x28] str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str w1, [fp, #0x34] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x20] str x14, [fp, #0x28] ldr x14, [fp, #0x28] add x14, x14, #8 ldr x15, [fp, #0x38] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x28] ldr w1, [fp, #0x34] str w1, [x0, #0x10] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x38] ldr x0, [x0, #0x08] str x0, [fp, #0x10] ldr x0, [fp, #0x18] ldr x1, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 ldr x0, [fp, #0x10] ldr x1, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 220 1381: JIT compiled Perfolizer.Mathematics.Common.Moments+<>c__DisplayClass16_0:g__CalcCentralMoment|1(int) [Tier0, IL size=44, code size=220] ; Assembly listing for method Perfolizer.Mathematics.Common.Moments+<>c__DisplayClass16_1:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 1382: JIT compiled Perfolizer.Mathematics.Common.Moments+<>c__DisplayClass16_1:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method System.Linq.Enumerable:Average[double](System.Collections.Generic.IEnumerable`1[double],System.Func`2[double,double]):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 52 1383: JIT compiled System.Linq.Enumerable:Average[double](System.Collections.Generic.IEnumerable`1[double],System.Func`2[double,double]) [Tier0, IL size=8, code size=52] ; Assembly listing for method System.Linq.Enumerable:Average[double,double,double,double](System.Collections.Generic.IEnumerable`1[double],System.Func`2[double,double]):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x90]! mov fp, sp str xzr, [fp, #0x70] add x2, sp, #144 str x2, [fp, #0x88] str x0, [fp, #0x80] str x1, [fp, #0x78] G_M000_IG02: mov w0, #0xD1FFAB1E str w0, [fp, #0x48] ldr x0, [fp, #0x80] cbnz x0, G_M000_IG03 mov w0, #16 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x78] cbnz x0, G_M000_IG04 mov w0, #15 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldr x0, [fp, #0x80] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str x0, [fp, #0x70] G_M000_IG05: ldr x0, [fp, #0x70] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG06 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG06: ldr x0, [fp, #0x70] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str d0, [fp, #0x40] ldr d0, [fp, #0x40] ldr x0, [fp, #0x78] ldr x0, [x0, #0x08] ldr x1, [fp, #0x78] ldr x1, [x1, #0x18] blr x1 str d0, [fp, #0x38] ldr d0, [fp, #0x38] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x68] mov x0, #1 str x0, [fp, #0x60] b G_M000_IG08 G_M000_IG07: ldr x0, [fp, #0x70] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 str d0, [fp, #0x30] ldr d0, [fp, #0x30] ldr x0, [fp, #0x78] ldr x0, [x0, #0x08] ldr x1, [fp, #0x78] ldr x1, [x1, #0x18] blr x1 str d0, [fp, #0x28] ldr d0, [fp, #0x28] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x20] ldr d1, [fp, #0x20] ldr d0, [fp, #0x68] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x68] ldr x0, [fp, #0x60] add x0, x0, #1 str x0, [fp, #0x60] G_M000_IG08: ldr w0, [fp, #0x48] sub w0, w0, #1 str w0, [fp, #0x48] ldr w0, [fp, #0x48] cmp w0, #0 bgt G_M000_IG10 G_M000_IG09: add x0, fp, #72 mov w1, #110 bl CORINFO_HELP_PATCHPOINT G_M000_IG10: ldr x0, [fp, #0x70] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG07 ldr d0, [fp, #0x68] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x50] ldr x0, [fp, #0x60] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x18] ldr d1, [fp, #0x18] ldr d0, [fp, #0x50] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 str d0, [fp, #0x58] b G_M000_IG11 G_M000_IG11: ldr x0, [fp, #0x88] bl G_M000_IG15 G_M000_IG12: nop G_M000_IG13: ldr d0, [fp, #0x58] G_M000_IG14: ldp fp, lr, [sp], #0x90 ret lr G_M000_IG15: stp fp, lr, [sp, #-0x20]! add x3, fp, #144 str x3, [sp, #0x18] G_M000_IG16: ldr x0, [fp, #0x70] cbz x0, G_M000_IG17 ldr x0, [fp, #0x70] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG17: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 632 1384: JIT compiled System.Linq.Enumerable:Average[double,double,double,double](System.Collections.Generic.IEnumerable`1[double],System.Func`2[double,double]) [Tier0, IL size=168, code size=632] ; Assembly listing for method Perfolizer.Mathematics.Common.Moments+<>c__DisplayClass16_1:b__2(double):double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str d0, [fp, #0x10] G_M000_IG02: ldr d0, [fp, #0x10] ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] ldr d1, [x0, #0x10] fsub d0, d0, d1 ldr x0, [fp, #0x18] ldr w0, [x0, #0x10] scvtf d1, w0 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 76 1385: JIT compiled Perfolizer.Mathematics.Common.Moments+<>c__DisplayClass16_1:b__2(double) [Tier0, IL size=26, code size=76] ; Assembly listing for method Perfolizer.Mathematics.Common.MathExtensions:Pow(double,double):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str d0, [fp, #0x18] str d1, [fp, #0x10] G_M000_IG02: ldr d0, [fp, #0x18] ldr d1, [fp, #0x10] bl System.Math:Pow(double,double):double G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 36 1386: JIT compiled Perfolizer.Mathematics.Common.MathExtensions:Pow(double,double) [Tier0, IL size=8, code size=36] ; Assembly listing for method System.Double:CreateChecked[long](long):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: b G_M000_IG03 G_M000_IG03: add x1, fp, #16 ldr x0, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG04 add x1, fp, #16 ldr x0, [fp, #0x18] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 cbnz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 G_M000_IG04: ldr d0, [fp, #0x10] G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 112 1387: JIT compiled System.Double:CreateChecked[long](long) [Tier0, IL size=74, code size=112] ; Assembly listing for method System.Double:TryConvertFrom[long](long,byref):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str x0, [fp, #0x58] str x1, [fp, #0x50] G_M000_IG02: b G_M000_IG03 G_M000_IG03: b G_M000_IG04 G_M000_IG04: b G_M000_IG05 G_M000_IG05: ldr x0, [fp, #0x58] str x0, [fp, #0x38] ldr x0, [fp, #0x38] scvtf d16, x0 ldr x0, [fp, #0x50] str d16, [x0] mov w0, #1 G_M000_IG06: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 64 1388: JIT compiled System.Double:TryConvertFrom[long](long,byref) [Tier0, IL size=391, code size=64] ; Assembly listing for method Perfolizer.Mathematics.Common.Moments:.ctor(double,double,double,double):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str d0, [fp, #0x30] str d1, [fp, #0x28] str d2, [fp, #0x20] str d3, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x38] stp xzr, xzr, [x0] stp xzr, xzr, [x0, #0x10] str xzr, [x0, #0x20] ldr x0, [fp, #0x38] ldr d16, [fp, #0x30] str d16, [x0] ldr x0, [fp, #0x38] ldr d16, [fp, #0x28] str d16, [x0, #0x08] ldr x0, [fp, #0x38] ldr d16, [fp, #0x20] str d16, [x0, #0x10] ldr x0, [fp, #0x38] ldr d16, [fp, #0x18] str d16, [x0, #0x18] ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x10] ldr d0, [fp, #0x10] bl System.Math:Sqrt(double):double ldr x0, [fp, #0x38] str d0, [x0, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 144 1389: JIT compiled Perfolizer.Mathematics.Common.Moments:.ctor(double,double,double,double) [Tier0, IL size=54, code size=144] ; Assembly listing for method Perfolizer.Mathematics.Common.Moments:get_Variance():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1390: JIT compiled Perfolizer.Mathematics.Common.Moments:get_Variance() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Mathematics.Common.Moments:get_Mean():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1391: JIT compiled Perfolizer.Mathematics.Common.Moments:get_Mean() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Mathematics.Common.Moments:get_StandardDeviation():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0, #0x20] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1392: JIT compiled Perfolizer.Mathematics.Common.Moments:get_StandardDeviation() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Mathematics.Common.Moments:get_Skewness():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1393: JIT compiled Perfolizer.Mathematics.Common.Moments:get_Skewness() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Mathematics.Common.Moments:get_Kurtosis():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1394: JIT compiled Perfolizer.Mathematics.Common.Moments:get_Kurtosis() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Mathematics.OutlierDetection.TukeyOutlierDetector:FromQuartiles(Perfolizer.Mathematics.QuantileEstimators.Quartiles,double):Perfolizer.Mathematics.OutlierDetection.TukeyOutlierDetector ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp str xzr, [fp, #0x48] str xzr, [fp, #0x18] str x0, [fp, #0x58] str d0, [fp, #0x50] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x48] ldr x0, [fp, #0x48] str x0, [fp, #0x18] ldr x0, [fp, #0x58] ldp q0, q16, [x0] stp q0, q16, [fp, #0x20] ldr x1, [x0, #0x20] str x1, [fp, #0x40] ldr x0, [fp, #0x18] add x1, fp, #32 ldr d0, [fp, #0x50] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x48] G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 116 1395: JIT compiled Perfolizer.Mathematics.OutlierDetection.TukeyOutlierDetector:FromQuartiles(Perfolizer.Mathematics.QuantileEstimators.Quartiles,double) [Tier0, IL size=8, code size=116] ; Assembly listing for method Perfolizer.Mathematics.OutlierDetection.TukeyOutlierDetector:.ctor(Perfolizer.Mathematics.QuantileEstimators.Quartiles,double):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x1, [fp, #0x30] str d0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x20] ldr d16, [fp, #0x20] str d16, [fp, #0x10] ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0x28] fmul d16, d0, d16 ldr d17, [fp, #0x10] fsub d16, d17, d16 ldr x0, [fp, #0x38] str d16, [x0, #0x08] ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str d0, [fp, #0x18] ldr d16, [fp, #0x18] str d16, [fp, #0x10] ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0x28] fmul d16, d0, d16 ldr d17, [fp, #0x10] fadd d16, d17, d16 ldr x0, [fp, #0x38] str d16, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 220 1396: JIT compiled Perfolizer.Mathematics.OutlierDetection.TukeyOutlierDetector:.ctor(Perfolizer.Mathematics.QuantileEstimators.Quartiles,double) [Tier0, IL size=53, code size=220] ; Assembly listing for method Perfolizer.Mathematics.OutlierDetection.OutlierDetector:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 1397: JIT compiled Perfolizer.Mathematics.OutlierDetection.OutlierDetector:.ctor() [Tier0, IL size=7, code size=44] ; Assembly listing for method Perfolizer.Mathematics.OutlierDetection.TukeyOutlierDetector:get_LowerFence():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1398: JIT compiled Perfolizer.Mathematics.OutlierDetection.TukeyOutlierDetector:get_LowerFence() [Tier0, IL size=7, code size=28] ; Assembly listing for method Perfolizer.Mathematics.OutlierDetection.TukeyOutlierDetector:get_UpperFence():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1399: JIT compiled Perfolizer.Mathematics.OutlierDetection.TukeyOutlierDetector:get_UpperFence() [Tier0, IL size=7, code size=28] ; Assembly listing for method System.Linq.Enumerable+WhereArrayIterator`1[double]:.ctor(double[],System.Func`2[double,bool]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x0, [fp, #0x28] str x1, [fp, #0x20] str x2, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x28] add x14, x14, #24 ldr x15, [fp, #0x20] bl CORINFO_HELP_ASSIGN_REF ldr x14, [fp, #0x28] add x14, x14, #32 ldr x15, [fp, #0x18] bl CORINFO_HELP_ASSIGN_REF G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 1400: JIT compiled System.Linq.Enumerable+WhereArrayIterator`1[double]:.ctor(double[],System.Func`2[double,bool]) [Tier0, IL size=21, code size=84] ; Assembly listing for method System.Linq.Enumerable+WhereArrayIterator`1[double]:ToArray():double[]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x70]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp q16, q16, [x9, #0x20] stp xzr, xzr, [x9, #0x40] str xzr, [x9, #0x50] str x0, [fp, #0x68] G_M000_IG02: ldr x1, [fp, #0x68] ldr x1, [x1, #0x18] ldr w1, [x1, #0x08] add x0, fp, #56 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x68] ldr x0, [x0, #0x18] str x0, [fp, #0x30] str wzr, [fp, #0x2C] mov w0, #0xD1FFAB1E str w0, [fp, #0x18] b G_M000_IG05 G_M000_IG03: ldr x0, [fp, #0x30] ldr w1, [fp, #0x2C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG09 add x0, x0, x1, LSL #3 add x0, x0, #16 ldr d0, [x0] str d0, [fp, #0x20] ldr x0, [fp, #0x68] ldr x0, [x0, #0x20] str x0, [fp, #0x10] ldr x0, [fp, #0x10] ldr x0, [x0, #0x08] ldr d0, [fp, #0x20] ldr x1, [fp, #0x10] ldr x1, [x1, #0x18] blr x1 cbz w0, G_M000_IG04 add x0, fp, #56 ldr d0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG04: ldr w0, [fp, #0x2C] add w0, w0, #1 str w0, [fp, #0x2C] G_M000_IG05: ldr w0, [fp, #0x18] sub w0, w0, #1 str w0, [fp, #0x18] ldr w0, [fp, #0x18] cmp w0, #0 bgt G_M000_IG07 G_M000_IG06: add x0, fp, #24 mov w1, #60 bl CORINFO_HELP_PATCHPOINT G_M000_IG07: ldr w0, [fp, #0x2C] ldr x1, [fp, #0x30] ldr w1, [x1, #0x08] cmp w0, w1 blt G_M000_IG03 add x0, fp, #56 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG08: ldp fp, lr, [sp], #0x70 ret lr G_M000_IG09: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 312 1401: JIT compiled System.Linq.Enumerable+WhereArrayIterator`1[double]:ToArray() [Tier0, IL size=74, code size=312] ; Assembly listing for method Perfolizer.Mathematics.OutlierDetection.OutlierDetector:IsOutlier(double):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str d0, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [fp, #0x10] ldr x1, [fp, #0x18] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x20] blr x1 cbnz w0, G_M000_IG04 ldr x0, [fp, #0x18] ldr d0, [fp, #0x10] ldr x1, [fp, #0x18] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x28] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr G_M000_IG04: mov w0, #1 G_M000_IG05: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 96 1402: JIT compiled Perfolizer.Mathematics.OutlierDetection.OutlierDetector:IsOutlier(double) [Tier0, IL size=19, code size=96] ; Assembly listing for method Perfolizer.Mathematics.OutlierDetection.TukeyOutlierDetector:IsLowerOutlier(double):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str d0, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0x10] fcmp d0, d16 cset x0, gt G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 60 1403: JIT compiled Perfolizer.Mathematics.OutlierDetection.TukeyOutlierDetector:IsLowerOutlier(double) [Tier0, IL size=10, code size=60] ; Assembly listing for method Perfolizer.Mathematics.OutlierDetection.TukeyOutlierDetector:IsUpperOutlier(double):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str d0, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr d16, [fp, #0x10] fcmp d0, d16 cset x0, lo G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 60 1404: JIT compiled Perfolizer.Mathematics.OutlierDetection.TukeyOutlierDetector:IsUpperOutlier(double) [Tier0, IL size=10, code size=60] ; Assembly listing for method BenchmarkDotNet.Mathematics.Statistics:get_StandardDeviation():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0, #0x98] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1405: JIT compiled BenchmarkDotNet.Mathematics.Statistics:get_StandardDeviation() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Mathematics.Statistics:get_Mean():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0, #0x60] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1406: JIT compiled BenchmarkDotNet.Mathematics.Statistics:get_Mean() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Mathematics.Statistics:get_StandardError():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0, #0x88] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1407: JIT compiled BenchmarkDotNet.Mathematics.Statistics:get_StandardError() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Mathematics.PercentileValues:.ctor(System.Collections.Generic.IReadOnlyList`1[double]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x14, [fp, #0x18] add x14, x14, #8 ldr x15, [fp, #0x10] bl CORINFO_HELP_ASSIGN_REF ldr x0, [fp, #0x18] mov w1, wzr movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x18] str d0, [x0, #0x10] ldr x0, [fp, #0x18] mov w1, #25 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x18] str d0, [x0, #0x18] ldr x0, [fp, #0x18] mov w1, #50 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x18] str d0, [x0, #0x20] ldr x0, [fp, #0x18] mov w1, #67 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x18] str d0, [x0, #0x28] ldr x0, [fp, #0x18] mov w1, #80 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x18] str d0, [x0, #0x30] ldr x0, [fp, #0x18] mov w1, #85 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x18] str d0, [x0, #0x38] ldr x0, [fp, #0x18] mov w1, #90 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x18] str d0, [x0, #0x40] ldr x0, [fp, #0x18] mov w1, #95 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x18] str d0, [x0, #0x48] ldr x0, [fp, #0x18] mov w1, #100 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x18] str d0, [x0, #0x50] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 388 1408: JIT compiled BenchmarkDotNet.Mathematics.PercentileValues:.ctor(System.Collections.Generic.IReadOnlyList`1[double]) [Tier0, IL size=139, code size=388] ; Assembly listing for method BenchmarkDotNet.Mathematics.PercentileValues:Percentile(int):double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str w1, [fp, #0x24] G_M000_IG02: ldr x0, [fp, #0x28] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr w1, [fp, #0x24] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 1409: JIT compiled BenchmarkDotNet.Mathematics.PercentileValues:Percentile(int) [Tier0, IL size=13, code size=84] ; Assembly listing for method BenchmarkDotNet.Mathematics.PercentileValues:get_SortedValues():System.Collections.Generic.IReadOnlyList`1[double]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1410: JIT compiled BenchmarkDotNet.Mathematics.PercentileValues:get_SortedValues() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Mathematics.PercentileValues:Percentile(System.Collections.Generic.IReadOnlyList`1[double],int):double ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x50]! mov fp, sp add x9, fp, #16 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str x0, [fp, #0x48] str w1, [fp, #0x44] G_M000_IG02: ldr x0, [fp, #0x48] cbnz x0, G_M000_IG04 G_M000_IG03: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x28] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x20] ldr x1, [fp, #0x20] ldr x0, [fp, #0x28] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x28] bl CORINFO_HELP_THROW G_M000_IG04: ldr w0, [fp, #0x44] tbnz w0, #31, G_M000_IG05 ldr w0, [fp, #0x44] cmp w0, #100 ble G_M000_IG06 G_M000_IG05: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x38] ldr x0, [fp, #0x38] ldr w1, [fp, #0x44] str w1, [x0, #0x08] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x30] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x18] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x10] ldr x1, [fp, #0x18] ldr x3, [fp, #0x10] ldr x2, [fp, #0x38] ldr x0, [fp, #0x30] movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x30] bl CORINFO_HELP_THROW G_M000_IG06: ldr x0, [fp, #0x48] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 cbnz w0, G_M000_IG08 movi v0.16b, #0 G_M000_IG07: ldp fp, lr, [sp], #0x50 ret lr G_M000_IG08: ldr w0, [fp, #0x44] scvtf d0, w0 ldr d16, [@RWD00] fdiv d0, d0, d16 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] ldr x1, [fp, #0x48] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 G_M000_IG09: ldp fp, lr, [sp], #0x50 ret lr RWD00 dq 4059000000000000h ; 100 ; Total bytes of code 388 1411: JIT compiled BenchmarkDotNet.Mathematics.PercentileValues:Percentile(System.Collections.Generic.IReadOnlyList`1[double],int) [Tier0, IL size=87, code size=388] ; Assembly listing for method BenchmarkDotNet.Mathematics.Statistics:get_Median():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0, #0x58] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1412: JIT compiled BenchmarkDotNet.Mathematics.Statistics:get_Median() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults+<>c:b__18_1(BenchmarkDotNet.Reports.Measurement):double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 48 1413: JIT compiled BenchmarkDotNet.Engines.RunResults+<>c:b__18_1(BenchmarkDotNet.Reports.Measurement) [Tier0, IL size=8, code size=48] ; Assembly listing for method System.SZArrayHelper:GetEnumerator[BenchmarkDotNet.Reports.Measurement]():System.Collections.Generic.IEnumerator`1[BenchmarkDotNet.Reports.Measurement]:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str x0, [fp, #0x28] G_M000_IG02: ldr x0, [fp, #0x28] str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr w0, [x0, #0x08] cbz w0, G_M000_IG04 movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr x1, [fp, #0x20] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 mov w1, #62 bl CORINFO_HELP_CLASSINIT_SHARED_DYNAMICCLASS movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] G_M000_IG05: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 144 1414: JIT compiled System.SZArrayHelper:GetEnumerator[BenchmarkDotNet.Reports.Measurement]() [Tier0, IL size=24, code size=144] ; Assembly listing for method System.SZGenericArrayEnumerator`1[BenchmarkDotNet.Reports.Measurement]:.ctor(BenchmarkDotNet.Reports.Measurement[]):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x1, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 52 1415: JIT compiled System.SZGenericArrayEnumerator`1[BenchmarkDotNet.Reports.Measurement]:.ctor(BenchmarkDotNet.Reports.Measurement[]) [Tier0, IL size=8, code size=52] ; Assembly listing for method System.SZGenericArrayEnumerator`1[BenchmarkDotNet.Reports.Measurement]:get_Current():BenchmarkDotNet.Reports.Measurement:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x28] str x8, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] ldr w0, [x0, #0x10] str w0, [fp, #0x1C] ldr x0, [fp, #0x28] ldr x0, [x0, #0x08] str x0, [fp, #0x10] ldr w0, [fp, #0x1C] ldr x1, [fp, #0x10] ldr w1, [x1, #0x08] cmp w0, w1 blo G_M000_IG03 ldr w0, [fp, #0x1C] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldr x0, [fp, #0x10] ldr w1, [fp, #0x1C] ldr w2, [x0, #0x08] cmp w1, w2 bhs G_M000_IG05 add x0, x0, x1, LSL #5 add x0, x0, #16 ldr x1, [fp, #0x20] ldp q16, q17, [x0] stp q16, q17, [x1] G_M000_IG04: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG05: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 144 1416: JIT compiled System.SZGenericArrayEnumerator`1[BenchmarkDotNet.Reports.Measurement]:get_Current() [Tier0, IL size=39, code size=144] ; Assembly listing for method BenchmarkDotNet.Mathematics.Statistics:IsActualOutlier(double,int):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str xzr, [fp, #0x20] str xzr, [fp, #0x18] str xzr, [fp, #0x10] str x0, [fp, #0x38] str w1, [fp, #0x2C] str d0, [fp, #0x30] G_M000_IG02: ldr w0, [fp, #0x2C] cmp w0, #3 bhi G_M000_IG03 ldr w0, [fp, #0x2C] mov w0, w0 adr x1, [@RWD00] ldr w1, [x1, x0, LSL #2] adr x2, [G_M000_IG02] add x1, x1, x2 br x1 G_M000_IG03: b G_M000_IG12 G_M000_IG04: mov w0, wzr G_M000_IG05: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG06: ldr x0, [fp, #0x38] ldr d0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG07: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG08: ldr x0, [fp, #0x38] ldr d0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG09: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG10: ldr x0, [fp, #0x38] ldr d0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG11: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG12: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x20] ldr x0, [fp, #0x20] ldr w1, [fp, #0x2C] str w1, [x0, #0x08] movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x18] mov w0, #0xD1FFAB1E movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_STRCNS str x0, [fp, #0x10] ldr x1, [fp, #0x10] ldr x2, [fp, #0x20] ldr x0, [fp, #0x18] mov x3, xzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x18] bl CORINFO_HELP_THROW brk_windows #0 RWD00 dd G_M000_IG04 - G_M000_IG02 dd G_M000_IG06 - G_M000_IG02 dd G_M000_IG08 - G_M000_IG02 dd G_M000_IG10 - G_M000_IG02 ; Total bytes of code 320 1417: JIT compiled BenchmarkDotNet.Mathematics.Statistics:IsActualOutlier(double,int) [Tier0, IL size=68, code size=320] ; Assembly listing for method BenchmarkDotNet.Mathematics.Statistics:IsUpperOutlier(double):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str xzr, [fp, #0x18] str x0, [fp, #0x28] str d0, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x28] ldr x0, [x0, #0x38] str x0, [fp, #0x18] ldr x0, [fp, #0x18] ldr d0, [fp, #0x20] ldr x1, [fp, #0x18] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x28] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 68 1418: JIT compiled BenchmarkDotNet.Mathematics.Statistics:IsUpperOutlier(double) [Tier0, IL size=13, code size=68] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults:IsSuspiciouslySmall(double):bool ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str d0, [fp, #0x18] G_M000_IG02: ldr d16, [fp, #0x18] ldr d17, [@RWD00] fcmp d16, d17 cset x0, lo G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr RWD00 dq 3FB999999999999Ah ; 0.1 ; Total bytes of code 36 1419: JIT compiled BenchmarkDotNet.Engines.RunResults:IsSuspiciouslySmall(double) [Tier0, IL size=13, code size=36] ; Assembly listing for method BenchmarkDotNet.Reports.Measurement:get_LaunchIndex():int:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1420: JIT compiled BenchmarkDotNet.Reports.Measurement:get_LaunchIndex() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults+d__18:System.Collections.Generic.IEnumerator.get_Current():BenchmarkDotNet.Reports.Measurement:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x8, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] ldp q16, q17, [x0, #0x30] stp q16, q17, [x1] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 40 1421: JIT compiled BenchmarkDotNet.Engines.RunResults+d__18:System.Collections.Generic.IEnumerator.get_Current() [Tier0, IL size=7, code size=40] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults+d__18:<>m__Finally1():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movn w11, #0 str w11, [x0, #0x20] ldr x0, [fp, #0x18] ldr x0, [x0, #0x10] cbz x0, G_M000_IG03 ldr x0, [fp, #0x18] ldr x0, [x0, #0x10] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x1, [x11] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 72 1422: JIT compiled BenchmarkDotNet.Engines.RunResults+d__18:<>m__Finally1() [Tier0, IL size=27, code size=72] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults+d__18:System.IDisposable.Dispose():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str wzr, [fp, #0x1C] add x1, sp, #48 str x1, [fp, #0x28] str x0, [fp, #0x20] G_M000_IG02: ldr x0, [fp, #0x20] ldr w0, [x0, #0x20] str w0, [fp, #0x1C] ldr w0, [fp, #0x1C] cmn w0, #3 beq G_M000_IG03 ldr w0, [fp, #0x1C] cmp w0, #1 bne G_M000_IG06 G_M000_IG03: b G_M000_IG04 G_M000_IG04: ldr x0, [fp, #0x28] bl G_M000_IG07 G_M000_IG05: nop G_M000_IG06: ldp fp, lr, [sp], #0x30 ret lr G_M000_IG07: stp fp, lr, [sp, #-0x20]! add x3, fp, #48 str x3, [sp, #0x18] G_M000_IG08: ldr x0, [fp, #0x20] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG09: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 128 1423: JIT compiled BenchmarkDotNet.Engines.RunResults+d__18:System.IDisposable.Dispose() [Tier0, IL size=27, code size=128] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults:get_GCStats():BenchmarkDotNet.Engines.GcStats:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x8, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] G_M000_IG03: add x2, x0, #24 ldp q16, q17, [x2] stp q16, q17, [x1] G_M000_IG04: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 44 1424: JIT compiled BenchmarkDotNet.Engines.RunResults:get_GCStats() [Tier0, IL size=7, code size=44] ; Assembly listing for method BenchmarkDotNet.Engines.GcStats:Equals(BenchmarkDotNet.Engines.GcStats):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x1, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x2C] ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w1, [fp, #0x2C] cmp w0, w1 bne G_M000_IG04 ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x28] ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w1, [fp, #0x28] cmp w0, w1 bne G_M000_IG04 ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x24] ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr w1, [fp, #0x24] cmp w0, w1 bne G_M000_IG04 ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x18] cmp x0, x1 bne G_M000_IG04 ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x10] cmp x0, x1 cset x0, eq G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG04: mov w0, wzr G_M000_IG05: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 356 1425: JIT compiled BenchmarkDotNet.Engines.GcStats:Equals(BenchmarkDotNet.Engines.GcStats) [Tier0, IL size=78, code size=356] ; Assembly listing for method BenchmarkDotNet.Engines.GcStats:ToOutputLine():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #48 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] str x0, [fp, #0x58] G_M000_IG02: add x0, fp, #48 mov w1, #5 mov w2, #6 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x2C] ldr w1, [fp, #0x2C] add x0, fp, #48 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x28] ldr w1, [fp, #0x28] add x0, fp, #48 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str w0, [fp, #0x24] ldr w1, [fp, #0x24] add x0, fp, #48 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] add x0, fp, #48 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x10] ldr x1, [fp, #0x10] add x0, fp, #48 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 588 1426: JIT compiled BenchmarkDotNet.Engines.GcStats:ToOutputLine() [Tier0, IL size=154, code size=588] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults:get_ThreadingStats():BenchmarkDotNet.Engines.ThreadingStats:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] str x8, [fp, #0x10] G_M000_IG02: ldr x0, [fp, #0x18] ldr x1, [fp, #0x10] ldp x2, x3, [x0, #0x38] stp x2, x3, [x1] ldr x2, [x0, #0x48] str x2, [x1, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 48 1427: JIT compiled BenchmarkDotNet.Engines.RunResults:get_ThreadingStats() [Tier0, IL size=7, code size=48] ; Assembly listing for method BenchmarkDotNet.Engines.ThreadingStats:get_Empty():BenchmarkDotNet.Engines.ThreadingStats ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x30]! mov fp, sp str x8, [fp, #0x28] G_M000_IG02: stp xzr, xzr, [fp, #0x10] str xzr, [fp, #0x20] add x0, fp, #16 mov x1, xzr mov x2, xzr mov x3, xzr movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr x4, [x4] blr x4 ldr x0, [fp, #0x28] ldp x1, x2, [fp, #0x10] stp x1, x2, [x0] ldr x1, [fp, #0x20] str x1, [x0, #0x10] G_M000_IG03: ldp fp, lr, [sp], #0x30 ret lr ; Total bytes of code 84 1428: JIT compiled BenchmarkDotNet.Engines.ThreadingStats:get_Empty() [Tier0, IL size=12, code size=84] ; Assembly listing for method BenchmarkDotNet.Engines.ThreadingStats:Equals(BenchmarkDotNet.Engines.ThreadingStats):bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x40]! mov fp, sp str x0, [fp, #0x38] str x1, [fp, #0x30] G_M000_IG02: ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x28] ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x28] cmp x0, x1 bne G_M000_IG04 ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x20] cmp x0, x1 bne G_M000_IG04 ldr x0, [fp, #0x38] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x0, [fp, #0x30] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 ldr x1, [fp, #0x18] cmp x0, x1 cset x0, eq G_M000_IG03: ldp fp, lr, [sp], #0x40 ret lr G_M000_IG04: mov w0, wzr G_M000_IG05: ldp fp, lr, [sp], #0x40 ret lr ; Total bytes of code 228 1429: JIT compiled BenchmarkDotNet.Engines.ThreadingStats:Equals(BenchmarkDotNet.Engines.ThreadingStats) [Tier0, IL size=48, code size=228] ; Assembly listing for method BenchmarkDotNet.Engines.ThreadingStats:ToOutputLine():System.String:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #48 movi v16.16b, #0 stp q16, q16, [x9] str xzr, [x9, #0x20] str x0, [fp, #0x58] G_M000_IG02: add x0, fp, #48 mov w1, #3 mov w2, #4 movz x3, #0xD1FFAB1E movk x3, #0xD1FFAB1E LSL #16 movk x3, #0xD1FFAB1E LSL #32 ldr x3, [x3] blr x3 add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x28] ldr x1, [fp, #0x28] add x0, fp, #48 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x20] ldr x1, [fp, #0x20] add x0, fp, #48 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x58] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] add x0, fp, #48 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 add x0, fp, #48 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x60 ret lr ; Total bytes of code 404 1430: JIT compiled BenchmarkDotNet.Engines.ThreadingStats:ToOutputLine() [Tier0, IL size=104, code size=404] ; Assembly listing for method BenchmarkDotNet.Engines.RunResults:get_ExceptionFrequency():double:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr d0, [x0, #0x08] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1431: JIT compiled BenchmarkDotNet.Engines.RunResults:get_ExceptionFrequency() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Autogenerated.Runnable_0:__TrickTheJIT__():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str xzr, [fp, #0x10] str x0, [fp, #0x18] G_M000_IG02: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 bl CORINFO_HELP_NEWSFAST str x0, [fp, #0x10] ldr x0, [fp, #0x10] mov w1, #123 movz x2, #0xD1FFAB1E movk x2, #0xD1FFAB1E LSL #16 movk x2, #0xD1FFAB1E LSL #32 ldr x2, [x2] blr x2 ldr x0, [fp, #0x10] mov w1, wzr mov w2, #10 ldr x3, [fp, #0x10] ldr x3, [x3] ldr x3, [x3, #0x40] ldr x3, [x3, #0x30] blr x3 ldr x1, [fp, #0x18] str w0, [x1, #0x38] ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 136 1432: JIT compiled BenchmarkDotNet.Autogenerated.Runnable_0:__TrickTheJIT__() [MinOpts, IL size=28, code size=136] ; Assembly listing for method BenchmarkDotNet.Autogenerated.Runnable_0:__ForDisassemblyDiagnoser__():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr w0, [x0, #0x38] cmp w0, #11 bne G_M000_IG03 ldr x0, [fp, #0x18] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 60 1433: JIT compiled BenchmarkDotNet.Autogenerated.Runnable_0:__ForDisassemblyDiagnoser__() [MinOpts, IL size=17, code size=60] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:Dispose():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; fully interruptible G_M000_IG01: stp fp, lr, [sp, #-0x60]! mov fp, sp add x9, fp, #24 movi v16.16b, #0 stp q16, q16, [x9] stp xzr, xzr, [x9, #0x20] str xzr, [x9, #0x30] add x1, sp, #96 str x1, [fp, #0x58] str x0, [fp, #0x50] G_M000_IG02: ldr x0, [fp, #0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x40] ldr x0, [fp, #0x40] str x0, [fp, #0x38] ldr x0, [fp, #0x40] cbnz x0, G_M000_IG03 b G_M000_IG04 G_M000_IG03: ldr x0, [fp, #0x38] ldr x0, [x0, #0x08] ldr x1, [fp, #0x38] ldr x1, [x1, #0x18] blr x1 G_M000_IG04: b G_M000_IG05 G_M000_IG05: ldp fp, lr, [sp], #0x60 ret lr G_M000_IG06: stp fp, lr, [sp, #-0x20]! add x3, fp, #96 str x3, [sp, #0x18] G_M000_IG07: str x0, [fp, #0x30] ldr x0, [fp, #0x30] str x0, [fp, #0x48] ldr x0, [fp, #0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x20] ldr x0, [fp, #0x20] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 ldr x0, [fp, #0x50] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] blr x1 str x0, [fp, #0x28] ldr x0, [fp, #0x48] ldr x1, [fp, #0x48] ldr x1, [x1] ldr x1, [x1, #0x40] ldr x1, [x1, #0x20] blr x1 str x0, [fp, #0x18] ldr x1, [fp, #0x18] ldr x0, [fp, #0x28] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 ldr x2, [x11] blr x2 adr x0, [G_M000_IG05] G_M000_IG08: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 304 1434: JIT compiled BenchmarkDotNet.Engines.Engine:Dispose() [Tier0, IL size=56, code size=304] ; Assembly listing for method BenchmarkDotNet.Engines.Engine:get_GlobalCleanupAction():System.Action:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x48] G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 28 1435: JIT compiled BenchmarkDotNet.Engines.Engine:get_GlobalCleanupAction() [Tier0, IL size=7, code size=28] ; Assembly listing for method BenchmarkDotNet.Autogenerated.Runnable_0+<>c:<.ctor>b__3_0():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 20 1436: JIT compiled BenchmarkDotNet.Autogenerated.Runnable_0+<>c:<.ctor>b__3_0() [Tier0, IL size=1, code size=20] ; Assembly listing for method BenchmarkDotNet.Engines.HostExtensions:AfterAll(BenchmarkDotNet.Engines.IHost) ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] movz x11, #0xD1FFAB1E movk x11, #0xD1FFAB1E LSL #16 movk x11, #0xD1FFAB1E LSL #32 mov w1, #4 ldr x2, [x11] blr x2 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 48 1437: JIT compiled BenchmarkDotNet.Engines.HostExtensions:AfterAll(BenchmarkDotNet.Engines.IHost) [Tier0, IL size=8, code size=48] ; Assembly listing for method System.Object:.ctor():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; No PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 16 1438: JIT compiled System.Object:.ctor() [Tier1, IL size=1, code size=16] ; Assembly listing for method System.SZGenericArrayEnumeratorBase:MoveNext():bool:this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; PGO data available, but IL did not match ; 0 inlinees with PGO data; 1 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: ldr w1, [x0, #0x10] add w1, w1, #1 ldr x2, [x0, #0x08] ldr w2, [x2, #0x08] cmp w1, w2 blo G_M000_IG05 G_M000_IG03: str w2, [x0, #0x10] mov w0, wzr G_M000_IG04: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG05: str w1, [x0, #0x10] mov w0, #1 G_M000_IG06: ldp fp, lr, [sp], #0x10 ret lr ; Total bytes of code 64 1439: JIT compiled System.SZGenericArrayEnumeratorBase:MoveNext() [Tier1, IL size=44, code size=64] ; Assembly listing for method System.MulticastDelegate:CtorClosed(System.Object,long):this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; optimized using Static PGO ; fp based frame ; partially interruptible ; with Static PGO: edge weights are valid, and fgCalledCount is 866504 G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: cbz x1, G_M000_IG04 add x14, x0, #8 mov x15, x1 bl CORINFO_HELP_ASSIGN_REF str x2, [x0, #0x18] G_M000_IG03: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG04: movz x0, #0xD1FFAB1E movk x0, #0xD1FFAB1E LSL #16 movk x0, #0xD1FFAB1E LSL #32 ldr x0, [x0] blr x0 brk_windows #0 ; Total bytes of code 60 1440: JIT compiled System.MulticastDelegate:CtorClosed(System.Object,long) [Tier1 with Static PGO, IL size=23, code size=60] ; Assembly listing for method System.Number+Grisu3:BiggestPowerTen(uint,int,byref):uint ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-1 compilation ; optimized code ; fp based frame ; partially interruptible ; PGO data available, but IL did not match ; 0 inlinees with PGO data; 2 single block inlinees; 0 inlinees without PGO data G_M000_IG01: stp fp, lr, [sp, #-0x10]! mov fp, sp G_M000_IG02: add w1, w1, #1 mov w3, #0xD1FFAB1E mul w1, w1, w3 asr w1, w1, #12 cmp w1, #10 bhs G_M000_IG06 ubfiz x3, x1, #2, #32 movz x4, #0xD1FFAB1E movk x4, #0xD1FFAB1E LSL #16 movk x4, #0xD1FFAB1E LSL #32 ldr w3, [x3, x4] cmp w0, w3 bhs G_M000_IG04 G_M000_IG03: sub w1, w1, #1 cmp w1, #10 bhs G_M000_IG06 ubfiz x3, x1, #2, #32 ldr w3, [x3, x4] G_M000_IG04: add w0, w1, #1 str w0, [x2] mov w0, w3 G_M000_IG05: ldp fp, lr, [sp], #0x10 ret lr G_M000_IG06: bl CORINFO_HELP_RNGCHKFAIL brk_windows #0 ; Total bytes of code 108 1441: JIT compiled System.Number+Grisu3:BiggestPowerTen(uint,int,byref) [Tier1, IL size=60, code size=108] ; Assembly listing for method BenchmarkDotNet.Engines.AnonymousPipesHost:Dispose():this ; Emitting BLENDED_CODE for generic ARM64 CPU - Windows ; Tier-0 compilation ; MinOpts code ; fp based frame ; partially interruptible G_M000_IG01: stp fp, lr, [sp, #-0x20]! mov fp, sp str x0, [fp, #0x18] G_M000_IG02: ldr x0, [fp, #0x18] ldr x0, [x0, #0x08] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 ldr x0, [fp, #0x18] ldr x0, [x0, #0x10] movz x1, #0xD1FFAB1E movk x1, #0xD1FFAB1E LSL #16 movk x1, #0xD1FFAB1E LSL #32 ldr x1, [x1] ldr wzr, [x0] blr x1 G_M000_IG03: ldp fp, lr, [sp], #0x20 ret lr ; Total bytes of code 84 1442: JIT compiled BenchmarkDotNet.Engines.AnonymousPipesHost:Dispose() [Tier0, IL size=23, code size=84]